WITH HIERARCHICAL LIFTING STAGES

Technical Field

The invention relates to the field of encoding for parity-check codes, in particular high-speed encoding for low-density parity check (LDPC) codes.

Background and State of the Art

Linear codes over a finite field can be defined as the null space (or kernel) of a parity-check matrix (PCM) H or, equivalently, as the span of a generator matrix G.

Low-density parity-check (LDPC) codes are linear codes defined by sparse PCMs and are known for their excellent error correction capability. LDPC decoding usually relies upon belief propagation over the bipartite graph associated with the PCM and, due to the sparseness of H, has linear complexity in the word length.

In the following, it will be useful to refer to the two sub-matrices H _t and H ₂ of the PCM, defined by the relation

H = [//, H ₂ ], (1) where H ₁ and H ₂ have size (n - k) x k and (n— k) x (n— k), respectively. The positive integer n denotes a block length of a code word, and the positive integer k denotes a block length of an input information word.

A natural encoding algorithm of linear codes, and therefore also of LDPC codes, relies on their representation via the generator matrix G a code word of size n is obtained by multiplying an input information row-vector of size k by the generator matrix of size k x n. Unfortunately, a sparse PCM H does not imply a sparse generator matrix G and, therefore, for a generic, randomly constructed LDPC code, encoding, in contrast to belief propagation decoding, has quadratic complexity in the code word length. In practice, encoding represents a major hurdle to the implementation of generic random LDPC codes. T. J. Richardson and R. L. Urbanke in their paper“Efficient encoding of low-density parity- check codes,” published in 2001 in the IEEE Transactions on Information Theory, vol. 47, no. 2, pages 638-656, propose to bring the submatrix H ₂ into an approximate lower triangular form by performing row and column permutations only of the PCM, which do not alter its sparseness. The resulting encoding complexity is linear except for a quadratic term with a small coefficient. A disadvantage of this method is that column permutations lead to non- systematic encoding. Additionally, the resulting hardware architectures are not completely regular and do not scale favorably at high throughput rates.

A different research trend considers encoding algorithms based on the LU factorization of the sub-matrix H ₂ or its inverse transpose (f/J) ^-1 . In particular, A. Mahdi and V. Paliouras in the paper“A low complexity-high throughput QC-LDPC encoder”, published in the IEEE

Transactions on Signal Processing, vol. 62, no. 10, pages 2696-2708, 2014, propose the use of recursively-constructed quasi-cyclic (QC) LDPC codes to achieve low-encoding complexity.

In view of the prior art, what is needed is an encoding method and system that reduces the encoding complexity and allows for an efficient hardware architecture, in particular a hardware architecture that reduces the number of read and write accesses to memory.

Overview of the Invention

This objective is addressed with an encoding method according to independent claim l, and an encoding system according to independent claim n. The dependent claims relate to preferred embodiments.

In a first aspect, the invention relates to an encoding method for a parity-check code, wherein the encoding is based on a parity check matrix that comprises at least two sub-matrices, wherein at least one of the sub-matrices is a triangular matrix. The parity check matrix H is a (n - k) x n matrix, wherein n denotes a block length of a code word and k denotes a block length of an input word, and wherein the parity check matrix H can be represented in the form

H = [H ₁ H ₂ ] (2) wherein H is a (n-k) x k matrix, and H ₂ is a triangular (n-k) x (n-k) matrix. The method comprises generating the parity check matrix by means of iterative lifting of smaller parity check matrices.

A parity check matrix with a triangular sub-matrix allows for a particularly efficient encoding, with a coding complexity that scales linearly in the length of the information blocks to be encoded. Moreover, the structure of the parity check matrix allows for an efficient

implementation that minimizes the read and write accesses to memory of the encoding circuit,

A triangular matrix, in the sense of the present disclosure, may be a matrix in which all the matrix entries above the diagonal entries, or below the diagonal entries are“o” entries.

The triangular matrix may be a matrix having an equal number of rows and columns, wherein the number of rows and columns may be any integer value > 2.

Iterative lifting allows to preserve the triangular structure of the sequence of parity check matrices, and hence allows for a particularly efficient iterative code generation.

According to an embodiment, iterative lifting comprises: providing a first parity check matrix, wherein the first parity check matrix comprises a first sub-matrix that is triangular; and generating a second parity check matrix from the first parity check matrix, wherein the second parity check matrix is larger than the first parity check matrix and is obtained from the first parity check matrix by replacing zero entries of the first parity check matrix with zero matrices, and replacing non-zero entries of the first parity check matrix with permutation matrices.

A permutation matrix, in the sense of the present disclosure, may be a matrix with exactly one“l” entry in each row and column, and“o” entries elsewhere.

In particular, some or all of the permutation matrices may be circulant matrices.

A circulant matrix, in the sense of the present disclosure, may be a permutation matrix in which each row vector or each column vector is cyclically rotated by one element relative to the preceding row vector or column vector, respectively.

In the iterative lifting, non-zero diagonal entries of the first sub-matrix may be replaced by identity matrices, so to obtain a second triangular sub-matrix. The encoding method may further comprise: generating a third parity check matrix from the second parity check matrix, wherein the third parity check matrix is larger than the second parity check matrix and is obtained from the second parity check matrix by replacing zero entries of the second parity check matrix with zero matrices, and replacing non-zero entries of the second parity check matrix with permutation matrices, in particular circulant matrices.

Non-zero diagonal entries of the second sub-matrix may be replaced by identity matrices.

This lifting process may be repeated for the forth and any further parity check matrix. In this way, the final parity check matrix for the parity check code may be efficiently generated iteratively from smaller parity check matrices.

In the context of the present disclosure, the number of rows, or number of columns of the permutation matrix, or circulant matrix employed in the lifting may be called a lifting factor.

According to an embodiment, the encoding has a degree of parallelism that corresponds to a product of a plurality of lifting factors, in particular a product of a subset of the lifting factors.

The subset of the lifting factors may comprise all the lifting factors including and beyond the m-th lifting factor, for any integer m > 2.

According to an embodiment, the parity-check code is a systematic code.

A systematic code, in the sense of the present disclosure, may denote a code in which the information symbols are embedded in the code words.

According to an embodiment, the encoding comprises a parallel processing of a plurality of rows of the parity check matrix, in particular a parallel processing of all rows of the parity check matrix. In particular, the encoding may comprise a parallel processing in a plurality of encoding paths, wherein each encoding path pertains to a row of the parity check matrix.

According to an embodiment, the encoding comprises permuting a plurality of input symbols.

The encoding method according to the present disclosure may be implemented in an encoding circuit, which may be a circuit comprising hardware elements and/or software elements. In particular, the encoding circuit may comprise a combinational logic circuit or switching logic circuit. In some embodiments, the encoding circuit may comprise a memory element, such as a RAM element.

The encoding may comprise applying a first plurality of permutations to an input symbol, the first plurality of permutations pertaining to a first plurality of lifting stages, in particular a first plurality of lifting stages consisting of all lifting stages including and beyond the m-th lifting stage, for an integer m > 2.

According to an embodiment, the first plurality of permutations are applied by means of a combinational logic circuit, or a switching logic circuit.

In an example, the permuting is realized by means of barrel shifters.

The encoding may comprises an accumulated addition operation, in particular after a step of permuting a plurality of input symbols.

In an example, the accumulated addition operation comprises a second plurality of permutations pertaining to a second plurality of lifting stages, in particular a second plurality of lifting stages consisting of all lifting stages below the m-th lifting stage, for an integer m >

2.

According to an embodiment, the second plurality of lifting stages may be applied by means of a memory element, in particular a RAM element.

The accumulated addition operation may employ a memory with a single read port and a single write port.

Hence, according to an example, the method comprises a hybrid permutation of the input symbols. In particular, the second plurality of permutations corresponding to the lifting stages l to m-i, for an integer m ³ 2, may be implemented by means of the memory element, in particular the RAM element. The first plurality of permutations corresponding to the upper lifting stages including and beyond the m-th lifting stage may be implemented in combinational logic, or switching logic.

The value m > 2 is smaller than the total number of lifting stages, and can be a

predetermined parameter selected depending on the chip performance.

This allows for a particularly efficient and fast encoding, with minimal resources. According to an embodiment, the encoding comprises computing a second plurality of parity check symbols pertaining to a second input block as an accumulated addition operation of a plurality of information symbols pertaining to the second input block and a first plurality of parity check symbols pertaining to a first input block, wherein the first input block in particular precedes the second input block.

In an example, the encoding comprises backfeeding parity check symbols from an output of an encoding circuit to an input of the encoding circuit.

Hence, the encoding circuit according to the present disclosure may generate parity check symbols iteratively based on the parity check symbols obtained for a previous block. This simplifies the encoder architecture, and leads to a particularly efficient coding scheme.

In a second aspect, the disclosure relates to an encoding system, implementing an encoding based on a parity check matrix that comprises at least two sub-matrices, wherein at least one of the sub-matrices is a triangular matrix. The parity check matrix is a (n-k) x n parity check matrix, wherein n denotes a block length of a code word and k denotes a block length of an input word, wherein the parity check matrix can be represented in the form of equation (2), and the encoding system is adapted to generate the parity check matrix by means of iterative lifting of smaller parity check matrices.

The parity check matrix may be a parity check matrix with some or all of the features described above.

The system may comprise an encoding circuit.

According to an embodiment, the encoding system comprises a first plurality of permutator elements adapted to apply a first plurality of permutations to an input symbol, the first plurality of permutations pertaining to a first plurality of lifting stages.

In particular, the first plurality of lifting stages may consist of all lifting stages including and beyond the m-th lifting stage, for an integer m ³ 2.

According to an example, the first plurality of permutator elements may comprise a combinational logic circuit, or switching logic circuit.

According to an embodiment, the encoding system may comprise a plurality of accumulator elements adapted to perform an accumulated addition operation. In particular, the plurality of accumulator elements may be located downstream of the first plurality of permutator elements.

According to an example, the plurality of accumulator elements comprises a respective second plurality of permutator elements.

In an example, the second plurality of permutator elements may be adapted to apply a second plurality of permutations pertaining to a second plurality of lifting stages, in particular a second plurality of lifting stages consisting of all lifting stages below the m-th lifting stage, for an integer m ³ 2

The second plurality of permutator elements may comprise memory elements, in particular RAM elements.

Hence, the encoding system may be adapted to employ the permutation in a hybrid implementation, wherein the functionality of the lower lifting stages is realized in RAM, and the functionality of the upper lifting stages is realized in combinational logic.

According to an embodiment, the encoding system is adapted to compute parity symbols, and backfeed the computed parity symbols to an input of the encoding system.

The backfeeding of parity symbols constitutes an independent aspect of the present disclosure.

In particular, according to a third aspect the invention relates to an encoding system, comprising: an input node for receiving information symbols; and an encoding circuit connected to the input node. The encoding circuit comprises a plurality of permutator elements associated with a plurality of encoding paths; and a plurality of accumulator elements associated with the plurality of encoding paths. The encoding circuit further comprises a feedback path adapted to backfeed output symbols of the encoding circuit to an input of the encoding circuit; and an output node connected to the encoding circuit, wherein the output node is adapted to output codeword symbols.

The encoding system may be adapted to implement the encoding method with some or all of the features described above. According to an embodiment, the plurality of accumulator elements are located downstream from the plurality of permutator elements in the plurality of encoding paths.

In an example, the encoding circuit comprises a row selector element, in particular downstream from the plurality of accumulator elements.

The encoding circuit may be adapted to compute parity symbols.

According to an embodiment that may implement a systematic encoder, the encoding system further comprises a bypass path adapted to provide the information symbols from the input node to the output node.

The encoding system may be adapted to alternatively connect the input node and the feedback path to the input of the encoding circuit, in particular by means of a switch.

According to an embodiment, the permutator elements are adapted to apply a first plurality of permutations pertaining to a first plurality of lifting stages, in particular a first plurality of lifting stages including and beyond the m-th lifting stage, for an integer m > 2.

The permutator elements may comprise a combinational logic circuit, or switching logic circuit.

In an example, the permutator elements comprise barrel shifters.

According to an embodiment, the plurality of accumulator elements are adapted to apply a second plurality of permutations pertaining to a second plurality of lifting stages, in particular a second plurality of lifting stages below the m-th lifting stage, for an integer m ³

2.

According to an embodiment, the plurality of accumulator elements may comprise a second plurality of permutator elements adapted to implement a second plurality of permutations pertaining to a second plurality of lifting stages.

In particular, the second plurality of lifting stages may consist of all lifting stages below the m-th lifting stage, for m > 2.

According to an embodiment, the plurality of accumulator elements are adapted to compute a second plurality of parity symbols pertaining to a second input block of information symbols as an accumulated addition operation of a plurality of information symbols pertaining to the second input block provided from the input note, and a first plurality of parity symbols pertaining to a first input block of information symbols, wherein the first plurality of parity symbols are provided via the feedback path.

Each of the plurality of accumulator elements, or each of the second plurality of permutator elements may comprise a memory element, in particular a RAM element.

Each of the plurality of accumulator elements may comprise a memory with a single read port and a single write port.

Brief Description of the Drawings

The features of the present invention and the numerous advantages associated therewith will be best apparent from a detailed description of example embodiments with reference to the accompanying drawings, in which:

Fig. l is a schematic diagram illustrating a data transmission process that employs an encoding method and system according to an embodiment;

Fig. 2 is a schematic illustration of a lifting procedure that may be employed in an encoding method according to an embodiment;

Fig. 3 is a schematic diagram illustrating an encoder architecture of an encoding system according to an embodiment;

Fig. 4 is a schematic diagram illustrating a permutator element that may be used in an encoding system according to an embodiment;

Fig. 5 is a schematic block diagram of a barrel shifter that that may be used in an encoding system according to an embodiment; and

Fig. 6 is a schematic diagram illustrating an accumulator element that may be used in an encoding system according to an embodiment.

Description of Embodiments In this disclosure, we consider a special class of low density parity check (LDPC) codes that admit linear-complexity encoding, and we describe an efficient hardware architecture for the implementation of suitable high-speed encoders. The encoding method and encoding system maybe employed for the transmission of digital information over optical networks. However, this is merely an example, and in general the encoding techniques according to the present disclosure may be employed for any kind of data storage, data compression, or data transmission over any possible transmission medium.

Fig. l is a schematic illustration of a data transmission system 10 that employs an encoding method and system according to an embodiment.

The data transmission system to comprises an encoding system 12, a transmission channel 14, and a decoding system 16. The encoding system 12 receives input symbols 18, such as a string of digital data bits, and encodes them by means of an encoding method that generates a string of code symbols 20. These code symbols 20 are subjected to the transmission channel 14, which models transmission of the code symbols 20 over a transmission path, such as an optical fibre channel, from a sender station to a receiver station. The transmitted code symbols 22 received at the receiver station maybe subjected to the decoding system 16, which converts them into decoded code symbols 24. Ideally, the decoded code symbols 24 are identical to the input symbols 18, or at least a very close approximation.

In general, the input information may be represented by any kind of symbols, such as any b- ary symbols. However, in the following examples we focus on binary symbols, for the ease of presentation.

We consider a special class of LDPC codes for the encoding system 12 that

• have a parity check matrixH with triangular sub-matrix H ₂ according to Eq. (2), and

• are constructed by applying hierarchical lifting to a protograph.

For this class of codes we describe an encoder architecture suitable for a high-speed low- power very large scale integration (VLSI) implementation, and characterized by

• a degree of parallelism equal to the product of the upper lifting factors, and

• a hybrid implementation of a bit permutation, whereby the functionality of the lower stages is realized in RAM and that of the upper stages is realized in combinational logic (also denoted by switching logic). In contrast to some state-of-the-art solutions that, like ours, exploit structural properties of the PCM, we require the sub-matrix H ₂ to be triangular rather than approximately triangular or dual diagonal. Also, differently from other solutions applicable to quasi-cyclic LDPC codes we do not make use of a LU decomposition. An advantage of our solution lies in the efficient implementation of the bit permutation, which exploits the construction by means of hierarchical lifting to enable high throughput without incurring routing congestion.

By using a protograph approach, we design LDPC code ensembles with triangular H ₂ and excellent performance. The possibility of using a PCM with a triangular sub-matrix H ₂ without suffering from performance penalties leads to significant simplifications in the encoding algorithm.

Code Construction

Let us denote by the protomatrix associated with the considered protograph, and let us introduce the sub-matrices of size (zzf ⁰⁾ —

(rd° ⁾ — /d° ⁾ ), respectively, such that

We pose the following constraints on the structure of

• The diagonal elements have value l;

• The elements above the diagonal are zero, i.e., the matrix is lower triangular.

Alternatively, an upper triangular matrix could be used.

The proto matrix H ⁽⁰⁾ or, equivalently, the protograph can be designed according to customary techniques, as e.g. density evolution.

Subsequently, we apply l hierarchical lifting stages to the protograph with a similar procedure to that described by N. Miladinovic and M. Fossorier in“Systematic recursive construction of LDPC codes,” IEEE Communications Letters, vol. 8, no. 5, 2004, pages 302-304. At stage z (z = o, 1, ..., I- 1) we use cyclic permutation matrices and zero-matrices of size <7® x q® to lift the protomatrix and obtain the new protomatrix

and

The protomatrix obtained after the last lifting stage coincides with the desired PCM

Fig. 2 provides a graphical exemplification of the lifting procedure at two successive stages. At the lifting stage i an entry /i® = 1 of the protomatrix //® is replaced by a qh ⁾ c q ^(l circulant matrix. Subsequently, at the lifting stage i + 1, a resulting entry = 1 is replaced in turn by a c q( ^l+1 ) circulant matrix.

At the lifting stage o each entry equal to any integer v > 1 is replaced by the sum of v

different circulant matrices of size x q ⁽ -°\ With the first lifting stage we take care of removing all multiple edges from the protograph, i.e., all entries with value larger than one from the protomatrix. To this end, q ⁽⁰⁾ may be equal to or larger than the maximum entry of h° ⁾ . If the initial protograph has no parallel edges, this initial step may be skipped, i.e. q ^m may be set to one.

We may constrain the lifting procedure described above by adopting at the i-th stage (i = o, l, ..., l-i) zero-shift permutation matrices (i.e. identity matrices) for the diagonal elements of f/® . This condition simplifies encoding without affecting the code performance.

The product of the lifting factors employed at the lifting stages i, 2, ..., /-l

DoP _dec = P¾® (8) determines the maximum natural degree of parallelism (DoP) in the VSLI implementation of the decoder and, therefore, for a fixed clock frequency, its maximum throughput.

Encoder architecture

For any throughput target, the encoder system 12 can be implemented with a lower DoP than the decoder because, differently from belief propagation, the encoding algorithm is not iterative. We choose the DoP of the encoder as the product of the upper l— m (0 < m < i) lifting stages:

DoP _enc = rfei ® £ DoP _dec . (9)

The patent application WO2004/ 077733A2 entitled“Method and Apparatus for Performing Low-Density Parity-Check (LDPC) Code Operations using a Multi-Level Permutation” by Tom Richardson proposes a method to implement different degrees of parallelism, e.g. between encoder and decoder. Whereas the method of WO2004/077733A2 makes use of non-cyclic permutations that can be factorized in two permutation operations performed on equally sized vectors, our method relies on a hierarchical lifting, which induces a series of cyclic permutations with increasingly finer granularity.

The triangular structure of H ₂ , enforced by the code construction, results in the following simple encoding procedure. The i-th parity bit of the LDPC code (i = 0, 1, ... , n® - /c®— 1) is computed as the accumulated exclusive or (XOR) operation of the information bits and, for i ¹ 0, the previous parity bits involved in the i -th row of the PCM H. At each step the encoder must keep track of the XOR-accumulated values. Therefore, the state of the encoder consists of one bit per each row of the PCM, i.e., in total n®— /c® bits that are updated via XOR accumulation.

We mention in passing that for non-binary LDPC codes the XOR accumulation of selected bits must be replaced by the multiplication of the variables by their corresponding coefficients and the subsequent accumulated addition in the respective Galois field.

The proposed architecture implements systematic encoding. During an“information phase”, the information bits enter the encoder, are used to update the state accumulators, and are forwarded unmodified to the output. Subsequently, during a“parity phase”, the accumulated XOR bits of each row are sent to the output as parity bits and fed back to the input of the encoder to update the XOR accumulators of the following rows.

Fig. 3 schematically shows a block diagram of an exemplary systematic LDPC encoder system 12. Every connector in the diagram represents a bus of width DoP _enc .

The input information bits 18 to be encoded are received at an input node 26, and are forwarded towards an output node 28 via a bypass line 30. Moreover, the input bits 18 are copied and provided, via an input switch unit 32, to an encoding circuit 34 that is adapted to compute the parity bits for the LDPC.

As further illustrated in Fig. 3, the encoding circuit 34 comprises - /< ⁽¹⁾ parallel encoding paths 36 ₁ to 30 _n-k , each consisting of a respective permutator element 38 ₁ to 38 _n-k

implemented in combinational logic, and an accumulator element 4O ₁ to 40 _n-k downstream of the respective permutator element 38 ₁ to 38 _n-k . Here and in the description that follows, we use shorthand notation n-k for the subscripts nW-k ^(l) etc., for ease of notation. A row selector 42 selects among the encoding paths 36 ₁ to 36 _n-k , and provides the respective parity bits 44 to a combiner switch 46 at the output node 28, where the parity bits 44 are combined with the input bits 18 to form the codeword bits 20.

As can be further taken from Fig. 3, the parity bits 44 from the encoding circuit 34 are additionally provided, via a feedback path 48, to the input switch unit 32, which selectively backfeeds them into the encoding circuit 32.

The two switches 32 and 46 in Fig. 3 are configured to route towards their output port the input of the I port during the information phase and the input of the P port during the parity phase.

The combinational permutator elements 38 ₁ to 38 _n-k implements the permutations associated with the lifting stages m, m + 1, ... , l - 1, i.e., the upper l - m lifting stages.

The connections of the input bits 18 with the XOR accumulator elements 40 ₁ to 40 _n -k as well as the connections of the XOR accumulator elements 40 ₁ to 40 _n-k with the output bits 20 depend on the cyclic permutation matrices chosen at each lifting stage for each entry of the protomatrices. In a VLSI implementation of a LDPC encoder system 12, routing generally represents the bottleneck that limits the achievable throughput. The connections between the input/output ports and the processing core are usually implemented via a dedicated permutation block, or“permutator” that dominates the silicon area and therefore the costs of the circuit. In the following we describe a simple permutation architecture for the considered code construction.

We will refer to the rows and columns of the protomatrix H (i = 1, 2, ... , l) as z- rows and z- columns, respectively. During the lifting procedure, each z'-row (z-column) expands to q ^l,J j- rows (/-columns) (J ³ i), respectively, where

In particular, each l-row or l-column expands to DoP _enc rows or columns of the PCM H, respectively. The DoP _enc (information or parity) bits at the output of switch unit 32 correspond to an uz-column, and each path corresponds to a l-row.

Each combinational permutator element 38, such as the combinational permutator elements 38 ₁ to 38 _n -k, can be conveniently realized as a cascade of l— m barrel shifter groups 50 _m - 501- ₁ , as illustrated in Fig. 4. Every _< 7 ^W -i _evei barrel shifter group 50 ₁ (i = m, m + 1, ... , l - 1) comprises _< 7® barrel shifter units 52 ₁ and qh ⁾ combiner units 54 ₁ , and operates on busses of qfd ⁺ⁱ -0 ¾its each by applying a configurable circular permutation. The input bus 56 is initially split into DoP _enc bits that are progressively recombined after each barrel shifter until, eventually, a single output bus 58 of DoP _enc bits is obtained. Although the functionality of the whole combinational permutator 38 is purely combinational, pipeline stages can be inserted where required to achieve timing closure in the VLSI implementation without changing the principle of operation.

Barrel shifters are well-known building blocks of digital circuits. For the sake of

completeness, the block diagram of a generic 2 ^s -level barrel shifter (for a positive integer S) is shown in Fig. 5. The connectors represent busses of appropriate width. The circuit consists of multiple cascaded stages 6q _ί : The i-th stage (i = 0,1, ... , s— 1) can operate in bypass mode or can rotate cyclically the input signal by 2 ^l positions. For more details we refer to the tutorial paper“Design alternatives for barrel shifters,” by M. R. Pillmeier et al. published in

December 2002 in the SPIE Proceedings, vol. 4791.

Besides XOR accumulation, the accumulator elements 4O ₁ to 40 _n-k in Fig. 3 implement, by means of the addressing scheme, the permutations associated with the lifting stages

1, 2, ... , m— 1, i.e. the lower m— 1 lifting stages. The lifting stage 0, which is used to remove the parallel edges from the initial protograph, does not correspond to a permutation function and is implicitly implemented through the use of rather than rd° ⁾ parallel paths in the encoder.

Fig. 6 illustrates an exemplary implementation of an accumulator element 40, such as one of the accumulator elements 4O ₁ to 40 _n-k in Fig. 3. The i-th accumulator 4O ₁ (i = -

/< ⁽¹⁾ - 1) stores the DoP _enc qi ¹ ·™ ⁾ state bits associated with the i-th l-row. All accumulators together hence store = 71® - /<® state bits.

The accumulator element 40 comprises a data input node 62 adapted to receive input data, such as from the permutator element 38, and data output node 64. As can be taken from Fig. 6, the accumulator element 40 further comprises an XOR gate element 66, a memory element 68, a delay element 70, and an address generator element 72.

By recalling that each l-row corresponds to m- rows and that each m- row is associated with DoP _enc state bits, we organize the accumulator storage in qD.w ⁾ _{wor(js 0} f DoP _enc bits each, whereby each word corresponds to an m- row. It is now important to realize that • the DoP _enc bits transported at any given time by the input bus belong to the same m- column;

• due to the use of (circular) permutation matrices in the lifting procedure, each m- column intersects at most one of the qi ¹ ·™) m- rows associated with a given l-row.

This implies that, at any given time, at most one of the stored words must be updated.

This fact allows us to implement the storage via a memory element 68 with a single read-port 74 and a single write-port 76 without access conflicts, such as a standard two-port random- access memory (RAM). Both the write port 74 and the read port 76 may have separated data (WD and RD), address (WA and RA) and enable (WE and RE) signals. At any given time the i-th accumulator 40 ₁ (for each i = 0, 1, ... , n ⁽¹⁾ - k ⁽¹⁾ - 1) reads, updates and writes at most a single set of DoP _enc state bits, corresponding to one of the m-rows associated with the i- th l-row.

The index of the intersecting m- row (between 0 and - 1) depends on the circular permutation matrices chosen at the lower m - 1 lifting stages. By recalling that a qd ⁾ c q ⁽ 0 circulant matrix is univocally specified by a shifting factor in {0, 1, ... , - l}, we can establish a natural indexing of the m- rows. To this end we sort the m- rows associated with the i-th l-row in lexicographic order according to the shift factors used at the lifting stages m - 1, m - 2, ... , 1. Of course, different indexing can be alternatively used.

The architecture and operation of the accumulator element will now be described in greater detail with further reference to Fig. 6.

A first input node of the XOR gate element 66 is connected to the input node 62, and, depending on the switch setting of the input switch 32, receives the permuted information bits (in the information phase) or parity bits (in the parity phase) from the permutator element 38. A second input of the XOR gate element 66 is connected, via an accumulator feedback path 78, to the read data (RD) output port of the memory element 68. The feedback path 78 comprises a reset switch unit 80 adapted to reset the accumulator 40 at the start of each new code word. The XOR gate element 66 computes the“exclusive or” of the signals received from the input node 62 and via the accumulator feedback path 78, and provides the result to the write data (WD) input port of the memory element 68.

The delay element 70, which accounts for the latency of the RAM, is connected to the read address (RA) output port of the memory element 68 and the write address (WA) input of the memoiy element, and may be employed to derive the write address from the read address. The addressing scheme within the accumulator 40 implements the functionality of the lower m-i stages of the permutation. The address generator 72 is connected to the memory element 68 and the delay element 70, and may consist of a linear counter and a look-up table (not shown in Fig. 6). The linear count may be remapped to the actual RAM addresses contained in the look-up table and generated from the circular shift factors of the permutation matrices according to the chosen indexing.

Due to the sparse nature of the H^ ¹⁾ protomatrix, a 1-column does not necessarily intersect each 1-row. Accordingly, it is possible that the processed m-column does not intersect any of the c _jf D. ^m) m- rows associated with the i-th accumulator (i = 0, 1, ... , — 1). In this case the write enable of the memory element 68 can be used to prevent updating the accumulator state. A clock gating technique can be used to disable the accumulators 40 during the idle periods and save power consumption.

The row selector 42 in Fig. 3 is used during the parity phase to route the content of the XOR accumulators 4O ₁ to 40 _n-k to the output, where it provides the parity bits 44. We recall that in the code construction, we used at the i-th stage (i = o, 1, ..., Z-i) zero-shift permutation matrices (i.e. identity matrices) for the diagonal elements of H^. As a consequence, the accumulated bits are read in the natural (“unpermutated”) order, i.e., the r-th parity bit (r = 0,1, ... , n® - /i® - 1) coincides with the content of the XOR accumulator 40 _r associated with the r-th row of the PCM H. Further, since not only the final matrix H _z , but also each intermediate matrix and, in particular, is triangular, the DoP _enc parity bits belonging to the same m-column are mutually independent. This circumstance allows us to compute DoP _e n _c parity bits simultaneously rather than sequentially and enables the desired degree of parallelism.

The encoding system 12 of Fig. 3 can be easily adapted to encode in time sharing L block- interleaved LDPC codewords, whereby at any time slot i the code word (i mod L) is processed. To this end it is sufficient to expand the storage in each accumulator RAM to L qD' ^m) words of DoP _enc bits each. Accordingly, the RAM address depends not only on the circular permutation matrices chosen at the lower m - i lifting stages but also on the code word index (t mod L). We mention that the time sharing approach besides improving the burst error tolerance of the forward error correction (FEC) scheme, increases the number of allowable latency cycles in the feedback loops 48, 78 in Figs. 3 and 6 and, thus, simplifies the VLSI implementation. In the examples described above with reference to Figs. 3 to 6, the lifting procedure has been constrained by requiring zero-shift permutation matrices, i.e. identity matrices, for the diagonal elements. This constraint leads to a particularly efficient implementation and architecture of the encoder structure, but is not an essential constraint. If the constraint is dropped, the encoding method may proceed similarly. For instance, an additional permutator element may be added downstream of the row selector 42 in the encoder architecture of Fig.

3.

The description of the embodiments and the drawings merely serve to illustrate the method and system according to the invention, but should not be understood to imply any limitation. The scope of the invention is to be determined from the appended claims.

Reference Signs

10 data transmission system

12 encoding system

14 transmission channel

i6 decoding system

i8 input symbols

20 code symbols

22 transmitted code symbols

24 decoded code symbols

26 input node

28 output node

30 bypass line

32 input switch

34 encoding circuit

361 - 36n-k encoding paths

38 permutator element

81 - 3811-k permutator elements of encoding paths 36 ₁ to 36 _n-k 0 accumulator element

0 - 40n-k accumulator elements of encoding paths 36 ₁ to 36 _n-k 2 row selector

4 parity bits

6 combiner switch

8 feedback path

0m ^— 50l- barrel shifter groups

2 barrel shifter

2m ^— 52l-i barrel shifter units

4m ^— 54l-i combiner units

6 input bus of permutator element 38

8 output bus of permutator element 38

oi stages of barrel shifter 52

2 data input node of accumulator element 40

4 data output node of accumulator element 40 XOR gate element of accumulator element 40

memory element of accumulator element 40

delay element of accumulator element 40

address generator element of accumulator element 40 input port and related control ports of memory element 68 output port and related control ports of memory element 68 feedback path of accumulator element 40

reset switch unit