Title:
PARALLEL RESIDUE ARTHMETIC OPERATION UNIT AND PARALLEL RESIDUE ARTHMETIC OPERATING METHOD
Document Type and Number:
WIPO Patent Application WO/2008/023684
Kind Code:
A1
Abstract:
A parallel residue arithmetic operation unit is provided to make it possible to
reduce processing delay, and to make an additional multiplier or a residue arithmetic
circuit unnecessary, so that a circuit can become small in size. In the parallel
residue arithmetic operation unit, a parallel CRC calculation circuit (100)
is comprised of input terminals (101)-(104) to which input data are divided into
a plurality of sub-blocks and the sub-blocks are input in parallel, an initial
value generating unit (110) for generating a part CRC corresponding to the forefront
of each sub-block as an initial value, a part CRC generating unit (111)-(114)
for receiving the part CRC corresponding to the forefront of each sub-block as
the initial value and sequentially generating a residue part CRC in accordance
with a recurrent equation, AND units (121)-(124) for calculating logical multiplications
of part CRC values, and a cumulative adding unit (130) for cumulatively adding
values output from the AND units (121)-(124).
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Inventors:
MOTOZUKA, Hiroyuki (())
Application Number:
JP2007/066156
Publication Date:
February 28, 2008
Filing Date:
August 21, 2007
Export Citation:
Assignee:
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 5718501, JP)
松下電器産業株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 5718501, JP)
松下電器産業株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 5718501, JP)
International Classes:
H03M13/09; H03M13/00
Attorney, Agent or Firm:
WASHIDA, Kimihito (5th Floor, Shintoshicenter Bldg. 24-1, Tsurumaki1-chome, Tama-sh, Tokyo 34, 2060034, JP)
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