Title:
PARAMETER OPTIMIZATION DEVICE, METHOD AND PROGRAM
Document Type and Number:
WIPO Patent Application WO/2019/239820
Kind Code:
A1
Abstract:
The present invention determines the optimal combination of a number of loop developments and a number of circuit parallels, in a high-level synthesis. A circuit synthesis information generation unit 11 sets, as parameter candidates, a plurality of combinations of a number M of loop developments and a number N of circuit parallels, and generates, for each combination, circuit synthesis information 23 indicating a synthesis circuit obtained by high-level synthesis processing. An optimal parameter determination unit 13 calculates, for each piece of generated circuit synthesis information 23, an estimated processing performance P pertaining to the synthesis circuit indicated by the circuit synthesis information 23, and determines the optimal combination of a number M of loop developments and a number N of circuit parallels on the basis of the circuit synthesis information 23 for which the maximum estimated processing performance PMAX is obtained.
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Inventors:
YOSHIDA SYUHEI (JP)
UKON YUTA (JP)
YAMAZAKI KOJI (JP)
NITTA KOYO (JP)
UKON YUTA (JP)
YAMAZAKI KOJI (JP)
NITTA KOYO (JP)
Application Number:
PCT/JP2019/020104
Publication Date:
December 19, 2019
Filing Date:
May 21, 2019
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE (JP)
International Classes:
G06F17/50
Domestic Patent References:
| WO2018066074A1 | 2018-04-12 |
Foreign References:
| JP2018041301A | 2018-03-15 | |||
| JP2002269162A | 2002-09-20 | |||
| JP2015095130A | 2015-05-18 |
Attorney, Agent or Firm:
YAMAKAWA, Shigeki et al. (JP)
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