Title:
PASSIVATION LAYER MANUFACTURING METHOD, HIGH-VOLTAGE SEMICONDUCTOR POWER DEVICE AND FRONT ELECTRODE
Document Type and Number:
WIPO Patent Application WO/2018/014792
Kind Code:
A1
Abstract:
A planar terminal passivation method, a semiconductor power device and a front electrode. The method comprises successively depositing a dielectric layer (5), a glass passivation layer (6) and a polyimide protection layer (8) onto a semiconductor power device to form a plurality of composite passivation layers. The semiconductor power device is manufactured by using this method.
Inventors:
JIN RUI (CN)
PAN YAN (CN)
WEN JIALIANG (CN)
ZHAO YAN (CN)
GAO MINGCHAO (CN)
WU DI (CN)
HE YANQIANG (CN)
LIU JIANG (CN)
CUI LEI (CN)
PAN YAN (CN)
WEN JIALIANG (CN)
ZHAO YAN (CN)
GAO MINGCHAO (CN)
WU DI (CN)
HE YANQIANG (CN)
LIU JIANG (CN)
CUI LEI (CN)
Application Number:
PCT/CN2017/093002
Publication Date:
January 25, 2018
Filing Date:
July 14, 2017
Export Citation:
Assignee:
GLOBAL ENERGY INTERCONNECTION RES INSTITUTE (CN)
International Classes:
H01L21/285; H01L21/56; H01L23/29; H01L23/31; H01L23/48
Foreign References:
| CN106252244A | 2016-12-21 | |||
| CN205845937U | 2016-12-28 | |||
| CN106098572A | 2016-11-09 | |||
| CN104332403A | 2015-02-04 | |||
| CN104201252A | 2014-12-10 | |||
| CN104810283A | 2015-07-29 | |||
| CN103579367A | 2014-02-12 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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