Title:
PATTERN DEFECT INSPECTION METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2006/075687
Kind Code:
A1
Abstract:
In a conventional pattern defect inspection of a complicated shape pattern formed on a reticle or a semiconductor wafer, a plenty of pseudo-defects (actually not defects) have been contained in what has been recognized as defects. It is necessary to reduce the number of pseudo-defects and significantly reduce the time required for the defect inspection. In a pattern defect inspection method in which an image of pattern to be inspected is compared to an image of a reference pattern so as to detect a defect of the pattern to be inspected, the inspection sensitivity is adjusted according to the pattern shape in the reference pattern.
Inventors:
KUDOU KENJI (JP)
Application Number:
PCT/JP2006/300349
Publication Date:
July 20, 2006
Filing Date:
January 13, 2006
Export Citation:
Assignee:
FUJITSU LTD (JP)
KUDOU KENJI (JP)
KUDOU KENJI (JP)
International Classes:
G01N21/956; G01B11/30; G03F1/84; H01L21/027; H01L21/66
Foreign References:
| JP2002532760A | 2002-10-02 | |||
| JPS58147114A | 1983-09-01 | |||
| JPS6186639A | 1986-05-02 | |||
| JP2002244275A | 2002-08-30 | |||
| JP2004191297A | 2004-07-08 | |||
| JP2004045066A | 2004-02-12 | |||
| JP2005215400A | 2005-08-11 |
Attorney, Agent or Firm:
Yokoyama, Junichi c/o FUJITSU LIMITED (1-1 Kamikodanaka 4-chome, Nakahara-k, Kawasaki-shi Kanagawa, JP)
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