Title:
PHASE ADJUSTING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/1989/005081
Kind Code:
A1
Abstract:
A phase adjusting circuit for forming false synchronizing signals by changing the phase of the synchronizing signal in order to place the picture at the center of the screen on a display unit. This circuit includes a voltage comparator (50) having two input terminals maintained at the same DC potential. One of the input terminals receives, via a DC blocking capacitor (C2), a sawtooth wave signal (P1) obtained by integrating the input synchronizing signal, in order to obtain output pulses each having an edge between input synchronizing pulses. False synchronizing signal generating means (101) and (102) are triggered at the edges of the output pulses to produce a false synchronizing signal different in phase from the input synchronizing signal.
Inventors:
KITAMURA TSUTOMU (JP)
Application Number:
PCT/JP1988/001146
Publication Date:
June 01, 1989
Filing Date:
November 14, 1988
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD (JP)
International Classes:
G09G1/00; G09G1/04; G09G1/16; H03K5/13; H04N3/227; H04N5/04; H04N5/05; H03K5/00; (IPC1-7): H04N5/05
Foreign References:
| JPS61134795A | 1986-06-21 | |||
| JPS6277766A | 1987-04-09 | |||
| JPS61143186U | 1986-09-04 |
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