Title:
PHASE ADJUSTMENT CIRCUIT AND ENDOSCOPE SYSTEM
Document Type and Number:
WIPO Patent Application WO/2021/176629
Kind Code:
A1
Abstract:
A phase adjustment circuit wherein a binarization circuit outputs a binary signal on the basis of the edge of an image signal. A delayed clock signal generation circuit generates a delayed clock signal having a phase delayed by a first delay amount from the phase of a clock signal. A delay time control circuit causes the phase of the binary signal to match the phase of the delayed clock signal by adjusting the first delay amount. A sampling signal generation circuit generates a sampling signal having a phase delayed by a second delay amount from the phase of the clock signal. The second delay amount corresponds to the first delay amount and a phase shift amount based on the clock signal.
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Inventors:
TANAKA TAKANORI (JP)
HIRAIDE SHUZO (JP)
HIRAIDE SHUZO (JP)
Application Number:
PCT/JP2020/009306
Publication Date:
September 10, 2021
Filing Date:
March 05, 2020
Export Citation:
Assignee:
OLYMPUS CORP (JP)
International Classes:
H03H11/16
Foreign References:
| JPH06311154A | 1994-11-04 | |||
| JPH0823272A | 1996-01-23 | |||
| JPH11505987A | 1999-05-25 | |||
| JP2003198874A | 2003-07-11 |
Attorney, Agent or Firm:
MATSUNUMA Yasushi et al. (JP)
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