Title:
PHASE DETECTOR, PHASE SYNCHRONIZATION CIRCUIT, AND METHOD FOR CONTROLLING PHASE SYNCHRONIZATION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/094310
Kind Code:
A1
Abstract:
The present invention improves the operating range of a phase detector equipped with flip-flops and improves the jitter resistance of a reception circuit. This phase detector is provided with a retention unit and a detection unit. In the phase detector, the retention unit retains an input signal in synchronization with a predetermined periodic signal. On the basis of the signal retained by the retention unit, the detection unit detects a phase difference between the predetermined periodic signal and a specified edge specified by a control signal that specifies, as a specified edge, either a rising edge or a falling edge of the input signal.
More Like This:
WO/2013/063500 | CLOCK AND DATA RECOVERY FOR NFC TRANSCEIVERS |
WO/1993/013592 | PHASE DETECTOR CIRCUIT |
JP4546716 | PLL clock signal generation circuit |
Inventors:
ZHOU ZHIWEI (JP)
MASUDA TAKASHI (JP)
MARUKO KENICHI (JP)
MASUDA TAKASHI (JP)
MARUKO KENICHI (JP)
Application Number:
PCT/JP2016/076569
Publication Date:
June 08, 2017
Filing Date:
September 09, 2016
Export Citation:
Assignee:
SONY CORP (JP)
International Classes:
H03L7/089; H03K5/26; H03L7/08; H04L7/033
Foreign References:
JP2000092035A | 2000-03-31 | |||
JPS59208932A | 1984-11-27 | |||
JP2007267005A | 2007-10-11 | |||
JP2010252244A | 2010-11-04 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
Download PDF: