Title:
PHASE INTERPOLATION CIRCUIT, RECEPTION CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2022/118440
Kind Code:
A1
Abstract:
This phase interpolation circuit includes: a first buffer circuit (201) for generating a first input clock signal by adjusting a rise time or a fall time of a first reference clock signal on the basis of a first control signal; a second buffer circuit (202) for generating a second input clock signal by adjusting a rise time or a fall time of a second reference clock signal on the basis of a second control signal; a detection circuit (401) for detecting the rise time or the fall time of the first input clock signal or the second input clock signal and in accordance with a detection result, generating the first control signal and the second control signal; and a mixer circuit (203) for generating an output clock signal having a phase between the phase of the first input clock signal and the phase of the second input clock signal.
More Like This:
| JP5153094 | DLL device and DLL clock generation method |
| JP2002135116 | PLL CIRCUIT AND FREQUENCY-DIVIDING METHOD |
Inventors:
FUJIMURA TAKUYA (JP)
Application Number:
PCT/JP2020/045100
Publication Date:
June 09, 2022
Filing Date:
December 03, 2020
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H03L7/081
Domestic Patent References:
| WO2013108350A1 | 2013-07-25 |
Foreign References:
| JP2018504849A | 2018-02-15 | |||
| JP2010232868A | 2010-10-14 | |||
| JP2012231394A | 2012-11-22 | |||
| JP2015033094A | 2015-02-16 | |||
| JP2018046489A | 2018-03-22 |
Attorney, Agent or Firm:
KOKUBUN, Takayoshi (JP)
Download PDF: