Title:
PHASE-LOCKED LOOP APPARATUS AND METHOD FOR CLOCK SYNCHRONIZATION
Document Type and Number:
WIPO Patent Application WO/2019/172467
Kind Code:
A1
Abstract:
A phase-locked loop (PLL) apparatus and a method for clock synchronization are disclosed. According to an embodiment, the PLL apparatus comprises an adjustable oscillator, one or more first difference determiners, one or more first parameter determiners and a loop integrator. The adjustable oscillator can generate an oscillating signal based on a control signal. Each first difference determiner can receive a first clock reference signal and determine a phase difference between the received first clock reference signal and the oscillating signal. Each first parameter determiner can receive a phase difference from the one or more first difference determiners and generate a first control parameter based on a variation of the phase difference. The loop integrator can integrate the one or more first control parameters to generate the control signal for the adjustable oscillator.
Inventors:
BAE JUNKYE (KR)
Application Number:
PCT/KR2018/002664
Publication Date:
September 12, 2019
Filing Date:
March 06, 2018
Export Citation:
Assignee:
ERICSSON TELEFON AB L M (SE)
BAE JUNKYE (KR)
BAE JUNKYE (KR)
International Classes:
H03L7/099; H03L7/087
Domestic Patent References:
| WO2016144486A1 | 2016-09-15 |
Foreign References:
| KR20090050636A | 2009-05-20 | |||
| US20170257103A1 | 2017-09-07 | |||
| JP2017118371A | 2017-06-29 | |||
| US20160373121A1 | 2016-12-22 |
Other References:
See also references of EP 3763045A4
Attorney, Agent or Firm:
YANG, Young June et al. (KR)
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