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Patent Searching and Data


Title:
PHASE-LOCKED LOOP CIRCUIT AND FREQUENCY ADJUSTMENT METHOD FOR INJECTION-LOCKED FREQUENCY DIVIDER
Document Type and Number:
WIPO Patent Application WO/2015/136659
Kind Code:
A1
Abstract:
In a PLL circuit (1001), first of all, an output voltage (Vtune) of an LPF (50) is coupled to an ILFD (10(n)), whereby the ILFD (10(n)) becomes an oscillator. The ILFD (10(n)), a DIV (20), a PFD (30), a CP (40) and the LPF (50) form a PLLn, and a lock operation starts. After a lapse of a given time, the output frequency of the ILFD (10(n)) converges to a given value and the PLLn becomes locked. After the PLLn becomes locked, a sample and hold circuit SH (70(n)) holds the loop filter output voltage (Vtune) at a current time, and a frequency adjustment of the ILFD (10(n)) is completed. Similar frequency adjustments are sequentially implemented for ILFD (10(n − 1)) to ILFD (10(1)).

Inventors:
NAKAI, Takayuki (7-3 Marunouchi 2-chome, Chiyoda-k, Tokyo 10, 〒1008310, JP)
Application Number:
JP2014/056623
Publication Date:
September 17, 2015
Filing Date:
March 13, 2014
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORPORATION (7-3 Marunouchi 2-chome, Chiyoda-ku Tokyo, 10, 〒1008310, JP)
International Classes:
H03L7/08; H03K23/58
Domestic Patent References:
WO2013140755A12013-09-26
Foreign References:
US7856212B22010-12-21
JP2008236557A2008-10-02
US20130195224A12013-08-01
JPS5725728A1982-02-10
Other References:
SHO IKEDA ET AL.: "A Low Voltage Phase-Locked Loop with Digitally Calibrated Injection Locked Frequency Divider and Linearized Varactor", PROCEEDINGS OF THE 2013 IEICE ELECTRONICS SOCIETY CONFERENCE, vol. 2, 18 September 2013 (2013-09-18)
CHANGHUA CAO ET AL.: "A-50GHz Phase-Locked Loop in 0.13-pm CMOS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 42, no. 8, August 2007 (2007-08-01), pages 1649 - 1656
Attorney, Agent or Firm:
MIZOI, Shoji et al. (MIZOI INTERNATIONAL PATENT FIRM, NTA Ofuna Building 3rd floor 17-10, Ofuna 2-chome, Kamakura-sh, Kanagawa 56, 〒2470056, JP)
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