PLL circuits are widely used circuit building blocks. A few of their applications are tone decoding, demodulation of AM and FM signals, frequency multiplication, frequency synthe- sis, pulse synchronisation of signals from noisy sources and the regeneration of signals without noise. Typically, a PLL comprises a phase detector circuit, an amplifier or charge pump and a voltage controlled oscillator (VCO). The phase detector circuit detects whether two signals are in or out of phase. One of these signals is a reference sig- nal. The other one is generated in the PLL. The charge pump generates an analog signal with a high current drive suit- able for the control of the VCO. The charge pump signal has usually two fixed current values of the same amount, but opposite sign corresponding to the digital 0 and 1 respec- tively provided by the phase detector. The frequency of the VCO is adjusted until the reference signal and the signal which is compared to the reference signal are synchronised.

The signal generated in the PLL and being compared to the reference signal is not necessarily identical with the sig- nal generated by the VCO. For a very common application, the signal of the VCO is firstly divided by a divider and then fed into the phase detector. The VCO therefore gener- ates a frequency which is by a factor given by the inverse of the divider ratio higher than the reference signal (fre- quency multiplication).

In digital PLLs, EXOR gates are commonly used as phase de- tectors. If the reference signal and the signal generated in the PLL do not have a duty factor of 50 % at the begin- ning, their duty factors are often altered to 50 % before comparison by the phase detector. A duty factor of 50 % is very suitable for EXOR detectors. In this case, the duty factor of the signal generated by the EXOR gate increases linearly with increasing phase difference between the two compared signals and reaches its maximum value of 100 % for a phase difference of 180 degrees and decreases afterwards again. A duty factor of 50 % occurs for a phase difference of 90 degrees.

Using an EXOR gate as phase detector for example, it is ex- tremely difficult to synchronize both signals if the phase difference between both signals is larger than 180 degrees because the relationship between the phase difference sig- nal and the phase difference is no more linear. Such large phase differences can for example occur if the divider ra- tio is changed, the frequency of the reference signal changes or mechanical stress such as vibrations or shocks is applied to the PLL.

Before the signal provided by the charge pump is fed to the VCO, a DC signal is usually generated in a loop filter.

This filter averages the signal provided by the charge pump. As the charge pump typically generates two fixed cur- rent values of the same amount, but opposite sign corre- sponding to the digital 0 and 1 respectively provided by the phase detector, the filtered signal will be zero for a phase difference of 90 degrees when the duty factor is 50 % in the ideal case. A zero current at the input of the VCO usually signifies that the VCO maintains its frequency.

Hence, the phase shift between the reference signal and the signal compared to the reference signal is 90 degrees in

steady-state conditions (the phase-locked loop is locked).

However, real charge pumps cannot provide two current val- ues of exactly the same amount, but opposite sign. In steady-state conditions, the phase shift between the refer- ence signal and the signal compared to the reference signal is therefore in general not exactly 90 degrees.

Besides, the loop filter contributes considerably to the fact that the signal compared to the reference signal is unable to follow the changes of the reference signal imme- diately because it has to be charged. The times it takes until the phase-locked loop circuit reaches its steady- state conditions, i. e. the lock time, depends on the quali- ties of the loop filter. In general, low pass filters are used as loop filters. Whereas a loop filter with a broad bandwith is able to follow the changes of the phase differ- ence signal quite rapidly, a loop filter with a narrow band slowly follows the changes of the phase difference signals, but provides a signal free of ripple as required by the VCO. Such ripple would provoke the variation of the VCO frequency.

The patent application US 2002/0041214 discloses a PLL cir- cuit, wherein the lock time is shortened by increasing the output current of the charge pump during lock-up. Due to the increase of the output current, the loop filter is charged more rapidly. Thus, a quick lock time can be achieved for a filter with a narrow bandwith suited for the VCO.

However, the two output current values of the charge pump cannot be controlled very exactly as mentioned before. The unsatisfactory control of the output current results in a dependence of the actual phase shift between the reference

signal and the signal compared to the reference signal on the amount of the two output current values of the charge pump disturbing the lock-up of the phase-locked loop. A further disadvantage of the disclosed circuit is its com- plexity.

The US patent 4482, 869 discloses a PLL circuit based on a dual bandwith loop filter. The broad bandwith is used dur- ing lock-up. The filter is then able to follow the changes of the phase difference signals quickly, whereas the narrow bandwith is used in the linear range leading to the genera- tion of a signal free of ripple. Problems might arise when the bandwith is switched from the broad bandwith to the narrow bandwith. Therefore, the narrow bandwith is achieved by switching-in only components which do not have to be loaded, i. e. resistors. A disadvantage is that this limits the flexibility in the design and performance of the fil- ter.

The object underlying the present invention is to provide a phase-locked loop circuit enabling quick lock times and ripple free signals at the input of the voltage controlled oscillator without the requirement of complex circuitry.

Further, a corresponding loop filter circuit and an advan- tageous method for operating the loop filter circuit are to be provided.

In one aspect of the present invention, a phase-locked loop circuit comprising : a voltage controlled oscillator gener- ating oscillator signals with frequencies dependent on filtered signals applied to said voltage controlled oscil- lator ; a phase detector circuit providing phase difference signals on the basis of the phase difference of said oscil- lator signals and reference signals ; a loop filter circuit

with at least a first and a second bandwith filtering said phase difference signals and providing said filtered sig- nals, said first bandwith being determined by a first net- work of circuit components being switched in when said phase-locked loop circuit is not locked, said second band- with being determined by a second network of circuit compo- nents being switched in when said phase-locked loop circuit is locked ; is characterized in that a bias circuit is ap- plying a voltage value of a node of said first network to a node of said second network when said second network is switched off and in that the circuit components of said second network are being charged before the second network is switched in.

An advantage of the present invention is that the circuit components of said first network are already charged before they are switched in. Therefore the output signal of the loop filter circuit is not distorted by the switching ac- tion.

A further advantage is that circuit components with a high capacitance can be used exclusively for the locked opera- tion.

In one feature of the present invention, said oscillator signals are applied to a divider before being applied to the phase-locked loop circuit.

In another feature of the present invention, said phase difference signals are applied to a charge pump circuit be- fore being filtered by said loop filter circuit.

In a further feature of the present invention, said phase

detector circuit is an EXOR gate.

In yet a further feature of the present invention, the switching-in of said first network and said second network is controlled by signals indicating whether said phase- locked loop is locked.

In a further feature of the present invention, no component being part of said first network is part of said second network.

In another feature of the invention, said bias circuit com- prises at least one voltage follower.

In a second aspect of the present invention, a filter cir- cuit for a phase-locked loop with at least a first and a second bandwith, said first bandwith being determined by a first network of circuit components and being used when said phase-locked loop circuit is not locked, said second bandwith being determined by a second network of circuit components being used when said phase-locked loop circuit is locked ; is characterized in that a bias circuit is ap- plying a voltage value of a node of said first network to a node of said second network when said second network is switched off and in that the circuit components of said second network are being charged before the second network is switched in.

In a third aspect of the present invention, a method for operating a loop filter circuit filtering phase difference signals with at least a first bandwith being determined by a first network of circuit components and a second bandwith being determined by a second network of circuit components

in a phase-locked loop circuit with a voltage controlled oscillator generating oscillator signals with frequencies dependent on filtered signals applied to said voltage con- trolled oscillator and a phase detector circuit providing said phase difference signals on the basis of the phase difference of said oscillator signals and reference sig- nals, comprising the following steps: Switching-in of said first network when said phase-locked loop circuit is not locked Switching-in of said second network when said phase-locked loop circuit is locked ; is characterized by the following steps : applying a voltage value of a node of said first network to a node of said second network when said second network is switched off; charging of the cir- cuit components of said second network before the second network is switched in.

In a further feature of the present invention, said oscil- lator signals are applied to a frequency modulator circuit before being applied to the phase-locked loop circuit.

Embodiments of the present invention will now be described, by the way of example only, with reference to the following drawings in which: Fig. 1 is a block diagram of a PLL circuit according to the invention; Fig. 2 is a circuit diagram showing the loop filter used in the circuit of figure 1.

Fig. 3 is a circuit diagram showing an alternative loop filter.

Fig. 4 is a circuit diagram showing a further alternative loop filter.

As shown in fig. 1, a PLL circuit according to the present invention has the same design as a state-of-the-art circuit except that a different loop filter is used. The phase de- tector PD compares two signals UEF and uiv, wherein uEF is a reference signal and Uoiv is a signal provided by the di- vider DIV. It consists typically of an EXOR gate. Based on the comparison of these two signals, the phase detector provides the phase difference signals UPDat its output. The digital signal upD is converted to an analog signal in the charge pump CP suitable for the control of the VCO.

Before the signal generated by the charge pump uCP is re- ceived at the voltage controlled oscillator, the signal Ucp- is filtered in the loop filter LF. The loop filter LF has two filter paths being switched in and off by the switches S1 and S2 being controlled by the control signals uCOn which might be generated by the phase detector. Alternatively, the signals Ueon might indicate that the divider ratio was changed a certain time ago and that the phase-locked loop circuit is now definitively locked as estimates for the lock time are known. The fast filter path is used for lock- up and has a wide bandwith. The slow filter path is used when the phase-locked loop is locked and has a narrow band with. The slow filter paths comprises internal switches be- ing controlled by ucOn signals. Internal switches control the charging of circuit components of the slow filter. The fast filter path and the slow filter path are connected by a voltage follower VF. The loop filter LF provides the sig- nal u>F which controls the VCO at its output.

The signal provided at output of the voltage controlled os- cillator is delivered to the application A and applied at the divider DIV. The divider DIV divides the frequency of the uvco signal by the divider ratio and provides the signal UDIV which is compared to the reference signal at its out-

put. In steady-state conditions, the VCO generates a signal which is by a factor corresponding to the inverse of the divider ration higher than the reference signal and deliv- ers it to the application A.

The loop filter of figure 1 is shown in figure 2 in detail.

The switches Si, S2, S3, S4, and S5 are controlled by the signal ucon of fig. 1. The loop filter is shown for the case that the phase-locked loop is locked. The fast filter path comprising the circuit components Cl, C2, C3, R1, and R2 is switched off and the slow filter path comprising the cir- cuit components C4, C5, C6, R3, and R4 is switched in. The voltage follower VF is disconnected from the slow filter path by the switches S3, S4, S5. The loop filter must not necessarily consist of two or more filter paths. It might also comprise circuit components used when the phase-locked loop is either locked or unlocked.

During lock-up, the fast filter path is switched in using the switches S1 and S2 and the voltage follower VF applies the voltage level of node 1 of the network of the circuit components C1, C2, C3, R1, and 2 to the nodes 2, 3, and 4 of the network of the circuit components C4, C5, C6, R3, and R4.

The two circuit paths do have the same design. However, they have different transfer characteristics due to differ- ent values for their circuit components. Especially, large capacitors C4, C5, and C6 are preferred for the slow filter path used within the linear range, whereas small capacitors C1, C2r C3 are preferred for the fast filter path used dur- ing lock-up. The small capacitors are able to follow sudden changes quickly and shorten the lock time. The charging of the large capacitors C4, C, 5, and C6 takes long and they can-

not follow sudden voltage changes. However, the large ca- pacitors C4, C5, and C6 are not susceptible to quick voltage changes. The signal provided by the fast filter path is therefore free of ripple.

Fig. 3 shows an alternative filter. The reference numerals of fig. 2 are used for similar circuit components. In con- trast to fig. 2, the voltage follower applies the voltage level of node 5 of the network of circuit components C1, C2, C3, Ri and R2 to the nodes 2, 3, and 4 of the network of the circuit components C4, C5, C6, R3, and R4.

Fig. 4 shows a further alternative filter. The reference numerals of fig. 2 are used for similar circuit components.

In contrast to fig. 2, the bias circuit consisting of three voltage followers VF1, VF2, and VF3 applies the voltage level of node 1 of the network of circuit components Cl, C2, C3, R1, and R2 to the nodes 2,3, and 4 of the network of the circuit components C4, C5, C6, R3, and R4.