Title:
PHASE-LOCKED LOOP CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/167670
Kind Code:
A1
Abstract:
The present art relates to a phase-locked loop circuit that enables power consumption to be reduced. The phase-locked loop circuit comprises: an SAR-ADC that includes two capacitors and outputs a comparison result of voltages occurring across the two capacitors; an electric current source that charges the two capacitors with electric current; a first switch that is arranged between the electric current source and one of the two capacitors and supplied with a phase difference between a first clock having a reference frequency and a second clock having a frequency higher than the first clock; and a second switch that is arranged between the electric current source and the other of the two capacitors and supplied with the second clock. The present disclosure can be applied, for example, to a wireless communication device.
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Inventors:
ARISAKA NAOYA (JP)
FUJIWARA TETSUYA (JP)
ETOU SHINICHIROU (JP)
FUJIWARA TETSUYA (JP)
ETOU SHINICHIROU (JP)
Application Number:
PCT/JP2019/005554
Publication Date:
September 06, 2019
Filing Date:
February 15, 2019
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H03K5/26; H03L7/085
Foreign References:
| JP2017163546A | 2017-09-14 | |||
| JPH09153773A | 1997-06-10 |
Other References:
SOMNATH KUNDUBONGJIN KIMCHRIS H. KIM: "19.2 A 0.2-to-1.45 GHz Subsampling Fractional-N All-Digital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection", 2016 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, 3 February 2016 (2016-02-03), Retrieved from the Internet
See also references of EP 3761509A4
See also references of EP 3761509A4
Attorney, Agent or Firm:
NISHIKAWA Takashi et al. (JP)
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