Title:
PHASE LOCKED LOOP
Document Type and Number:
WIPO Patent Application WO/2019/073841
Kind Code:
A1
Abstract:
This phase locked loop is provided with: a phase comparison circuit that compares the phase of a first signal and the phase of a second signal corresponding to a clock signal; a loop filter that comprises a resistive element having one end connected to a first node and the other end connected to a second node, and a capacitive element having one end connected to the second node, and that generates a control voltage on the basis of a phase comparison result in the phase comparison circuit; an oscillation circuit that generates the clock signal on the basis of the control voltage; an AD conversion circuit that converts a voltage difference between both ends of the resistive element into a digital code; and a current generation circuit that generates a first current on the basis of the digital code, and supplies the first current to the second node.
Inventors:
LIN YINTA (JP)
Application Number:
PCT/JP2018/036704
Publication Date:
April 18, 2019
Filing Date:
October 01, 2018
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H03L7/08; H03L7/093
Foreign References:
| US20160240921A1 | 2016-08-18 | |||
| JP2015516133A | 2015-06-04 | |||
| JP2007184778A | 2007-07-19 |
Other References:
CHANG, JUNG-YU ET AL.: "A Phase-Locked Loop With Background Leakage Current Compensation", IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, vol. 57, no. 9, 19 August 2010 (2010-08-19), pages 666 - 670, XP011316887
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (JP)
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