Copyright NoticelPermission A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the United States Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. The following notice applies to the drawing hereto: Copyright 0 1999-2000, Nexus Telocation Systems, Ltd., Israel, All Rights Reserved.

Field of the Invention The present invention relates to telecommunication modulation techniques. In particular, the present invention relates to Pulsed Frequency Shifl Keying for phase modulation in direct sequence or frequency hopping spread-spectrum circuits.

Background of the Invention The most common technology of modulation in narrow-band digital wireless communication is Frequency Shift Keying (FSK) due to the fact that the implemcntation of FSK modulators is simple, small and low in cost. FSK modulation is less efficient than Phase Shift Keying (PSK) modulation in bit error rate (BER) compared to EhJN" (the energy per bit over the noise density), however, FSK modulation is widely used in such systems as Gaussian Minimal Shift Keying (GSMK) modulation and Digital European Cellular Telephone (DECT) due to the lower cost in implementation and operation.. Thus, although PSK will provide better performance than FSK, PSK modulators are more expensive, larger in size and consume a larger amount of power compared to the FSK modulators.

The modulation circuits rely upon a basic Phase Lock Loop (PLL) circuit to produce a stable RF carrier signal which may be then modulated with the information by phase shifting the carrier or frequency shifting the carrier. The stability of the carrier is critical to later demodulation of the information so frequency drift of the carrier is avoided with a PLL. A PLL circuit is comprised of three main components: a phase detector, a low pass filter (LPF), and a Voltage Controlled Oscillator (VCO). A feedback loop from the output of the VCO to one input of the phase detector completes the loop. The phase detector operates as a comparator to compare the VCO output to a reference frequency. The output of the phase detector is the error voltage which is then used to adjust the VCO frequency.

Figure 1 is a block diagram of a known Phase Lock Loop (PLL) circuit 100 utilizing an FSK modulating technique. The modulation signal is a digital signal having a serial stream of ONE's and ZERO's where the digital ONE is represented by a positive voltage and the digital ZERO is represented by a zero voltage. A Temperature Controlled Crystal Oscillator (TCXO) 102 provides a reference frequency signal which is (optionally) divided by frequency divider 104 and driven to phase detector 106. The modulated Radio Frequency (RF) output 118 is sensed at 116 and divided by RF frequency divider 108. The phase detector 106 operates as a phase lock loop to compare the divided down reference frequency to the divided down RF carrier signal and to produce an error voltage on its output. The error voltage from phase detector 206 is filtered to remove any high frequency noise through low pass filter (LPF) 110 which provides only the low spectrum component of the phase lock error signal to Voltage Controlled Oscillator (VCO) 112. A VARICAP (voltage variable diode-capacitor) in VCO 112 receives the modulation signal 114 and the low spectrum error signal from the low pass filter 110 and produces a frequency shift keying modulated RF output signal 118 which is stabilized to the reference frequency from 102.

Figure 2 is a block diagram of a two-port FSK modulator 200 using a phase lock loop and which is commonly used in a wide variety of digital and analog communications systems. As described above, the modulation signal is a digital signal having a serial stream of ONE's and ZERO's where the digital ONE is represented by a positive voltage and the digital ZERO is represented by a zero voltage. A Voltage Controlled and Temperature Controlled Crystal Oscillator (VCTCXO) 202 provides the reference signal which is optionally divided down with divider 204 and fed to comparator/phase detector 206. The modulation signal 214 is filtered with a low pass filter 220 and used to modulate the reference frequency at VCTCXO 202 to produce a modulated reference frequency. The modulated reference signal is optionally divided down by divider 204 and driven to phase detector circuit 206. The phase detector 106 compares the modulated reference frequency to a divided down feedback signal from the modulator output 218. The RF output signal is sensed at 218 and divided down by divider 208 to produce the feedback signal used by phase detector 206. The output of phase detector 206 is an error voltage which is filter by LPF 210 to remove the high- frequency components of the error signal. The filtered error signal is used to control and stabilize VCO 212 which also receives the modulation signal 214 to modulate the stabilized RF carrier. Again, a VARICAP (voltage variable diode-capacitor) in VCO 212 receives the modulation signal 214 and the low spectrum component of the error signal from the low pass filter 210 to frequency shift key the carrier to produce a frequency shift keyed modulated RF carrier signal 218. The low spectrum of the modulation is practically blocked by the PLL circuit, which restores the frequency changes such that the modulation point (VCTCXO) 202 generates only the low spectrum modulation. The advantage of the FSK circuit of figure 2 is that the two modulation points avoids carrier frequency drift when a long series of ONE's or ZERO's are being transmitted and the modulation voltage stays at one level for a long time.

The resulting modulated carrier is seen as shifting between two stable frequencies. regardless how many one's or zero's are transmitted in a long string.

The most common technique for direct phase modulation is shown in Figure 3 as a PSK modulator. The phase modulator 300 exists mostly as a Quadrature Phase Shift Keying (QPSK) modulator (2 bits per symbol) producing shifts of 0°, 90°, 180° or 270°, although the same circuit is used for BiPhase Shift Keying (BPSK) by shifting the carrier 180° or 0° by shortening the two modulation ports 324,326 in modulator 314. The QPSK technique of Figure 3 has several drawbacks. The modulation of modulator 314 creates discontinuity"contaminates"in the frequency spectrum and therefore could easily generate oscillations in the transmitter. Also, the modulator 314 pulls of the VCO 312 and creates ringing on the pulses. In order to isolate the modulator from the VCO, a buffer 318 or amplifier 318 is required, which consumes additional power and cost. The modulator 314 of Figure 3 is based on switches 324,326 and therefor the sidelobe control in the frequency domain is limited.

In the case of a class-C power amplifier 318 following the PLL circuit, sidelobe control is limited. The modulation itself consumes significant power and does not fit low power integrated circuits. The accuracy of the PSK modulator 300 of Figure 3 is on the order of + 10°, due to inaccuracy of the 90° hybrids 324,326 and due to the imbalance of the switches (mixers) 322a and 322b in I and Q branches 328a and 328b, respectively.

Further, low speed modulation (measured as a ratio of modulation rate versus carrier frequency) is practically impossible since the pulling of the VCO 312 by the modulator 314 and the resulting radio frequency interference (RFI) effects requires isolation that is very nearly impossible to achieve. The low speed interference which results in frequency instability is"corrected"by the PLL, since the loop bandwidth is assumed to be wider than the modulation speed and the result is ringing effect or inability to achieve the required phase.

In order to overcome the pulling problems and the isolation problem that is partially due to high frequency radiation of the direct PLL modulator 300 of Figure 3, a double conversion PLL modulator 400 of Figure 4 is used. In a double conversion PSK circuit the most common technique is to modulate the VCO 412 at some intermediate frequency (IF) usually hellom 100 MHZ (see upper half of Figure 4), and up-convcrt the signal to its final frequency at mixer 432.. Since the RFI at IF is significantly smaller and the isolation is easier, the circuit 400 has in general better performance than the direct modulation of Figure 3. However, the double conversion circuit 400 of Figure 4 has several drawbacks in terms of complexity of implementation which leads to excessive costs to build and operate. Two PLL circuits operating at IF and RF are required. Also, due to the size and number of components, the required power used to operate the circuit of Figure 4 is excessive.

Figure 5 is a block diagram of a PLL modulator 500 having Direct Digital Synthesizer (DDS) phase modulation. The DDS modulator produces a digital synthesized frequency by using a sampled cosine stored and read from a read only memory or a Programmable Read-Only Memory (PROM) device 530 in which each address has a value representing the amplitude of a corresponding cosine wave at the specific point in time. The addresses of PROM 530 is stepped by an address circuit 534,536,538 and synchronized to the reference frequency 502 to produce a very clean cosine. The rate of addressing corresponds to the desired carrier frequency. Assuming that the PROM 530 has N-entries, the corresponding value of the n'h entry will be A (n) = COS (2*n/N).

Adding a fractional phase each period of time from the PROM 530 generates the carrier frequency through an Digital to Analog Convertor (DAC) 528.

Assuming that the sample frequency is F, for example, for each I/Fs the phase is moving forward by reading the PROM cosine data out of the DAC 528 by k values, the frequency generated is: F=F, *k/N.

Adding the proper value from phase selector 536 to the PROM address through adder 536 generates the phase change. Modulating by 2z ! 4 (90°) is implemented by adding N/4 to the address register. The DAC translates the output of the DDS to the analog world and the spurious frequencies are filtered by band-pass filter (BPF) 526. Optionally the DDS produces frequency at some low IF and the modulator output 524 is up-converted by another circuit to the RF level. Although the DDS modulator 500 of Figure 5 is very accurate, it is expensive to implement, it is large in size with many components and it consumes a large amount of power.

Figure 6 is a block diagram of a PLL modulator 600 having up-converted Quadrature or I-Q Modulation. The modulation signal is a digital signal driven through an optional Application-Specific Integrated Circuit (ASIC) 628 which is then converted to an analog voltage through the Digital to Analog Convertors (DAC) 626 to modulate the amplitude of a phase shifted signal. The IF frequency is generated in a conventional manner using a Plu in the upper left of Figure 6 while the PLL for the RF component is shown in the lower left of Figure 6.

Figure 6 represents one of the most common techniques for implementing N-PSK modulation for I-Q modulation where N represents the number of levels used in the modulation. The modulator operates according to the following trigonometric equations to mathematically model the circuit behavior: <BR> <BR> A* COS (wt + ) = A* COS (¢) COS (wt)-A* SIN (#)SIN (wt)<BR> (wt+#)=I*COS(wt)-Q*SIN(wt)A*COS I = A* COS (¢) Q = A* SIN (> In the circuit implementation shown in Figure 6, the amplitude is controlled by the voltage variable attenuators (VVA) 622a and 622b. In general, the modulation is done in the IF band and up-converted to the RF band. The main problem with the implementation of the modulator 600 of Figure 6 is the cost of implementation.

Keeping the two branches balanced and keeping the same amplitude behavior for both VVA's 622a, 622b over a significant operational temperature range is expensive.

Therefor, the modulation is done usually in fixed IF.

As one skilled in the art will recognize, and in light of the shortcomings of the prior art described above, there is a need in the art for an improved modulation technique for narrow-band digital wireless communication which can be implemented in a smaller design area, which requires less power to operate and is relatively inexpensive to manufacture.

Summary of the Invention The present invention solves the above deficiencies in the art as well as solving other advantages which will be understood by those skilled in the art upon reading and understanding the following description. The present invention describes a Pulsed Frequency Shift Keying modulation method and apparatus which uses narrow bipolar pulses to shift the frequency of a carrier signal which results in a phase shift keying of a carrier wave. The first, positive-going narrow pulse shifts the frequency of a carrier signal from a first frequency to a second frequency, and returns the carrier to the first frequency thereby changing the phase of the carrier. Then, a second, negative- going narrow pulse shifts the carrier frequency from the first frequency to a third frequency, thus restoring the original phase of the carrier. A pair of positive-going and negative-going differential pulses represents one symbol of transmitted information and results in a momentary phase shift in the carrier. The implementation of this pulsed frequency shift keying modulation may be in biphase shift keying, or in any number of multiple phase shift keying implementations where a single symbol represents more than one digital bit. Other implementations and multiple embodiments of the present invention are also described.

Brief Descriptions of the Drawings In the drawings, in which like reference numbers represent like components throughout the several views, where the leftmost digits of the reference numbers correspond to the Figure first describing the component, and where the rightmost digits of the reference numbers generally describe similar components throughout the several views.

Figure I is a block diagram of a prior art circuit using a Phase Lock Loop (PLL) circuit for producing Frequency Shift Keying (FSK) Modulation.

Figure 2 is a block diagram of a prior art two-port circuit using a PI, for producing FSK modulation.

Figure 3 is a block diagram of a prior art circuit using a PLL circuit for producing Quadrature Phase Shift Keying (QPSK) direct modulation.

Figure 4 is a block diagram of a prior art circuit using a PLL circuit for producing QPSK up-converted modulation.

Figure 5 is a block diagram of a prior art circuit using a PLL circuit for producing Phase Shift Keying (PSK) modulation using Direct Digital Synthesization (DDS).

Figure 6 is a block diagram of a prior art circuit using a PLL circuit for producing I-Q Quadrature Phase Shift Keying (QPSK) modulation in the Intermediate Frequency (IF) band.

Figure 7 is a block diagram of a two-port PLL circuit of the present invention which produces Pulsed Frequency Shift Keying (PFSK) modulation.

Figure 8 is a block diagram of a mathematical model of a Frequency Modulator producing FSK or PSK of the present invention.

Figure 9 is a graph of the modulation signal over time and the resulting phase shift over time of the PFSK modulator of the present invention.

Figure 0 is a block diagram of a mathematical model of a PLL circuit in the phase domain for describing the present invention.

Figure 11 is a block diagram of a mathematical model of a PFSK circuit in the phase domain of the present invention.

Figure 12a and 12b are block diagrams of additional embodiments of two-port modulator PFSK circuits of the present invention.

Figure 13 is a block diagram of a self-calibrating PFSK circuit of the present invention.

Figure 14 is a comparison graph plotting the sidelobes of Bi-Phase Shift Keying (BPSK), Differential PFSK and Filtered Differential PFSK of the present invention in the frequency domain.

Figure 15 is a block diagram of a fractional PLL circuit of the present invention which produces PFSK modulation.

Figure 16 is a block diagram of a PLL circuit of the present invention which produces narrow bandwidth PFSK modulation.

Figure 17 is a block diagram of a PLL circuit of the present invention which produces narrow bandwidth PFSK modulation using DDS for the reference frequency.

Figures 18a and 18b are a block diagrams of wireless and wired communications devices incorporating any of the embodiments of the present invention described in Figures 7-17.

Detailed Description of the Preferred Embodiments In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that process or mechanical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims. The mathematical variables used throughout this description of the invention use descriptors which are consistent with commonly used textbook descriptors for telecommunications mathematical modeling and electromagnet theory. Since these variables and their descriptors are known to those skilled in the art, some variables in this patent application are only briefly defined.

Overview of the Invention The present invention describes a new implementation technique for Pulsed Frequency Shift Keying (PFSK) modulation that allows a simple and low cost implementation of phase modulation. The technique of the present invention is very useful for implementing low-cost spread-spectrum circuits, both for direct sequence (high-speed modulation) and for frequency hopping (lower speed modulation). An advantage of the PFSK modulation of the present invention is a"constant envelope" waveform which produces low side lobes, even if the power amplifier is C class. The present invention can be used for both direct sequence and frequency hopping spread spectrum modulation which provides for dual-mode end user communications devices.

The circuitry of the present invention consumes significantly less power than conventional phase modulators and is implemented significantly smaller than modulators circuits of the prior art. In addition, an exemplary embodiment of the present invention allows for the implementation of a high-level phase modulator such as eight or sixteen level phase modulators with very high phase accuracy.

A simple representation of a modulator 700 of the present invention is shown in Figure 7. This representation is similar in layout to the FSK modulator of Figure 2 with several important distinctions. The modulation signal 714 (described more fully below) represents the digital data as very narrow pulses in both the positive and negative voltage directions. Also, the frequency dividers 704,708 and the phase detector 706 are all designed to operate in a narrow frequency range to allow the PLL to lock to a new frequency and remain at the new frequency until a negative voltage narrow pulse is received from the modulator 714 to return the frequency to its original frequency. In this fashion, rapid differential pulses from modulator 714 are used to effect a narrow frequency shift which appears very much as a short-duration phase shift in the carrier signal.

The present invention relies on the following: A (D = 2n J AF dt = 2n*A F * AT where F is the frequency, T is the time, ## is the apparent change in phase of the carrier signal (A representing the universal mathematical symbol for change). For example, by applying a short pulse AT long, and shift the frequency for this time by AF, the phase of the carrier will be shifted at the end of the process by Ab. If the phase of the carrier is to be shifted by +#/2 (such as with biphase shift keying (BPSK)), and the modulation bit rate is I Mbps (megabits per second), the rise time of the carrier is 0.1 microsecond and the following describes the frequency shift: AF = Ad)/22 AT = (7z/2)/2n* 10-'= 10'14 = 250 kHz The resulting modulation is smooth in phase and will have inherently low side lobes.

Applying a low pass filter 720 to the modulating pulse further reduces the side lobes.

There are a wide variety of possible implementations of the present invention as described below. In one embodiment, the digital data is produced as a serial stream of pulses from an Application Specific Integrated Circuit (ASIC), the pulses are converted using a Digital to Analog Convertor (DAC) into positive and negative pairs of narrow pulses which can be used to rapidly shift the frequency so an apparent phase shift occurs in the carrier. By way of example, the variable K represents the VCO 712 modulation constant in Hz per volt. The variable A represents the VCO 712 modulation port amplitude in volts such that the'frequency shift of the carrier appears fotlows: AF= K* A Note that the amplitude could be positive or negative. BPSK modulation is generated using this technique by applying n/2. This technique fits high-speed modulation (wider than the loop bandwidth) as well as low speed modulation (narrower than the loop bandwidth). The low speed modulation is achieved in the previous example by pulse modulation of the VCTCXO.

Theory of Operation of the Present Invention Frequency Shift Keying can represent digital data by shifting between a plurality of frequencies, but in a simple form, FSK shifts between two frequencies. Bi- Phase Shift Keying shifts the phase of a carrier between two phases. Both type represent two states or levels. A theoretical comparison of BPSK to two level FSK starts with a review of two level FSK.

In two level FSK, the. information per symbol (digital one = '1' and digital zero'0') is defined as: <BR> <BR> 0: SO (t) = ACos (2rfa t)<BR> S1(t)=ACos(2#f1t)1: where f1 and f0 are selected such that the cross correlation between the symbols will bc minimized. The difference between the frequencies Af is compared to the sampling frequency Fs such that: /f1-f0/#f= <BR> 1#xcorr(S0,S1)=0#f/fs= <BR> #f/fs #xcorr(S0,S1)=#-0.50.707 In theoretical BPSK modulation, the information per symbol ('I'and'0') is defined as: 0: Cos (2 ; rf (. I 1: S, (t) =-ACos (2rf. 1) The information in BPSK is encoded in the phase difference. The phase difference between digital'1'and digital'0'is 180° (or s radians). The cross correlation is: xcorr(S"SJ =-1 The better cross correlation of the BPSK results in better BER (bit error rate) per same Eb/No (energy per bit versus noise density). On the other hand, the transmitter and modulator of non-coherent FSK is very simple to implement. A coherent FSK transmitter is relatively difficult to implement and its receiver is complicated. BPSK coherent receivers are relatively simpler to implement. The present invention combines the non-coherent FSK transmitter simplicity with BPSK modulation.

The mathematical model of an FSK modulator is described in Figure 8.

The mathematical model describes a transmission phase, which is an integral of the control voltage, and therefor is always continuous. The transmission is called continuous phase frequency shift keying (CPFSK). Using this model, with the understanding that there cannot be an instantaneous change in voltage over time, the present invention utilizes an FSK modulator paradigm to implement BPSK.

The time domain diagram of a near impulse modulation signal 902 impressed on an FSK VCO is shown in Figure 9 which results in phase modulation of the carrier 904. The phase of the transmission is an integral of the frequency modulated VCO. Therefor, in order to phase modulate one should derive in time the modulated signal and use the derivative to modulate. Theoretically, since the modulation information is a sequence of square bits, the derivative in time is a sequence of impulses (5 function). Since in real world practice, the implementation of the 6 function is impossible (zero pulse-width with infinite amplitude cannot be realized), the implementation replaces the 5 function by narrow pulses 906,908 of Tr, relativc to the symbol width TB, with finite amplitude Vp and-Vp. The impulses are desirably narrow with a fast rise time to mimic a theoretical impulse. The phase change thus begins with the rising edge of the narrow pulse. The positive voltage pulse 906 and the corresponding negative voltage pulse 908 represent a single symbol.

A mathematical model of a Frequency Modulator (FM) implemented with a PLL circuit is described in Figure 10 which shows a basic block diagram of a PLL in the phase domain. The feedback loop locks the VCO 1012 on an accurate reference 1002, and creates an accurate frequency generator in a higher frequency. The lock is based on matching the phase (and consequently the frequency) of the VCO with the reference 1002 at a phase detector 1006 and feeding the difference through a loop filter 1010 into the control voltage of the VCO 1012. After phase lock, the following equation describes the operation of the PLL: <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> f0=f=# <BR> NR R<BR> N R R (Equation 1) The output frequency is controlled by N, the VCO frequency divider and by R, the reference frequency divider. Equation 2 below describes the response of the loop, (comparing the phase of the output 4'Oen to the phase of the input (D,,), in the phase domain: (Equation 2) where KPDis the phase detector constant (output voltage vs. phase error), and Ko is the VCO constant (frequency vs. input voltage).

(See PLL 700 described above.) In order to find the frequency domain behavior, we need to find the time derivative of the phase, i. e. multiply the phase transmission with V-The function is of interest since it provides the frequency stabilization time and the phase noise of the loop. For a second order loop (F(s)=K1+K2/s) the transmission function has typical low pass filter (LPF) behavior. For higher order loops, the transmission must be simulated, although in a typical design, the higher loop poles are far away from zero in a frequency plane plot. Therefor, for a typical PLL, a simple second order loop modeling is adequate for a modulation analysis described below.

A mathematical model of a PFSK modulator is shown in Figure 11.

Modulating the synthesizer circuit 1100 can be done through the following modulation entry points (where V is a voltage). VR 1170 is a control voltage controlling the frequency of the Voltage Controlled Crystal Oscillator (VCXO). Vp is the modulation voltage added 1180 to the error voltage from the phase detector 1106 with the sum driving the loop filter 1110. Vp is a modulation voltage added 1182 to the output of the loop filter 1110 with the resulting sum driving the control voltage input of the VCO 1112. The mathematical models of the response functions of the PFSK model of Figure I I are as follows: Ooelr N t} F (s) H (s) Fomr N KrsXvF (s) (Di) R 5 [N5+boF (S)] S VR R Ns+KrlKoF (s) t... (J {ST Ks F (s) (Srn KiJ2tUF (s) , tp Ns +,"K sF (s) ;", Ns + bI>K2F (s) uc,hCtv Fottr Kv YF KrDsßF s/Kf I + KrERKvF 5)/ N (Equation 3) For a second order loop the response to VR and Vp are low-pass in nature. The response to VF is high-pass.

Narrow Bandwidth PSK Modulation Implementation of a narrow bandwidth PFSK modulator where Fus « sloop bandwidth is possible using an FSK modulator of Figure 11 using entry points VR and Vp. The response to VR in the phase domain is integrative (pole in the origin). In the frequency domain the response has a low-pass characteristic which is proportional to the response of the closed loop. The response to Vp in the phase domain has a low-pass characteristic which is proportional to the response of the closed loop. In the frequency domain the response is distorted. Consequently, the most convenient way for narrow bandwidth PFSK modulation of the present invention is to modulate the frequency through VR and the phase through Vp. Both are low-pass filtered by the loop filter 1110 and therefor their bandwidth must be smaller than the loop filter 1110.

Modulating through VR has a factor of N/R uhich is the ratio between the reference frequency 1102 and the output frequency 1118. Modulating through Vp has a factor of N which is the ratio between the reference frequency 1102 after division <BR> <BR> <BR> 1104 and the output frequency 1118. In addition to the methods described here, PFSK of the present invention can be implemented by changing N, the divider 1108 by a fractional synthesizer. If the symbols rate is slow enough compared to the PLL lock time, the synthesizer 1100 could hop from frequency to frequency in generating the phase modulation for a frequency hopping spread spectrum direct modulation. By way of example and not by way of limitation, see the low speed BPSK modulator using a fractional synthesizer described below.

Wide Bandwidth PSK Modulation Implementation of a wide bandwidth PFSK modulator where Fs » the <BR> <BR> <BR> <BR> loop bandwidth is possible using an FSK modulator of Figure 11 using entry point VF.

As seen from Equation 3 above, the only way to directly modulate the synthesizer 1100 is through the VCO port VF I 1 72 Port VF has no low pass characteristics and its speed limit is the maximal modulation rate of the VCO 1112. Hence, the response of the loop <BR> <BR> <BR> <BR> to VF has a high-pass characteristic with approximately the loop bandwidth. However, the portion of the modulation in frequencies lower than the loop bandwidth wit) not be transmitted. There are several methods in the present invention used to overcome this problem.

In one embodiment. a narrow loop filter I I 10 is used in the PFSK circuit of Figure 1 I in order to minimize the loss of information. This method does have its limitations since a narrow loop filter does not solve the problem but only lessens the loss of information since random digital modulation has significant DC elements.

Further, the use of a narrow loop filter is difficult to implement since the filter implementation requires accurate values of resistors and capacitors and the loop will be close to unstable point (pole in a plane plot). In addition, the low bandwidth resulting from the narrow filter contradicts other system requirements such as short settle time, and low phase noise.

In another embodiment, the design of Figure 11 is implemented using a modulating signal VF having no DC elements. In some implementation of modulator design for signal transmission such as in Direct Sequence Spread Spectrum (DSSS) modulation, the solution is that the modulation bandwidth must be increased in order to remove the DC elements. Removing the DC components of the modulating signal is also accomplished by encoding the digital data stream to ensure frequent transitions (such as when transmitting a long string of ONE's or ZERO's). The present invention is capable of utilizing encoding schemes to remove the DC component such as High Density Bipolar 3 (HDB-3 ensures that no more than 3 consecutive zero voltage states will be transmitted), Manchester encoding, Bi-Phase encoding (also known as Alternat Mark Inversion (AMI), etc.). Unfortunately, this method, although also useful, causes the modulator to be more complicated and the system performance (i. e. link margin) is degraded. Wider bandwidth also results in lower signal to noise ratio. However, the shortcomings of these embodiments do not result in unworkable systems. Depending upon the needs of the modulation system, these shortcomings may be tolerable.

Many of the aforemenlioned shortcomings in various embodiments of the present invention can be overcome in yet further embodiments of this invention described here. In yet several more embodiments, the design of Figure 11 is implemented using a two-port modulation injection with DC compensation, as shown two embodiments in Figures 12a and 12b. The modulation voltage 1210 is injected both through the VCO port V, 1174 and either from the reference port V. 1 70 (herein reference method A), as shown in Figure 12a, or through the loop filter port Vp 1172 (herein reference method B), as shown in Figure 12b, for DC compensation implementations. Equation 4 shown below shows that both methods of Figure 12a and 126 produce ideal loop response.

From (A): , (Dorl- (Dorn, IV KpijKoF (S.) Kc.) Yn Vir t t-R sN. s + KPnKnFs s + KrnKaF s x"x Hz fort IFofrr -1 Furrr =1 s Yn From (B): ntir Kl {torrr + 2 tf) ortr = K N + X 2 Yn s Irr VF s Ns + KYnKnFs, s + KnrKoF s, YUAN ka I Foif-i- un At.-.-. An s 1111) (Equation 4) DC compensation through the reference port 1170 for reference method A of Figure 12a has a simplicity advantage since it does not require the pole in the origin (K,/S), which is required by reference method B of Figure 12b. In the alternative, the maximal modulation point is limited in reference method A of Figure 12a by the maximal modulation bandwidth of the reference 1102. For example, VCTCXO 1102 has a limitation of 10 kHz. The modulation factor is limited by the pulling ratio of the reference 1102. An accurate reference can be pulled by i 10 PPM (parts per million).

In reference method B of Figure 12b, DC compensation accomplished by injecting the modulation signal into the loop filter port Vp 1172, is more complicated since it requires a pure integrator. However, since PFSK of the present invention requires pulse modulation, the integration on the pulses regenerates the symbol bits.

Thugs, the integrator is redundant since the modulation voltage is injected into the loop filter port directly and the integrator is redundant.

Factors Affecting Phase Accuracy in PFSK Modulation In the preferred embodiment of the present invention, three main factors affect the modulation accuracy: frequency ramp time accuracy, frequency accuracy and the loop response. The frequency ramp time accuracy of the present invention is not a significant factor since the timing references 1102 are typically 10-5 accurate, which portrays an error of less than I n in phase, which is insignificant. The frequency ramp timing accuracy could have an affect on the phase modulation mainly due to insufficient timing resolution (slow clock). Loop response is also of concern only in terms of component selection.

Frequency inaccuracy is the dominant factor affecting phase accuracy. In narrow-band PFSK using reference modulation (Figure 12a), the changes in Kif modulation factor due to temperature or aging are insignificant. The accuracy is mainly determined by the modulation voltage accuracy and calibration accuracy. In wide band PFSK using VCO modulation, accurate modulation requires accurate knowledge of the VCO modulation factor Kyco over the frequency and temperature range. The present description describes two main exemplary methods for implementing accurate calibration.

In one exemplary embodiment of the present invention, calibration factors for VCO deviation over temperature and frequency ranges is maintained in a PROM since the transmission frequency and the temperature determine affect the value of the modulation. A variety of micro-controllers are capable of temperature measurements and accurate analog-to-digital convertor (ADC) measurements of the modulation voltage to compensate for changes and to maintain accuracy of the modulation.

In another exemplary embodiment of the present invention, continuous self-calibration is performed as shown in Figure 13. The synthesizer 1300 can measure the VCO modulation factor through a high resolution (typically 10 bits) ADC 1394 connected to the control voltage from LPF 1310. Upon power up, the micro-controller measures the VCO control voltage 1398 with no modulation. Prior to the transmission or modulation with output 1318 disconnected by switch 1388, the micro-controller 1396 sets the synthesizer 1300 to a small offset above the transmission frequency (f,,) through <BR> <BR> <BR> Digital to analog convertor (DAC) 1392 and measures the control voltage VH at 1398 driving the VCO 1312. Next, the micro-controller 1396 sets the synthesizer 1300 to a small offset below the transmission frequency (f,) and measures the control voltage V,..

KVCO is then computed by the micro-controller according to Equation 5 below.

(Equation 5) This exemplary method does not require any laboratory calibration, but it require an additionally accurate ADC 1394. The need for a 10 bit ADC or more is due to the necessity to separate between V"and VL, which are close to each other.

Time and Frequency Domain Analysis Assuming that a receiver is perfectly matched for the reception of a BPSK signal resulting from the PFSK modulator of the present invention, the received symbol will have a"rise time"in the phase. If we assume that the receiver totally ignores the rise and the fall time of the symbol, the loss in sensitivity will be in decibels (dB) regarding E/Nn (c energy per bit over the noise density) according to the following equation: <BR> <BR> lOlog [i-TJ2Tb]<BR> where Tr is the rise time, and 2Tb is the symbol-width in time.

Thus, for a rise time of 10% of the symbol width, the loss is 0.22 dB.

For a rise time of 20% of the symbol width the loss is 0.45 dB. Comparing to the gain of processing BPSK versus non-coherent FSK, this loss is negligible. Since the phase accuracy that can be reached with the present invention is very high, even comparing it to the loss of the inaccuracy of conventional BPSK modulators (a 10'inaccuracy is equivalent to a loss of 0.5 dB) shows the present invention to have an advantage.

Figure 14 is a frequency domain spectrum plot (amplitude vs. frequency) comparing the sidelobe levels of conventional BPSK implementations 1402 to the PFSK signal 1404 of the present invention (using a differential pulse signal 902 shown in Figure 9), and a filtered PFSK signal 1406 of the present invention (also using a differential pulse signal 902 shown in Figure 9). As can be seen from Figure 14, PFSK attenuates the sidelobes compared to a conventionally produced BPSK signal. The plot of Figure 14 is the result of measuring, with a spectrum analyzer, a conventional BPSK random signal, PFSK with modulation pulse of 0.1 bit width, and filtered PFSK. The filtering the PFSK 1406 is linear, whereas the known commercial BPSK modulators are non linear and filtering the data does not fully reduces the sidelobes.

Low Speed BPSK Using Fractional Synthesizer Figure 15 is a block diagram detailing one implementation of the present <BR> <BR> <BR> <BR> invention. The modulator circuit 1500 of Figure 15 was constructed with a fractional<BR> <BR> <BR> <BR> <BR> <BR> synthesizer 1560 made by Rockwell Semiconductor Systems (now known as Conexant Systems Inc.). The resultant modulation on output 1518 is low speed BPSK, although QPSK is easily implemented with the same circuit. The fractional synthesizer 1560 divides the RF 1518a by Nr in fractional divider 1562, which is a simple fraction. The fraction is derived by changing the dividers of the RF such that: !/Nf= Average (I INj) The algorithm of the selection of the integers Ni is proprietary information of Rockwell Semiconductor Systems. The synthesizer 1500 has an FSK modulation port 1514, in which N, + Nd 1562 does the division such that the addition of <BR> <BR> <BR> <BR> Nd from pulse-width generator 1564 generates a frequency shift. The system provides very high frequency resolution with wide loop bandwidth. The specific circuit 1500 has a second order loop bandwidth with-10kHz bandwidth. The modulation is BPSK at a rate of 200 symbols per second (SPS). An FSK pulse of 5 kHz for 100 microseconds <BR> <BR> <BR> <BR> creates ir degrees phase change as follows:<BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> <BR> 2##f#t = #= The modulation is single sided and therefor the frequency spectrum is uneven around the carrier, but it does not effect the receiver sensitivity or out-of-band spurious noise.

Lo Speed 8PSK Using VCTCXO Modulation Figure 16 describes another embodiment of the present invention in which the symbol rate of the modulator circuit 1600 is 400 SPS. The modulation is QPSK and is implemented by changing the VCTCXO 1602 frequency according to the modulation signal 1614. In a preferred embodiment, the basic frequency of the VCTCXO 1602 is 9.6 MHZ and the modulation ratio is #3 PPM. The output frequency is 9171 MHZ. The 3 PPM modulation produces frequency offset of 2751 Hz with and error of 3 Hz. Changing the pulse width generates the eight-level Phase Shift Keying (8PSK) by shifting the level of the VREI control voltage through a digitally controlled amplifier 1693, controlled by timing controller 1691.

For a positive phase shift from circuit 1600, the frequency offset is changed by +275 1 Hz and negative phase change by-2751 Hz. Changing the phase by 45° (n/4) requires a pulse of : #/4##t=1/8#f2#*#f*#t= Af = 1/8 *2751 = 45.44 microseconds where At is generated by a 9.6 MHZ clock. A count of 436 by timing controller 1691 generates a modulation of #/4 where N = 9.6* 106 + 45.44 * l o-6 = ~ 436.

Further, a count of 872 by timing controller 1691 generates a modulation ofn,'2, a count of 1309 by timing controller 1691 generates modulation of 3#/4 etc.

The bi-level modulation is required in order to produce a balanced frequency spectrum.

It is possible to use positive pulses only in Figure 16 by modulating-A as 2n at the expense of an imbalanced spectrum, which might create difficulties in the receiver.

The possible 3 Hz error produces an error of 0. 12°. The resolution of the pulse-width counter produces an even smaller error. The major error is the accuracy of the 3-PPM, which is from the VCTCXO 1602, depended and must be calibrated. Note that the timing controller compensates inaccuracy in the modulating voltage by programming the count.

Low Speed N Level PSK Using DDS Figure 17 is a block diagram describing a narrow bandwidth Pulsed Frequency Shift Keying (PFSK) modulator 1700 which can encode N levels (such as 8) and in which the reference frequency is generated using a direct digital synthesizer (DDS). As described above in conjunction with Figure 5, a DDS circuit can produce a SINE or COSINE signal from a stored representation. In the embodiment of the present invention shown in Figure 17, the PFSK is implemented by using a DDS as the reference frequency with the modulation being input at 1738 to control the address of PROM 1730 through adder 1734. The circuit 1700 implements the PFSK very accurately, at the expense of additional size, power consumption and cost. Note that the phase noise within the loop bandwidth will be higher than the implementation described in conjunction with the embodiment of Figure 16. However, the embodiment described in conjunction with Figure 17 does not need any calibration.

High Speed BPSK for DSSS Using VCO Modulation Referring once again to the circuit described in Figure 13, DSSS modulation has very little DC component since the direct sequence of the spread spectrum has short successive ONE's and ZERO's (due to the randomizing of the information). For cxample, a processing gain of 255 has a maximum of 8 successive chirps. At a rate of 1 mega-chirps per second (MCPS), the chirp lasts eight microseconds. A typical loop bandwidth of 10 kHz will not effect the modulation. For 1 MCPS BPSK modulation using PFSK of the present invention shown in Figure 13, the modulating pulse time will be 100 microseconds for phase change of +x/2 as shown as follows: Af=+ 1/4At=+2. 5MHZ Various AppHcations Utilizing the Present Invention<BR> Referring Figures 18a and 18b, any of the embodiments of the present invention may he utilized in transmitters 1802,1804 or receivers 1806,1808 of wircless 1800 or wired 1810 telecommunications devices.

Conclusion Although specilic embodiments have becn illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. For example, the present invention may be utilized in any telecomrnunications circuit for transmitted wired or wireless information regardless of the communications medium. Accordingly, this application is intended to cover any adaptations or variations of the invention. ft is manifestly intended that this invention be limited only by the following claims and equivalents thereof.