**PHASE MODULATORS**

*;*

**H03K5/13***;*

**H03K7/08***;*

**H03L7/081***;*

**H03L7/187***; (IPC1-7): H03K7/08; H03L7/18*

**H03L7/197**FR2195873A1 | ||||

US3876949A | ||||

EP0147307A2 |

1. | : A phase modulator comprising a circuit element (1) arranged for providing an output voltage (V) which can be changed from an initial level (V^), means (3) operative for effecting change, at a time dependent upon receipt by the phase modulator of a clocking edge of a reference clocking signal (^{F}_{re}f), of the output voltage (V) at a constant rate for a predetermined duration, means (4) operative for subseqeuently returning the output voltage of the circuit element (1) to said initial level at a constant rate, a generator (6) for generating an output pulse in dependence upon the return of the output voltage to said initial level, and means (5) for altering the rate of change or the rate of return of the output voltage of the circuit element in dependence upon a control signal, thereby enabling the time of generation of the output pulse to be varied relative to the clocking edge in dependence upon the control signal. |

2. | A phase modulator according to claim 1, wherein the time of generation of the output pulse is varied relative to the clocking edge in dependence upon the duration of the control signal. |

3. | A phase modulator according to claim 1 or claim 2, wherein the circuit element (1) is in the form of an 27 integrator. |

4. | A phase modulator according to claim 1, claim 2 or claim 3, wherein the means (3) operative for effecting change is a constant current source which is enabled by the reference clocking signal (F_{ref}), the means (4) operative for returning the output voltage (V) is a constant current source enabled by an enabling signal generated by the generator (6), and the means (5) for altering the rate of change or rate of return of the output voltage is a constant current source enabled by the control signal. |

5. | A phase modulator according to any one of the preceding claims wherein the generator (6) comprises a comparator (7) for comparing the output voltage (V) of the integrator (2) with a reference voltage (V4) to produce an output signal dependent upon the comparison, and a bistable circuit (8) for generating the output pulse and the enabling signal in response to the reference clocking signal (F_{re} ) and the output signal of the comparator (7). |

6. | A frequency synthesiser comprising a phase locked loop (PLL) having a voltage controlled oscillator (11) for producing an output signal which is afforded to a phase detector (13) via a divider (12), which phase detector is 28 arranged for providing a control signal for the voltage controlled oscillator in the presence of a phase difference between a reference signal (F__{e}f) from a reference source (14) and the signal afforded thereto from the divider (12), enabling means for enabling the division ratio of the divider (12) to be varied in a fractional N mode so that the output signal can be frequency divided in steps smaller than the frequency of the reference signal, and compensating means for compensating for a ripple signal tended to be produced in the PLL and the enabling means, the ripple signal causing frequency modulation of the output signal, wherein the compensating means comprises a phase modulator according to any one of claims 1 to 5, which phase modulator is operative for delaying, in dependence upon the control signal, the reference signal relative to the signal afforded to the phase detector or to delay the signal afforded to the phase detector relative to the reference signal thereby to compensate for the ripple signal, and means for generating the control signal in response to data fed to the enabling means. |

7. | A frequency synthesiser according to claim 6, wherein the means for generating the control signal comprises a down counter (29) which is clocked in dependence upon the output signal from the voltage controlled oscillator (11), and is fed with data from an arithmetic unit (16) of the enabling means. 29 . |

8. | A frequency synthesiser according to claim 6 or claim 7, wherein the phase modulator is operative to delay in dependence upon a plurality of control signals, respective control signals being generated by respective means for generating the control signals, wherein each means is fed with data from a different decade of an arithmetic unit (16) of the enabling means. |

This invention relates to phase modulators, and in particular to the use of such phase modulators in frequency synthesisers of the fractional N type.

A known type of phase modulator can delay pulses of an input pulse train by an amount which is dependent upon an analogue control signal. Such a phase modulator can be included in a frequency synthesiser of the fractional N type in order to provide a means for compensating for a ripple signal tending to be produced in the synthesiser, which ripple signal causes frequency modulation of an output signal of the synthesiser.

The use of such a phase modulator in frequency synthesisers of the fractional N type is disadvantageous in that the analogue control signal is derived from a logic signal produced at an output of an arithmetic unit, and this necessitates the inclusion of a means for converting the logic signal into the analogue control signal.

A digital to analogue converter (DAC) is conventionally used for the said means for converting, but the need to include such a converter is disadvantageous in that the DAC cannot be easily integrated into the type of logic array now generally used to implement digital

circuitry of synthesisers of the fractional N type, and a high degree of linearity in the DAC is required for cancellation of the ripple signal.

The present invention is directed to providing a phase modulator which can be incorporated into a frequency synthesiser of the fractional N type so as to eliminate the need to include digital to analogue converter.

According to the present invention there is provided a phase modulator comprising a circuit element arranged to provide an output voltage which can be changed from a initial level, means operative to effect change, at a time dependent upon receipt by the phase modulator of a clocking edge of a reference clocking signal, of the output voltage at a constant rate for a predetermined duration, means operative subsequently to return the output voltage of the circuit element to said initial level at a constant rate, a generator for generating an output pulse in dependence upon the return of the output voltage to said initial level, and means for altering the rate of change or the rate of return of the output voltage of the circuit element in dependence upon a control signal, thereby enabling the time of generation of the output pulse to be varied relative to the clocking edge in dependence upon the control signal. The time of generation of the output pulse is

preferably varied relative to the clocking edge in dependence upon the duration of the control signal.

Phase modulators embodying the present invention are advantageous in that they can be incorporated into fractional N type frequency synthesisers in order to eliminate the need to include a DAC, and consequently, the aforesaid disadvantages can be alleviated.

The circuit element of the phase modulator may be an integrator. The means operative to effect change may be a constant current source which is enabled by the reference clocking signal, the means operative to return the output voltage nay be a constant current source enabled by an enabling signal generated by the generator, and the means for altering the rate of change or rate of return of the output voltage may be a constant current source enabled by the control signal.

The generator may comprise a comparator for comparing the output voltage of the integrator with a reference voltage to produce an output signal dependent upon the comparison, and a bistable circuit for generating the output pulse and the enabling signal in response to the reference clocking signal and the output signal of the comparator. According to the present invention there is also

provided a frequency synthesiser of the fractional N type comprising a phase locked loop (PLL) having a voltage controlled oscillator for producing an output signal which is afforded to a phase detector via a divider, which phase detector is arranged to provide a control signal for the voltage controlled oscillator in the presence of a phase difference between a reference signal from a reference source and the signal afforded thereto from the divider, enabling means for enabling the division ratio of the divider to be varied in a fractional N mode so that the output signal can be frequency divided in steps smaller than the frequency of the reference signal, and compensating means for compensating for a ripple signal tending to be produced in the PLL and the enabling means, the ripple signal causing frequency modulation of the output signal, wherein the compensating means comprises a phase modulator as defined above, which phase modulator is operative to delay, in dependence upon the control signal, the reference signal relative to the signal afforded to the phase detector or to delay the signal afforded to the phase detector relative to the reference signal thereby to compensate for the ripple signal, and means for generating the control signal in response to data fed to the enabling means. The means for generating the control signal may

comprise a down counter which is clocked in dependence upon the output signal from the voltage controlled oscillator, and is fed with data from an arithmetic unit of the enabling means. The phase modulator may alternatively be arranged to be operative to delay in dependence upon a plurality of control signals, respective control signals being generated by respective means for generating the control signals, wherein each means is fed with data from a different decade of an arithmetic unit of the enabling means.

The invention will now be further described by way of example with reference to the accompanying drawings, in which: Figure 1 is a schematic block diagram of a phase modulator embodying the present invention;

Figure 2 is a waveform diagram used to assist explanation of the operation of the phase modulator of Figure 1; Figure 3 is a block diagram of a phase locked loop indirect frequency synthesiser;

Figure 4 is a block diagram of a fractional N frequency synthesiser;

Figure 5 is a block diagram of a compensated fractional N frequency synthesiser;

Figure 6 is a block diagram of a fractional N frequency synthesiser incorporating a phase modulator embodying the present invention;

Figure 7a is a block diagram of a means for generating a control signal for the phase modulator;

Figure 7b is a waveform diagram to be used to explain the operation of the means of Figure 7a;

Figure 8 is a block diagram of an alternative fractional N frequency synthesiser incorporating a phase modulator embodying the present invention; and

Figure 9 is a waveform diagram to show the timing of various events in the arrangement illustrated in Figure 8.

In Figure 1, there is shown a phase modulator which is arranged to receive a reference clocking signal ^{F }ref ^{an< }^ * ^{s } operative to provide an output pulse train, the pulses of which are delayed (relative to the clocking edges which give rise to the generation of the output pulses) by an amount which is dependent upon a control signal. The phase modulator comprises a circuit element in the form of an integrator 1 which is made up of an operational amplifier 2 and a feedback capacitor C^. The output voltage V of the integrator 1 is set at an initial predetermined level Vj, and the positive input to the operational amplifier 2 is connected to a reference

voltage V2.

The negative input to the operational amplifier 2 is connected to a constant current source 3 which is operative to permit a constant current I _{c } to flow into the integrator 1 and also to a pair of constant current sources 4 and 5 which are operative to permit constant currents I3 and l^ to flow from the integrator 1.

The phase modulator also comprises a generator 6 which includes a comparator 7 in the form of an operational amplifier and a bistable circuit such as a flip-flop 8. The negative input of the comparator 7 is connected to a reference voltage V4 and the positive input is connected to the output of the operational amplifier 2 of the integrator 1. The flip-flop 8 is operative to provide an enabling signal at its Q^ output, which enabling signal is used to switch the constant current source 4, and also to provide the output pulse train at its Q^ output. The flip-flop 8 is clocked by the reference clocking signal F _{re }f and is arranged so that the value of the D input (which is constantly held at logical 1 D=l) is transferred to the Q^ output on every transition of the reference signal F _{re }f from logical 1 to logical 0 (1/0 transition). The output of the comparator 7 is operative to reset the Q^ output to logical zero in

dependence upon the output voltage V of the integrator 1.

The operation of the phase modulator of Figure 1 will now be described with reference to Figure 2.

The output voltage V of the integrator 1 is set to be V^ when the phase modulator is in steady state, that is, when the constant current sources 3,4 and 5 are all switched off. The constant current source 3 is arranged to be switched on for a duration of T^ which is half a period of F _{re }f, for example, when the level of F _{re }f is high.

When the constant current source 3 is switched on, the constant current I _{c } flows into the integrator 1 which causes the output voltage V of the integrator to fall at a constant rate from the initial value of Vι_. The total drop in voltage isΔv over the period of T^ and is indicated by the dotted line A in Figure 2.

At the end of the period T _{] }_, at the falling edge of F _{re }f, the constant current source 3 is switched off and the output voltage V of the integrator 1 ceases to fall. At this point, the flip-flop 8 is triggered by the falling edge (1/0 transition) of F _{re }f and the Q^ output becomes high. The high Q^ output of the flip-flop 8 enables the constant current source 4 and hence, the constant current 1 flows from the integrator 1 thereby causing the output voltage V of the integrator 1

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to rise (as indicated by the dotted line B in Figure 2).

When the output voltage V of the integrator 1 becomes equal to the reference voltage V4 (which is equal to V^) after a time of T2, the comparator 7 generates an output pulse of voltage V3. This output pulse resets the flip-flop 8 so that the Q _{j } output returns to logical zero and the constant current source 4 is switched off.

The change of the Q^ output from 1 to 0 corresponds to a rise of 0 to 1 of the Q^ output of the flip-flop 8. The rising edge of the Q^ output is an output pulse of the output pulse train of the phase modulator.

It can be seen from Figure 2 that the time at which the flip-flop 8 is reset, and hence the time of generation of the rising edge of the Q^ output, can be varied by effectively altering the rate of fall or rise of the output voltage V of the integrator 1.

In this embodiment a further constant current source 5 is connected to the negative input of the integrator 1 and is switched on by a control signal fed to the phase modulator. When switched on, a constant current Id flows from the integrator 1 which effectively alters the rate of rise or fall of the output voltage V of the integrator 1.

In the example shown in Figure 2 the currentΔla is switched on for a time duration T _{p } when the current I _{c }

is flowing into the integrator 1. This has the effect of reducing the rate of fall of output voltage V of the integrator 1, which means that the output voltage V of the integrator 1 does not fall to the levelΔv below V^ during the time (Tχ> for which the current I _{c } flows. Consequently, when the currentΔI<j flows, the output voltage V of the integrator 1 is returned to V^ sooner than it would otherwise have been (see voltage profile C in Figure 2) had the constant current source 5 not been enabled, and the flip flop 8 is reset earlier.

The time at which the output Qi rises from logical 0 to 1 can thus be varied in dependence upon the timing and duration T _{p } of the control signal relative to the clocking edge of the reference signal F _{re }f. Therefore, the output pulses of the output pulse trainfrom the phase modulator can be delayed relative to the clocking edge of F _{re }f by an amount dependent upon the duration of the control signal.

Referring now to Figure 3, there is shown an indirect frequency synthesiser 10. The synthesiser 10 comprises a phase lock loop (PLL) having a voltage controlled oscillator (VCO) 11 the output frequency of which

^{F }oUT * ^{s } ^ ^{ed v a a var }i ^{aD }l ^{e } divider 12, having a division ratio N, to a phase detector 13. The phase detector 13 also receives from a reference source 14, a

reference signal having a reference frequency F _{e }^ and provides a control signal to the oscillator 11 along a loop 15 in the presence of a phase difference between the signals on its two inputs. The sense of the control signal from the phase detector 13 to the oscillator 11 is such that any phase difference between the input signals to the phase detector 13 is reduced to a minimum and hence any difference in the frequencies of these two input signals is reduced to zero. Thus, in a steady state the output frequency of the synthesiser

It can be seen from expression (1) that the minimum change in output frequency, obtained by incrementing or decrementing the division ratio N by 1, is F _{f }. Thus, if small frequency output steps are required with the synthesiser illustrated in Figure 3 this can only be achieved by decreasing the reference frequency F _{ψ } However, as previously stated, with relatively low values of F _{f } the system becomes slow to respond to demands for changes in the output frequency.

It is evident from expression (1) that small frequency output steps can be achieved with fast response times by providing apparatus which will permit fractions

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of N to be utilised. Such synthesisers are known as fractional N frequency synthesisers, an embodiment of which is illustrated in Figure 4.

In the synthesiser shown in Figure 4 a relatively high value for the reference frequency F.-^ is utilised, typically lOOKHz. Small output frequency steps are obtained by selectively controlling the division ratio of the variable divider 12 between N and N plus or minus an integer over a number of cycles of the reference frequency F _{re }f I can be realised that the instructed pattern of, for example, N and N + 1 division ratios, will give a mean value of N, termed N mean, such that the output frequency

F _{0UT } = F _{ref } x N mean (2)

In the synthesiser illustrated in Figure 4 the division ratio of the variable divider 12 is controlled by means of an arithmetic unit 16 and an adder 17. The arithmetic unit 16 is arranged to receive the reference frequency F _{* } along a line 18 and data indicative of the output frequency steps less than F _{e }^ along a data bus 19. The output of the arithmetic unit 16 is connected to the adder 17 by line 20 and the adder 17 is also arranged to receive data indicative of the output

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frequency steps greater than or equal to F _{f } along a data bus 21. The desired N/(N + 1) pattern appropriate to generate the required N mean for a chosen output frequency may be obtained by an arithmetic unit having a BCD adder in combination with D-type flip-flops (not shown) for each decade of decimal N required. For example, to obtain a fractional part of N, such as 0.789, three decades would be required. Such an arrangement may extend for as many decades as required with the carryout signal of any decade providing the carry in signal of the next significant decade; with the carry out signal of the most significant decade providing the "+1" input instruction to the adder 17 along line 20 from the arithmetic unit 16.

The data word fed to the arithmetic unit 16 is

F x Offset from multiple of F _ _{f } ______ ^{ret }

Minimum step of F _{ooτ } ^{F }ref * ^{3 }'

The first of these terms defines the capacity of the arithmetic unit 16 and the second term is the fractional offset, denoted by d. For example, consider a system with F _{ψ } = 100 KHz, minimum step of 100Hz with the output frequency F _{oUT } of the synthesiser set to 45.6789 MHz. The value of division ratio N for the variable divider is

45.6 106 = 456.

105

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This leaves an offset from the multiple of F _{ref } of 78.9 KHz and hence the data word fed to the arithmetic unit 16 is

100 x 10' x 78.9 x _lθ! 789 100 100 . 10 ^{3 }

Therefore, the required capacity of the arithmetic unit 16 is 1000 and three decades will be required.

This type of system has the defect of poor spectral purity of the output signal because the continuously varying division ratio means that pulses from the variable divider 12 arrive at the input to the phase detector 13 at varying tiroes to those arriving at the other input of the phase detector 13 from the reference source 14. The output of the phase detector 13 will therefore contain AC components, generally called a ripple signal, at frequencies related to the offset of the output frequency ^{F }OUT ^ ^{rom a } whole multiple of the reference frequency F _{e }£. The ripple signal is fed around the loop and causes frequency modulation of the oscillator 11; producing poor spectral purity.

Figure 5 illustrates a compensated fractional N synthesiser in which the spectral purity of the output signal F _{QUT } may be improved. The data at the output of the D-type flip flops (not shown) in the arithmetic

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unit 16 represent the difference in phase which would exist between the input signals to the phase detector 13 if the output from the oscillator 11 were spectrally pure. Therefore the data at the output of the arithmetic unit 16 may be converted to analogue form by a digital to analogue (D/A) converter 24 and the analogue signal used to control a voltage controlled delay element 26 which may be positioned at either input i.e. (positions A or B) to the phase detector. If the control signal to the delay element 26 from the D/A converter 24 is at the correct level, the phase detector does not perceive the phase perturbations caused by the ripple signal resulting from the variation in the division ratio of the variable divider 12. Hence, there is no spurious frequency modulation of the output signal from the oscillator 11. However, the use of a voltage controlled delay element 26 is disadvantageous as it necessitates the use of the digital to analogue converter 24 which imposes limitations as described earlier. The problems involved with using a digital to analogue converter can be avoided by replacing the voltage controlled delay element 26 with a phase modulator according to the present invention.

Referring now to Figure 6, a phase modulator 27 according to the present invention is shown to be

positioned so as to delay the clocking edges of the reference clocking frequency F _{re }f input of the modulator 27. In this case, the phase modulator delays incoming clocking edges by an amount which is dependent upon the duration rather than voltage amplitude of a control signal. The modulator 27 may be of the form illustrated in Figure 1.

The control signal is derived from a generating means 28 which is clocked by a clock signal having a frequency which is equal to F _{out }/10. The generating means 28 is illustrated in more detail in Figure 7a where the generating means 28 is shown to comprise a down counter 29 which receives data from the arithmetic unit 16. The down counter 29 receives the reference clocking frequency ^{F }ref which clocks the counter 29 to load with data from the arithmetic unit 16 once per F _{re }f cycle on a logical 1/0 transition of F _{re }f. The down counter 29 is clocked by the output of a NAND gate 30 which has two inputs, one being at logical '0' when the down counter 29 has counted down to zero from what ever number has been loaded therein from the arithmetic unit 16, and the other being clocked at a frequency of ^{F }©ut ιo. The control signal is generated at the Q _{2 } outpout of a flip-flop 31, which is clocked by the Fout/io signal, in dependence upon the 'O* on zero state output of thedown counter 29

and the clocking frequency F _{ou }t/l ^{n }« The reference frequency F _{re }f _{» } when zero, resets the flip-flop 31 so that the Q _{2 } output (i.e. the control signal) is zero. Figure 7b shows waveforms for the generating means 28 for the simple case when the data from the arithmetic unit

16 is equal to 3.

The relationship between the duration of the control signal and the data from the arithmetic unit 16 will now be explained on the basis that the fractional N frequency synthesiser of Figure 6 has an output frequency of :

) ^{F }out - (N+d )F _{ref } ( 4 ) where: N is an integer; and d is the fractional offset (0<d<l);

(b) and that the output spectrum of the synthesiser is pure (that is, the edges of the F _{out } signal are regularly spaced).

When the division ratio of the synthesiser is N, the time T _{var } between edges of the pulses of the signal emerging from the variable divider 12 is:

T _{var } = N = N = NT _{ref } (5) ^{F }OUt (N+d)F _{ref } (N+d) where T _{re }f is the period of the reference frequency F _{ref }.

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As can be seen from equation (5), the time T _{var } is not equal to T _{re }f and consequently, the period between the reference signal edge and the variable divider output edge will vary in dependence upon N and d. If at some time the reference signal edge and the variable divider output edge coincide exactly, then the next variable divider output edge will precede the next reference signal edge by:

-Δ-t = T _{ref } - T _{var } = T _{ref } - WT _{re: }r_

(N+d)

α T _{ref } (6)

(N+d)

The next reference signal and variable divider edges zf will be separated by twice this amount, the next by three times and so on, until (N+l) is entered into the variable divider 12. It can be shown that the data at the output of the flip-flops (not shown) in the arithmetic unit 16 increases in the same pattern as the separation of the inputs to the phase detector 13. Hence, this data can be used to generate a cancellation signal in order to remove the ripple signal. If the phase detector 13 is not to impose

serious frequency modulation on the output signal ^{F }out (°" ^{ue to tne } ripple signal), then either of the inputs to the phase detector 13 can be delayed by an appropriate amount, or a cancelling signal may be added at its output. In Figure 6, the phase modulator 27 is positioned at the reference frequency input to the phase detector 13.

In Figure 6, the phase modulator 27 is constructed in accordance with Figure 1. Figure 2 is an example of the waveforms of signals at various parts of the phase modulator 27 and is referred to in order to explain the relative timing of pulse edges.

In the phase modulator 27, the constant current I _{c } flows during the fixed period T^ which is chosen to be equal to £ T _{re }f. At the end of the period T^, the current I _{c } is switched off and the current 1^ is switched on. The current I _{ς }| flows until the voltage at the integrator output has returned to the value it had before the current 1^ was switched on. Therefore the voltage drop at the output the integrator due to the flow of current I _{c } is:

V = T _{λ } I _{c } = T _{2 } Id (7)

Cl c _{λ }

- T_. I τ _{2 } id

where T _{2 } = time for which 1,3 must flow for the integrator 1 output voltage V to be restored to V _{j }_.

It has already been shown that the inputs to the phase detector 13 increase their separation byΔt during a whole cycle of the phase detector. If the reference signal F _{re }f is delayed by a time period of T _{0 }, which T _{0 } is equal to T^ + T _{2 }, and then fed into the phase detector 13 reference input, the separation of the phase detector inputs can be kept constant by appropriate variation of the constant currents I _{c } or I3, and hence effectively varying the rate of change of the output voltage V of the integrator 1 over time ^ or T _{2 }.

If the phase detector input signals were coincident at their last occurrence, then the reference signal must occur early by an amount Δt if they are to remain coincident at their next occurrence. Hence, the new delay imposed by the phase modulator 27 must be (T _{0 } -Δt) which can be achieved by switching on a current Δ 1^ for a duration of p which is effective to reduce the current I _{c } for the duration Tp.

Equating the integrator output voltage change over time T _{j } to that over (T -Δt) gives the following: (I _{c } - I _{d }) T _{p } + I _{c } (T _{X } - T _{p })=(T _{2 } -Δt) I _{d } from which it can be shown that: ld = Id Δt (8)

^{T }P

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Substituting for Δt

Δ d ^{g } id a τ _{ref } (9 ^{) }

T _{p }(N+d)

Hence the required delay can be achieved by switching on l<a for a time T _{p } according to the following relation, rearranged from equation (9):

T _{p } - d T _{ref } x I _{d } (10)

is chosen so that it equals I _{d }, then:

T _{p } = d T _{ref } (11)

(N+d) The time T _{p } can be expressed in terms of the output frequency by substituting equation (4) into equation (11)

T _{p } = d x T _{out } (N+d) = d T _{out } (12)

(N+d) where T _{out } = 1

^{F }out

Hence, the current A I _{d } ( ^{= }Id) ^{must } flow for d

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cycles of the output frequency F _{OU }f

For each reference edge arriving at the phase detector 13 after the time at which the phase detector inputs were coincident, the length of time Tp for which Δlp must flow in order to delay the reference edges to maintain coincidence, increases every cycle in the manner d,2d,3d .......... The data at the outputs of the flip-flops in the arithmetic unit 16 increase in the same fashion except that the actual value of the data is not d,2d,3d , but:

F _{re }f x that series of values (13) minimum step size Therefore a control signal for switching on the current__\ I _{d } in the phase modulator 27 can be derived from the generating means described with reference to Figures 7a and 7b. The down counter 29 is set to an initial value equal to the data at the output of the arithmetic unit (to give the d,2d,3d dependence) and clocked at the output frequency F _{re }f (to give the inverse proportional dependence on (N+d)). A *zero state* signal is generated which is logical '1* when the down counter 29 is clocked and counting down, and becomes logical '0' when the down counter 29 has counted down to zero. This signal terns on a current equal to

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I Minimum step size ( 14 )

^{F }ref

In a particular embodiment, the synthesiser may cover 40 to 70 MHz, with F _{re }f = 100 KHz and have a minimum step size of 100 Hz.

A two-modulus prescaler, commonly a 10/11 divider (see divider 22 in Figure 6) can be employed to reduce the output frequency F _{ou }t to a value of d, the offset frequency, which can be processed by lower power logic. The output of the divider 22 clocks the generating means 28 and is fed to the variable divider 12. Because the width of the pulses driving the down counter 29 is multiplied by 10 (due to the division by the divider 22), the value of the current Δ I _{d } switched by the control signal from the generating means 28 must be divided by 10.

The division ratio of the divider 22 must be either 10 or 11 all the time that the down counters are being clocked. If a mixture of F _{ou }t/10 and F _{out }/ll rate pulses is counted, the linearity of the relationship between the number loaded into the down counter 29 and the mean current switched will be destroyed. The divide by 11 state could last as long as 110 cycles of 40 MHz, i.e.

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2.75 microseconds.

Referring now to Figure 8 , an alternative fractional N synthesiser is shown in which three generating means 30 , 31, 32 and hence three down counters, are included. The down counter 29 of Figure 7a, when incorporated into the generating means 28 , could have to count as many as 999 pulses at a rate as low as 4 Mhz. This would take 250 microseconds , and could not be completed between two reference rate edges 10 microseconds apart. This problem is overcome by using three down counters, each capable of 10 states, rather than one down counter capable of 1000 states. The three down counters, such as 10 KHz, lKHz, and 100Hz respectively, are all clocked by the output of the divider 22 , but each down counter is loaded with data from one decade of the arithmetic unit 16. Each down counter switches a different current__V lχ , Δl _{2 } , Δl3 , scaled in the ratio 100 : 10 : 1 for the 10 KHz, lKHz and 100Hz counters respectively. The maximum rundown time of any counter is now a duration of 10 cycles of 4 Mhz, i . e . 2.5 microseconds. This can be accommodated within the 10 microsecond period of the reference frequency F _{re }f .

Figure 9 illustrates the timing of various events occurring in the embodiment of Figure 8.

The down counter 30 starts to run as soon as possible af ter T^ , maximum delay = 10 cycles of 40 MHz = 0. 25 ιs

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(See period A). Period B illustrates when the phase detector rising edge must occur. This is because variable dividers provide for a divide by 11 prescaler ratio immediately after they give an output edge. This puts a limit on the system phase offset.

All divide by 11 states of the prescaler must end before T4. The maximum time to achieve this = 110 cycles of 40MHz « 2.75/ s. D denotes the edge of the delayed reference signal which is fed to the phase detector.