CROSS-REFERENCE TO RELATED APPLICATION(S)

[0001] This application claims benefit of and priority to U.S. Patent Application No. 17/662,389, filed May 6, 2022, which is herein incorporated by reference in its entirety.

TECHNICAL FIELD

[0002] Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to voltage-controlled oscillator (VCO) circuits with commonmode inductors.

BACKGROUND

[0003] Wireless communication networks are widely deployed to provide various communication services such as telephony, video, data, messaging, broadcasts, and so on. Such networks, which are usually multiple access networks, support communications for multiple users by sharing the available network resources. For example, one network may be a 3G (the third generation of mobile phone standards and technology), 4G, 5G, or later system, which may provide network service via any one of various radio access technologies (RATs) including EVDO (Evolution-Data Optimized), IxRTT (1 times Radio Transmission Technology, or simply lx), W-CDMA (Wideband Code Division Multiple Access), UMTS-TDD (Universal Mobile Telecommunications System - Time Division Duplexing), HSPA (High Speed Packet Access), GPRS (General Packet Radio Service), or EDGE (Enhanced Data rates for Global Evolution). Such multiple access networks may also include code division multiple access (CDMA) systems, time division multiple access (TDMA) systems, frequency division multiple access (FDMA) systems, orthogonal frequency division multiple access (OFDMA) systems, single-carrier FDMA (SC-FDMA) networks, 3 ^rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) networks, Long Term Evolution Advanced (LTE-A) networks, and New Radio (NR) networks. Other examples of wireless communication networks may include WiFi (in accordance with IEEE 802.11), WiMAX (in accordance with IEEE 802.16), and Bluetooth® networks. [0004] A wireless communication network may include a number of base stations that can support communication for a number of mobile stations. A mobile station (MS) may communicate with a base station (BS) via a downlink and an uplink. The downlink (or forward link) refers to the communication link from the base station to the mobile station, and the uplink (or reverse link) refers to the communication link from the mobile station to the base station. A base station may transmit data and control information on the downlink to a mobile station and/or may receive data and control information on the uplink from the mobile station.

[0005] In order to transmit or receive data and/or control information, the radio frequency front-end of the base station and/or the mobile station may include one or more frequency synthesizers to generate oscillating signals used for upconverting baseband signals and downconverting radio frequency (RF) signals. At least one of the frequency synthesizers may include a voltage-controlled oscillator (VCO) for tuning an oscillating signal to different frequencies.

SUMMARY

[0006] The systems, methods, and devices of the disclosure each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of this disclosure as expressed by the claims that follow, some features will now be discussed briefly. After considering this discussion, and particularly after reading the section entitled “Detailed Description,” one will understand how the features of this disclosure provide the advantages described herein.

[0007] Certain aspects of the present disclosure generally relate to techniques and apparatus for reducing phase noise, ripple voltage, and/or area of voltage-controlled oscillators (VCOs).

[0008] Certain aspects of the present disclosure provide a VCO circuit. The VCO circuit generally includes a resonant circuit having a main inductor, a p-type active negative transconductance circuit coupled to the resonant circuit, a p-side commonmode inductor coupled between the p-type active negative transconductance circuit and a first voltage rail, an n-type active negative transconductance circuit coupled to the resonant circuit, and an n-side common-mode inductor coupled between the n-type active negative transconductance circuit and a second voltage rail. [0009] Certain aspects of the present disclosure provide an electronic device comprising the VCO circuit described herein.

[0010] Certain aspects of the present disclosure are directed to a method of fabricating a VCO circuit. The method generally includes forming a resonant circuit having a main inductor; forming a p-type active negative transconductance circuit coupled to the resonant circuit; forming a p-side common-mode inductor coupled between the p-type active negative transconductance circuit and a first voltage rail; forming an n-type active negative transconductance circuit coupled to the resonant circuit; and forming an n-side common-mode inductor coupled between the n-type active negative transconductance circuit and a second voltage rail.

[0011] Certain aspects of the present disclosure are directed to method of oscillation. The method generally includes providing power to a VCO circuit and generating an oscillating signal with the powered VCO circuit, across a resonant circuit of the VCO circuit. The VCO circuit generally includes the resonant circuit having a main inductor, a p-type active negative transconductance circuit coupled to the resonant circuit, a p-side common-mode inductor coupled between the p-type active negative transconductance circuit and a first voltage rail, an n-type active negative transconductance circuit coupled to the resonant circuit, and an n-side common-mode inductor coupled between the n-type active negative transconductance circuit and a second voltage rail.

[0012] To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the appended drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] So that the manner in which the above-recited features of the present disclosure can be understood in detail, a more particular description, briefly summarized above, may be had by reference to aspects, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only certain typical aspects of this disclosure and are therefore not to be considered limiting of its scope, for the description may admit to other equally effective aspects.

[0014] FIG. 1 is a diagram of an example wireless communications network, in which aspects of the present disclosure may be practiced.

[0015] FIG. 2 is a block diagram of an example access point (AP) and example user terminals, in which aspects of the present disclosure may be practiced.

[0016] FIG. 3 is a block diagram of an example transceiver circuit, in which aspects of the present disclosure may be practiced.

[0017] FIG. 4 is a schematic diagram of an example voltage-controlled oscillator (VCO) with common-mode inductors, in accordance with certain aspects of the present disclosure.

[0018] FIGs. 5A and 5B are layout diagrams of example topologies for VCOs with common-mode inductors, in accordance with certain aspects of the present disclosure.

[0019] FIGs. 6A, 6B, and 6C illustrate example conceptual layout diagrams of common-mode inductors, in accordance with certain aspects of the present disclosure.

[0020] FIG. 7 is a flow diagram of example operations for fabricating a VCO circuit, in accordance with certain aspects of the present disclosure.

[0021] FIG. 8 is a flow diagram of example operations for generating an oscillating signal, in accordance with certain aspects of the present disclosure.

[0022] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one aspect may be beneficially utilized on other aspects without specific recitation.

DETAILED DESCRIPTION

[0023] Certain aspects of the present disclosure generally relate to voltage- controlled oscillators (VCOs) with common-mode inductors and to techniques and apparatus for reducing the phase noise of such VCOs. Certain aspects may additionally or alternatively relate to techniques and apparatus for reducing the ripple voltage and/or area of VCOs with common-mode inductors.

[0024] Various aspects of the disclosure are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure disclosed herein, whether implemented independently of or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim.

[0025] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0026] As used herein, the term “connected with” in the various tenses of the verb “connect” may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., that element A is indirectly connected with element ). In the case of electrical components, the term “connected with” may also be used herein to mean that a wire, trace, or other electrically conductive material is used to electrically connect elements A and B (and any components electrically connected therebetween).

An Example Wireless System

[0027] FIG. 1 illustrates a wireless communications system 100 with access points 110 and user terminals 120. For simplicity, only one access point 110 is shown in FIG. 1. An access point (AP) is generally a fixed station that communicates with the user terminals and may also be referred to as a base station (BS), an evolved Node B (eNB), or some other terminology. A user terminal (UT) may be fixed or mobile and may also be referred to as a mobile station (MS), an access terminal, user equipment (UE), a station (STA), a client, a wireless device, or some other terminology. A user terminal may be a wireless device, such as a cellular phone, a personal digital assistant (PDA), a handheld device, a wireless modem, a laptop computer, a tablet, a personal computer, etc.

[0028] Access point 110 may communicate with one or more user terminals 120 at any given moment on the downlink and uplink. The downlink (i.e., forward link) is the communication link from the access point to the user terminals, and the uplink (i.e., reverse link) is the communication link from the user terminals to the access point. A user terminal may also communicate peer-to-peer with another user terminal. A system controller 130 couples to and provides coordination and control for the access points.

[0029] System 100 employs multiple transmit and multiple receive antennas for data transmission on the downlink and uplink. Access point 110 may be equipped with a number Nap of antennas to achieve transmit diversity for downlink transmissions and/or receive diversity for uplink transmissions. A set N _u of selected user terminals 120 may receive downlink transmissions and transmit uplink transmissions. Each selected user terminal transmits user-specific data to and/or receives user-specific data from the access point. In general, each selected user terminal may be equipped with one or multiple antennas (i.e., Nut > 1). The N _u selected user terminals can have the same or different number of antennas.

[0030] Wireless system 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. System 100 may also utilize a single carrier or multiple carriers for transmission. Each user terminal 120 may be equipped with a single antenna (e.g., in order to keep costs down) or multiple antennas (e.g., where the additional cost can be supported). [0031] The access point 110 and/or user terminal 120 may include one or more frequency synthesizers to generate periodic signals used for signal transmission and/or reception. At least one of the frequency synthesizers may include a VCO with common-mode inductors, where the VCO implements techniques for reducing phase noise, ripple voltage, and/or area of such a VCO, in accordance with certain aspects of the present disclosure.

[0032] FIG. 2 shows a block diagram of access point 110 and two user terminals 120m and 120x in wireless system 100. Access point 110 is equipped with Nap antennas 224a through 224ap. User terminal 120m is equipped with Nut.m antennas 252ma through 252mu, and user terminal 120x is equipped with Nut.x antennas 252xa through 252xu. Access point 110 is a transmitting entity for the downlink and a receiving entity for the uplink. Each user terminal 120 is a transmitting entity for the uplink and a receiving entity for the downlink. As used herein, a "transmitting entity" is an independently operated apparatus or device capable of transmitting data via a frequency channel, and a "receiving entity" is an independently operated apparatus or device capable of receiving data via a frequency channel. In the following description, the subscript "dn" denotes the downlink, the subscript "up" denotes the uplink, N _U p user terminals are selected for simultaneous transmission on the uplink, Ndn user terminals are selected for simultaneous transmission on the downlink, N _U p may or may not be equal to Ndn, and N _U p and Ndn may be static values or can change for each scheduling interval. Beam-steering or some other spatial processing technique may be used at the access point and user terminal.

[0033] On the uplink, at each user terminal 120 selected for uplink transmission, a TX data processor 288 receives traffic data from a data source 286 and control data from a controller 280. TX data processor 288 processes (e.g., encodes, interleaves, and modulates) the traffic data {d _up } for the user terminal based on the coding and modulation schemes associated with the rate selected for the user terminal and provides a data symbol stream !.s _n/) Jfor one of the N _u t,m antennas. A transceiver front-end (TX/RX) 254 (also known as a radio frequency front-end (RFFE)) receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) a respective symbol stream to generate an uplink signal. The transceiver front-end 254 may also route the uplink signal to one of the Nut,m antennas for transmit diversity via an RF switch, for example. The controller 280 may control the routing within the transceiver front-end 254. Memory 282 may store data and program codes for the user terminal 120 and may interface with the controller 280.

[0034] A number N _up of user terminals 120 may be scheduled for simultaneous transmission on the uplink. Each of these user terminals transmits its set of processed symbol streams on the uplink to the access point.

[0035] At access point 110, N _ap antennas 224a through 224ap receive the uplink signals from all Nup user terminals transmitting on the uplink. For receive diversity, a transceiver front-end 222 may select signals received from one of the antennas 224 for processing. The signals received from multiple antennas 224 may be combined for enhanced receive diversity. The access point’s transceiver front-end 222 also performs processing complementary to that performed by the user terminal’s transceiver frontend 254 and provides a recovered uplink data symbol stream. The recovered uplink data symbol stream is an estimate of a data symbol stream {s _U p} transmitted by a user terminal. An RX data processor 242 processes (e.g., demodulates, deinterleaves, and decodes) the recovered uplink data symbol stream in accordance with the rate used for that stream to obtain decoded data. The decoded data for each user terminal may be provided to a data sink 244 for storage and/or a controller 230 for further processing.

[0036] The transceiver front-end (TX/RX) 222 of access point 110 and/or transceiver front-end 254 of user terminal 120 may include one or more frequency synthesizers to generate oscillating signals used for signal transmission and/or reception. At least one of the frequency synthesizers may include a VCO with common-mode inductors, where the VCO implements techniques for reducing phase noise, ripple voltage, and/or area, in accordance with certain aspects of the present disclosure.

[0037] On the downlink, at access point 110, a TX data processor 210 receives traffic data from a data source 208 for Ndn user terminals scheduled for downlink transmission, control data from a controller 230 and possibly other data from a scheduler 234. The various types of data may be sent on different transport channels. TX data processor 210 processes (e.g., encodes, interleaves, and modulates) the traffic data for each user terminal based on the rate selected for that user terminal. TX data processor 210 may provide a downlink data symbol stream for one of more of the Ndn user terminals to be transmitted from one of the Nap antennas. The transceiver frontend 222 receives and processes (e.g., converts to analog, amplifies, filters, and frequency upconverts) the symbol stream to generate a downlink signal. The transceiver front-end 222 may also route the downlink signal to one or more of the Nap antennas 224 for transmit diversity via an RF switch, for example. The controller 230 may control the routing within the transceiver front-end 222. Memory 232 may store data and program codes for the access point 110 and may interface with the controller 230.

[0038] At each user terminal 120, Nut.m antennas 252 receive the downlink signals from access point 110. For receive diversity at the user terminal 120, the transceiver front-end 254 may select signals received from one of the antennas 252 for processing. The signals received from multiple antennas 252 may be combined for enhanced receive diversity. The user terminal’s transceiver front-end 254 also performs processing complementary to that performed by the access point’s transceiver front-end 222 and provides a recovered downlink data symbol stream. An RX data processor 270 processes (e.g., demodulates, deinterleaves, and decodes) the recovered downlink data symbol stream to obtain decoded data for the user terminal.

[0039] Those skilled in the art will recognize the techniques described herein may be generally applied in systems utilizing any type of multiple access schemes, such as TDMA, SDMA, Orthogonal Frequency Division Multiple Access (OFDMA), CDMA, SC-FDMA, TD-SCDMA, and combinations thereof.

[0040] FIG. 3 is a block diagram of an example transceiver circuit 300, such as transceiver front-ends 222, 254 in FIG. 2, in which aspects of the present disclosure may be practiced. The transceiver circuit 300 includes at least one transmit (TX) path 302 (also known as a “transmit chain”) for transmitting signals via one or more antennas and at least one receive (RX) path 304 (also known as a “receive chain”) for receiving signals via the antennas. When the TX path 302 and the RX path 304 share an antenna 303, the paths may be connected with the antenna via an interface 306, which may include any of various suitable radio frequency (RF) devices, such as a duplexer, a switch, a diplexer, a multiplexer, and the like.

[0041] Receiving in-phase (I) or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 308, the TX path 302 may include a baseband filter (BBF) 310, a mixer 312, a driver amplifier (DA) 314, and a power amplifier (PA) 316. The BBF 310, the mixer 312, and the DA 314 may be included in one or more radio frequency integrated circuits (RFICs). The PA 316 may be external to the RFIC(s) for some implementations.

[0042] The BBF 310 filters the baseband signals received from the DAC 308, and the mixer 312 mixes the filtered baseband signals with a transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., upconvert from baseband to RF). This frequency-conversion process produces the sum and difference frequencies between the LO frequency and the frequencies of the baseband signal of interest. The sum and difference frequencies are referred to as the “beat frequencies.” The beat frequencies are typically in the RF range, such that the signals output by the mixer 312 are typically RF signals, which are amplified by the DA 314 and by the PA 316 before transmission by the antenna 303. While one mixer 312 is illustrated, several mixers may be used to upconvert the filtered baseband signals to one or more intermediate frequencies and to thereafter upconvert the intermediate frequency (IF) signals to a frequency for transmission.

[0043] The RX path 304 includes a low noise amplifier (LNA) 322, a mixer 324, and a baseband filter (BBF) 326. The LNA 322, the mixer 324, and the BBF 326 may be included in one or more RFICs, which may or may not be the same RFIC(s) that include the TX path components. RF signals received via the antenna 303 may be amplified by the LNA 322, and the mixer 324 mixes the amplified RF signals with a receive local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (i.e., downconvert). The baseband signals output by the mixer 324 may be filtered by the BBF 326 before being converted by an analog-to-digital converter (ADC) 328 to digital I or Q signals for digital signal processing.

[0044] Certain transceivers may employ frequency synthesizers with a voltage- controlled oscillator (VCO) to generate a stable, tunable LO with a particular tuning range. Thus, the transmit LO may be produced by a TX frequency synthesizer 318, which may be buffered or amplified by amplifier 320 before being mixed with the baseband signals in the mixer 312. Similarly, the receive LO may be produced by an RX frequency synthesizer 330, which may be buffered or amplified by amplifier 332 before being mixed with the RF signals in the mixer 324.

[0045] The TX frequency synthesizer 318 and/or the RX frequency synthesizer 330 may comprise a VCO (with one or more common-mode inductors) that implements techniques for reducing phase noise, ripple voltage, and/or area, in accordance with certain aspects of the present disclosure.

Example Voltage-Controlled Oscillators

[0046] Modem communication systems may rely on low phase noise to obtain high signal-to-noise ratio (SNR) in both receive and transmit paths (e.g., RX and TX paths 304, 302). Phase noise is the frequency-domain representation of random fluctuations in the phase of a waveform, such as the oscillating signal produced by a VCO. Whereas an ideal oscillator would generate a pure sine wave, real oscillators have phase- modulated noise components that spread the power of the oscillating signal to adjacent frequencies, resulting in noise sidebands. Oscillator phase noise may include low frequency flicker noise and white noise. Flicker noise is a type of electronic noise having a 1/f power density spectrum, and although flicker noise appears as a low- frequency phenomenon, this low-frequency noise can be upconverted to frequencies close to the carrier frequency, which results in oscillator phase noise. What is more, the flicker noise (and hence, the phase noise) may increase as complementary metal-oxide- semiconductor (CMOS) processes scale.

[0047] FIG. 4 is a schematic diagram of an example voltage-controlled oscillator (VCO) 404. The VCO 404 may receive power from a power supply 402 with a power supply voltage (e.g., Vdd) referenced to a reference potential node (e.g., electrical ground). The VCO 404 may have differential output nodes 406 and 408 for outputting the oscillating signal when power is supplied to the VCO. As illustrated, the VCO 404 includes a resonant circuit (also referred to as an inductor-capacitor (LC) circuit, a tank circuit, or a tuned circuit). The VCO 404 also includes a pair of cross-coupled n-type transistors Ml and M2 that form an n-type active negative transconductance (-gm) circuit. Additionally, the VCO 404 includes a pair of cross-coupled p-type transistors M3 and M4 that form a p-type active negative transconductance circuit. The crosscoupled transistors serve to cancel out the loss (due to parasitics) of the resonant circuit and, thus, to sustain the oscillating mechanism of the VCO 404.

[0048] The resonant circuit may include a center-tapped inductor LI (which may alternatively be implemented as two or more series inductors) and a capacitor network (e.g., comprising capacitors C1-C4) designed to oscillate in a certain resonant frequency range. The inductor LI may also be referred to as a “main LC tank inductor.” The inductor LI and/or one or more capacitors (or varactors) in the capacitor network may be variable to adjust the VCO frequency within a tuning range. For certain aspects, the resonant circuit may include one or more switches (e.g., represented by switch SI in FIG. 4) used to select different combinations of capacitors in the capacitor network.

[0049] The VCO 404 also includes two common-mode (CM) inductors L2 and L3. The CM inductor L2 may be a positive-side (p-side) inductor, and the CM inductor L3 may be a negative-side (n-side) inductor. The CM inductors L2 and L3 are coupled to the sources of the cross-coupled transistors (also referred to as “virtual nodes” for the CM inductors) and provide second-order harmonic high impedance for VCO phase noise reduction. In other words, the CM inductors L2 and L3 mitigate the problem of VCO phase noise.

[0050] FIG. 5A is a layout diagram of an example topology 500A for a VCO with CM inductors 504 and 506. As illustrated, the CM inductors 504 and 506 (which may correspond to the CM inductors L3 and L2, respectively, in FIG. 4) are located outside of a coil of a main LC tank inductor 502 (which may correspond to the main LC tank inductor LI in FIG. 4).

[0051] Additionally, as illustrated, the CM inductors 504 and 506 are located adjacent one another, with the CM inductor 504 centered toward a right side of the main LC tank inductor 502, and the CM inductor 506 centered toward a left side of the main LC tank inductor 502. Said differently, each one of the CM inductors 504 and 506 is asymmetrical with respect to an axis of symmetry 510 (e.g., a centerline) of the main LC tank inductor 502. This may cause magnetic coupling between the CM inductors 504 and 506 and the main LC tank inductor 502. As a result, the corresponding virtual nodes between each of the CM inductors 504 and 506 and the main LC tank inductor 502 will have small magnetically induced ripple voltage, which limits the output swing of the VCO and causes increased phase noise.

[0052] Accordingly, a VCO topology that resolves the unbalanced coupling between the CM inductors and the main LC tank inductor is desirable to reduce the phase noise and ripple voltage of such VCOs.

[0053] Certain aspects of the present disclosure provide layout topologies with CM inductors disposed within a coil of the main LC tank inductor of the VCO, such that the CM inductors are each symmetrical with respect to at least one axis of symmetry of the main LC tank inductor. This symmetry reduces phase noise and ripple voltage in the VCO by canceling the fundamental frequency signal coupling. Additionally, placing the CM inductors within a coil of the main LC tank inductor reduces the area that the VCO would occupy in an integrated circuit (IC). Certain aspects of the present disclosure may be combined in an effort to reduce the phase noise, ripple voltage, and/or area of VCOs.

[0054] FIG. 5B is a layout diagram of an example topology 500B for VCOs with CM inductors 504 and 506, in accordance with certain aspects of the present disclosure. As illustrated, the CM inductors 504 and 506 are located within a coil of a main LC tank inductor 502. Additionally, as explained below, the CM inductors 504 and 506 have a topology with increased symmetry relative to the main LC tank inductor 502 (e.g., with respect to axis 510 and/or axis 512, where axis 512 may be perpendicular to axis 510 and also forms an axis of symmetry for the main LC tank inductor 502). The topology of the CM inductors 504 and 506 may be similar to the shape of two intertwined figure eights.

[0055] In FIGs. 5A and 5B, each of the axes 510 and 512 is an approximated axis of symmetry for the inductors 502, 504, and/or 506. It is noted that in the context of discussing symmetry of the inductors 502, 504, and 506 in the present disclosure, the width of the coil traces and the fact that ends of the coils do not touch to complete a loop are to be ignored, and the reader should consider the general shape of the inductor coil for determining an axis of symmetry as described herein.

[0056] FIGs. 6A, 6B, and 6C illustrate example conceptual layout diagrams of common-mode inductors, with arrows showing directions of electron flow (opposite to directions of current flow), in accordance with certain aspects of the present disclosure. FIG. 6A illustrates a topology 600 in which an n-side CM inductor 602 and a p-side CM inductor 604 are placed side-by-side, each CM inductor being disposed as an individual coil. The labels “vdd” and “tailp” represent the power rail terminal (and associated via 609) and the cross-coupled transistor terminal (and associated via 608), respectively, of the p-side CM inductor 604. The labels “gnd” and “tailn” represent the ground terminal (and associated via 606) and the cross-coupled transistor terminal (and associated via 607), respectively, of the n-side CM inductor 602. As illustrated, the n-side CM inductor 602 may have a coil (e.g., a spiral) configured to have an electron flow with a counterclockwise orientation (and a current flow with a clockwise direction), and the p- side CM inductor 604 may have a coil configured to have an electron flow with a clockwise orientation (and a current flow with a counterclockwise direction). For other aspects, the n-side CM inductor 602 may have a coil configured to have an electron flow with a clockwise orientation (and a current flow with a counterclockwise direction), while the p-side CM inductor may have a coil configured to have an electron flow with a counterclockwise orientation (and a current flow with a clockwise direction).

[0057] FIG. 6B illustrates a topology 610 in which the coils of the p-side CM inductor 604 and the n-side CM inductor 602 are routed side by side in parallel with each other such that the CM inductors 602 and 604 resemble a figure-eight shape. In this topology, the two coils of the p-side and n-side inductors may be routed on the same layer and may not overlap within this layer, Furthermore, the topology 610 may have reduced mutual inductance (M) compared to the topology 600, which may contribute to reduced phase noise.

[0058] As illustrated in FIG. 6B, the n-side CM inductor 602 and the p-side CM inductor 604 may each have a first coil (e.g., on the left-hand side of topology 610) configured to have an electron flow with a counterclockwise orientation (and a current flow with a clockwise direction) from a first terminal (which may be coupled to a via in the layout) to a middle portion (e.g., a midpoint) of the figure-eight shape, and a second coil (e.g., on the right-hand side of topology 610) configured to have an electron flow with a clockwise orientation (and a current flow with a counterclockwise direction) from the middle portion (e.g., the midpoint) of the figure-eight shape to a second terminal (which may be coupled to another via). For example, the trace forming the n- side CM inductor 602 may be routed in a counterclockwise fashion from the gnd terminal to the midpoint of this inductor, and may be routed in a clockwise fashion from the midpoint to the tailn terminal, as shown. With this topology 610, the coil of the n- side CM inductor 602 on the left-hand side of FIG. 6B is smaller than the coil of the n- side CM inductor 602 on the right-hand side, and vice versa for the coils of the p-side CM inductor 604. In other words, the coils on the right- and left-hand sides of the topology 610 for a given CM inductor are not the same size.

[0059] FIG. 6C illustrates a topology 620 in which the coils of the p-side CM inductor 604 and the n-side CM inductor 602 are routed side by side in parallel with each other, for the most part, such that the CM inductors 602 and 604 resemble a figureeight shape. The topology 620 illustrated in FIG. 6C is similar to the topology 610 illustrated in FIG. 6B, the only difference being that the traces forming the n-side CM inductor 602 and the p-side CM inductor 604 cross over each other at a point along the outermost portion of each of the first and second coils.

[0060] This crossover in FIG. 6C results in a slightly more symmetrical topology compared to that in FIG. 6B. With this topology 620, the coil of the n-side CM inductor 602 on the left-hand side of FIG. 6C has substantially the same size as (and is basically a mirror image of) the coil of the n-side CM inductor 602 on the right-hand side, and vice versa for the coils of the p-side CM inductor 604. In other words, the coils on the right- and left-hand sides of the topology 610 for a given CM inductor are basically the same size and symmetrical.

Example Operations

[0061] FIG. 7 is a flow diagram of operations 700 for fabricating a voltage- controlled oscillator (VCO) circuit (e.g., VCO 404), in accordance with certain aspects of the present disclosure. The operations 700 may be performed by a semiconductor processing facility (e.g., a fab house).

[0062] The operations 700 may begin, at block 702, with the processing facility forming a resonant circuit (e.g., an LC tank circuit) having a main inductor (e.g., inductor LI). At block 704, the processing facility may form a p-type active negative transconductance circuit (e.g., cross-coupled p-type transistors M3 and M4) coupled to the resonant circuit. At block 706, the processing facility may form a p-side common-mode inductor (e.g., inductor L2 or CM inductor 506 or 604) coupled between the p-type active negative transconductance circuit and a first voltage rail (e.g., Vdd). The processing facility may form an n-type active negative transconductance circuit (e.g., cross-coupled n-type transistors Ml and M2) coupled to the resonant circuit at block 708. At block 710, the processing facility may form an n-side common-mode inductor (e.g., inductor L3 or CM inductor 504 or 602) coupled between the n-type active negative transconductance circuit and a second voltage rail (e.g., electrical ground).

[0063] According to certain aspects, at least one of: forming the p-side commonmode inductor at block 706 includes forming the p-side common-mode inductor in a coil of the main inductor; or forming the n-side common-mode inductor at block 710 includes forming the n-side common-mode inductor in the coil of the main inductor. For certain aspects, at least one of: forming the p-side common-mode inductor at block 706 involves forming the p-side common-mode inductor such that the p-side commonmode inductor is symmetrical with respect to a first axis (e.g., axis 510) of the coil of the main inductor; or forming the n-side common-mode inductor at block 710 involves forming the n-side common-mode inductor such that the n-side common-mode inductor is symmetrical with respect to the first axis of the coil of the main inductor. In this case, at least one of: forming the p-side common-mode inductor at block 706 includes forming the p-side common-mode inductor such that the p-side common-mode inductor is symmetrical with respect to a second axis (e.g., axis 512) of the coil of the main inductor; or forming the n-side common-mode inductor at block 710 includes forming the n-side common-mode inductor such that the n-side common-mode inductor is symmetrical with respect to the second axis of the coil of the main inductor. In this case, the second axis may be perpendicular to the first axis. For certain aspects, forming the p-side common-mode inductor at block 706 and forming the n-side common-mode inductor at block 710 involve forming a coil of the p-side common-mode inductor and a coil of the n-side common-mode inductor on a same layer of a physical layout. In this case, forming the resonant circuit at block 702 may include forming a coil of the main inductor on the same layer of the physical layout as the coil of the p-side common-mode inductor and the coil of the n-side common-mode inductor. [0064] According to certain aspects, at least one of the p-side common-mode inductor or the n-side common-mode inductor has a figure-eight shape with a first coil and a second coil. In this case, the operations 700 may further include forming a first via (e.g., via 606 or via 608) at a first end (e.g., terminal gnd or terminal tailp) of the first coil in the figure-eight shape and forming a second via (e.g., via 607 or via 609) at a second end (e.g., terminal tailn or terminal vdd) of a second coil in the figure-eight shape.

[0065] According to certain aspects, at least one of the p-side common-mode inductor or the n-side common-mode inductor has a figure-eight shape with a first coil and a second coil. In this case, the operations 700 may further involve forming a first via, wherein the first coil is configured to have an electron flow with a counterclockwise orientation from the first via to a midpoint of the figure-eight shape; and forming a second via, wherein the second coil configured to have the electron flow with a clockwise orientation from the midpoint of the figure-eight shape to the second via.

[0066] According to certain aspects, forming the p-side common-mode inductor at block 706 involves forming a first trace (e.g., the trace forming the p-side CM inductor 604) for the p-side common-mode inductor adjacent to a second trace (e.g., the trace forming the n-side CM inductor 602) for the n-side common-mode inductor. For certain aspects, the operations 700 may further include forming a first via (e.g., via 608) and forming a second via (e.g., via 609). In this case, forming the p-side common-mode inductor at block 706 may involve forming the first trace into: a first coil (e.g., lefthand side of the p-side CM inductor 604) configured to have a first electron flow with a counterclockwise orientation from the first via to a midpoint of the p-side commonmode inductor; and a second coil (e.g., right-hand side of the p-side CM inductor 604) configured to have the first electron flow with a clockwise orientation from the midpoint of the p-side common-mode inductor to the second via. For certain aspects, the operations 700 may further include forming a third via (e.g., via 606) and forming a fourth via (e.g., via 607). In this case, forming the n-side common-mode inductor at block 710 may involve forming the second trace into: a third coil (e.g., left-hand side of the n-side CM inductor 602) configured to have a second electron flow with a counterclockwise orientation from the third via to a midpoint of the n-side commonmode inductor; and a fourth coil (e.g., right-hand side of the n-side CM inductor 602) configured to have the second electron flow with a clockwise orientation from the midpoint of the n-side common-mode inductor to the fourth via. For certain aspects, the first coil is disposed inside the third coil, and/or the second coil is disposed outside the fourth coil. The first trace and the second trace may be formed on a same layer of a physical layout in certain aspects. For certain aspects, the first via is disposed adjacent to the third via, and/or the second via is disposed adjacent to the fourth via.

[0067] FIG. 8 is a flow diagram of operations 800 for oscillation, in accordance with certain aspects of the present disclosure. The operations 800 may be performed by an apparatus (e.g., a frequency synthesizer or a transceiver circuit) comprising a VCO (e.g., VCO 404) and a power supply (e.g., power supply 402).

[0068] The operations 800 may begin, at block 802, with the power supply providing power to the VCO circuit. The VCO circuit generally includes a resonant circuit having a main inductor, a p-type active negative transconductance circuit coupled to the resonant circuit, a p-side common-mode inductor coupled between the p- type active negative transconductance circuit and a first voltage rail, an n-type active negative transconductance circuit coupled to the resonant circuit, and an n-side common-mode inductor coupled between the n-type active negative transconductance circuit and a second voltage rail. At block 804, the powered VCO circuit generates an oscillating signal across the resonant circuit. For certain aspects, the operations 800 may further involve tuning the frequency of the oscillating signal.

Example Aspects

[0069] In addition to the various aspects described above, specific combinations of aspects are within the scope of the disclosure, some of which are detailed below:

[0070] Aspect 1 : A voltage-controlled oscillator (VCO) circuit comprising: a resonant circuit having a main inductor; a p-type active negative transconductance circuit coupled to the resonant circuit; a p-side common-mode inductor coupled between the p-type active negative transconductance circuit and a first voltage rail; an n-type active negative transconductance circuit coupled to the resonant circuit; and an n- side common-mode inductor coupled between the n-type active negative transconductance circuit and a second voltage rail. [0071] Aspect 2: The VCO circuit of Aspect 1, wherein at least one of the p-side common-mode inductor or the n-side common-mode inductor is disposed in a coil of the main inductor.

[0072] Aspect 3: The VCO circuit of Aspect 2, wherein the at least one of the p- side common-mode inductor or the n-side common-mode inductor is symmetrical with respect to a first axis of the coil of the main inductor.

[0073] Aspect 4: The VCO circuit of Aspect 3, wherein the at least one of the p- side common-mode inductor or the n-side common-mode inductor is symmetrical with respect to a second axis of the coil of the main inductor, the second axis being perpendicular to the first axis.

[0074] Aspect 5: The VCO circuit of any of the preceding Aspects, wherein a coil of the p-side common-mode inductor and a coil of the n-side common-mode inductor are disposed on a same layer of a physical layout.

[0075] Aspect 6: The VCO circuit of Aspect 5, wherein a coil of the main inductor is disposed on the same layer of the physical layout as the coil of the p-side commonmode inductor and the coil of the n-side common-mode inductor.

[0076] Aspect 7: The VCO circuit of any of the preceding Aspects, wherein at least one of the p-side common-mode inductor or the n-side common-mode inductor has a figure-eight shape.

[0077] Aspect 8: The VCO circuit of Aspect 7, wherein the at least one of the p- side common-mode inductor or the n-side common-mode inductor has a first via at a first end of a first coil in the figure-eight shape and has a second via at a second end of a second coil in the figure-eight shape.

[0078] Aspect 9: The VCO circuit of Aspect 7, wherein the at least one of the p- side common-mode inductor or the n-side common-mode inductor has a first coil configured to have an electron flow with a counterclockwise orientation from a first via to a midpoint of the figure-eight shape and has a second coil configured to have the electron flow with a clockwise orientation from the midpoint of the figure-eight shape to a second via. [0079] Aspect 10: The VCO circuit of any of the preceding Aspects, wherein a first trace for the p-side common-mode inductor is routed adjacent to a second trace for the n-side common-mode inductor.

[0080] Aspect 11 : The VCO circuit of Aspect 10, wherein the first trace is routed to form: a first coil configured to have a first electron flow with a counterclockwise orientation from a first via to a midpoint of the p-side common-mode inductor; and a second coil configured to have the first electron flow with a clockwise orientation from the midpoint of the p-side common-mode inductor to a second via.

[0081] Aspect 12: The VCO circuit of Aspect 11, wherein the second trace is routed to form: a third coil configured to have a second electron flow with a counterclockwise orientation from a third via to a midpoint of the n-side common-mode inductor; and a fourth coil configured to have the second electron flow with a clockwise orientation from the midpoint of the n-side common-mode inductor to a fourth via.

[0082] Aspect 13: The VCO circuit of Aspect 12, wherein the first coil is disposed inside the third coil and wherein the second coil is disposed outside the fourth coil.

[0083] Aspect 14: The VCO circuit of Aspect 12, wherein the first trace for the p- side common-mode inductor and the second trace for the n-side common-mode inductor cross over each other such that the first coil is partially disposed inside the third coil and the second coil is partially disposed inside the fourth coil.

[0084] Aspect 15: The VCO circuit of Aspect 12 or 13, wherein the first trace and the second trace are routed on a same layer of a physical layout.

[0085] Aspect 16: The VCO circuit of any of Aspects 12 to 15, wherein the first via is disposed adjacent to the third via and wherein the second via is disposed adjacent to the fourth via.

[0086] Aspect 17: A method of fabricating a VCO circuit, the method comprising: forming a resonant circuit having a main inductor; forming a p-type active negative transconductance circuit coupled to the resonant circuit; forming a p-side commonmode inductor coupled between the p-type active negative transconductance circuit and a first voltage rail; forming an n-type active negative transconductance circuit coupled to the resonant circuit; and forming an n-side common-mode inductor coupled between the n-type active negative transconductance circuit and a second voltage rail.

[0087] Aspect 18: The method of Aspect 17, wherein at least one of: forming the p-side common-mode inductor comprises forming the p-side common-mode inductor in a coil of the main inductor; or forming the n-side common-mode inductor comprises forming the n-side common-mode inductor in the coil of the main inductor.

[0088] Aspect 19: The method of Aspect 18, wherein at least one of: forming the p-side common-mode inductor comprises forming the p-side common-mode inductor such that the p-side common-mode inductor is symmetrical with respect to a first axis of the coil of the main inductor; or forming the n-side common-mode inductor comprises forming the n-side common-mode inductor such that the n-side common-mode inductor is symmetrical with respect to the first axis of the coil of the main inductor.

[0089] Aspect 20: The method of Aspect 19, wherein at least one of: forming the p-side common-mode inductor comprises forming the p-side common-mode inductor such that the p-side common-mode inductor is symmetrical with respect to a second axis of the coil of the main inductor, the second axis being perpendicular to the first axis; or forming the n-side common-mode inductor comprises forming the n-side common-mode inductor such that the n-side common-mode inductor is symmetrical with respect to the second axis of the coil of the main inductor.

[0090] Aspect 21 : The method of any of Aspects 17 to 20, wherein forming the p- side common-mode inductor and forming the n-side common-mode inductor comprise forming a coil of the p-side common-mode inductor and a coil of the n-side commonmode inductor on a same layer of a physical layout.

[0091] Aspect 22: The method of Aspect 21, wherein forming the resonant circuit comprises forming a coil of the main inductor on the same layer of the physical layout as the coil of the p-side common-mode inductor and the coil of the n-side commonmode inductor.

[0092] Aspect 23: The method of any of Aspects 17 to 22, wherein at least one of the p-side common-mode inductor or the n-side common-mode inductor has a figureeight shape with a first coil and a second coil and wherein the method further comprises: forming a first via at a first end of the first coil in the figure-eight shape; and forming a second via at a second end of the second coil in the figure-eight shape.

[0093] Aspect 24: The method of any of Aspects 17 to 22, wherein at least one of the p-side common-mode inductor or the n-side common-mode inductor has a figureeight shape with a first coil and a second coil and wherein the method further comprises: forming a first via, wherein the first coil is configured to have an electron flow with a counterclockwise orientation from the first via to a midpoint of the figure-eight shape; and forming a second via, wherein the second coil is configured to have the electron flow with a clockwise orientation from the midpoint of the figure-eight shape to the second via.

[0094] Aspect 25: The method of any of Aspects 17 to 24, wherein forming the p- side common-mode inductor comprises forming a first trace for the p-side commonmode inductor adjacent to a second trace for the n-side common-mode inductor.

[0095] Aspect 26: The method of Aspect 25, further comprising: forming a first via; and forming a second via, wherein forming the p-side common-mode inductor comprises forming the first trace into: a first coil configured to have a first electron flow with a counterclockwise orientation from the first via to a midpoint of the p-side common-mode inductor; and a second coil configured to have the first electron flow with a clockwise orientation from the midpoint of the p-side common-mode inductor to the second via.

[0096] Aspect 27: The method of Aspect 26, further comprising: forming a third via; and forming a fourth via, wherein forming the n-side common-mode inductor comprises forming the second trace into: a third coil configured to have a second electron flow with a counterclockwise orientation from the third via to a midpoint of the n-side common-mode inductor; and a fourth coil configured to have the second electron flow with a clockwise orientation from the midpoint of the n-side common-mode inductor to the fourth via.

[0097] Aspect 28: The method of Aspect 27, wherein the first coil is disposed inside the third coil and wherein the second coil is disposed outside the fourth coil. [0098] Aspect 29: The method of Aspect 27 or 28, wherein the first trace and the second trace are formed on a same layer of a physical layout.

[0099] Aspect 30: The method of any of Aspects 27 to 29, wherein the first via is disposed adjacent to the third via and wherein the second via is disposed adjacent to the fourth via.

[0100] Aspect 31 : A method of oscillation, comprising: providing power to a VCO circuit, the VCO circuit comprising: a resonant circuit having a main inductor; a p-type active negative transconductance circuit coupled to the resonant circuit; a p-side common-mode inductor coupled between the p-type active negative transconductance circuit and a first voltage rail; an n-type active negative transconductance circuit coupled to the resonant circuit; and an n-side common-mode inductor coupled between the n-type active negative transconductance circuit and a second voltage rail; and generating an oscillating signal across the resonant circuit with the powered VCO circuit.

[0101] Aspect 32: A method of oscillation comprising providing power to a VCO circuit according to any of Aspects 1 to 16 for generating an oscillating signal across the resonant circuit of the powered VCO circuit.

[0102] Aspect 33: An electronic device comprising a VCO circuit according to any of Aspects 1 to 16.

Additional Considerations

[0103] The various operations or methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to a circuit, an application specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in figures, those operations may have corresponding counterpart means-plus-function components with similar numbering.

[0104] As used herein, the term “determining” encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database, or another data structure), ascertaining, and the like. Also, “determining” may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Also, “determining” may include resolving, selecting, choosing, establishing, and the like.

[0105] As used herein, a phrase referring to “at least one of’ a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c- c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

[0106] The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

[0107] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes, and variations may be made in the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.