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Title:
PHASE SYNCHRONIZATION CIRCUIT, RF FRONT - END CIRCUIT, RADIO TRANSMISSION/RECEPTION CIRCUIT, AND MOBILE RADIO COMMUNICATION TERMINAL APPARATUS
Document Type and Number:
WIPO Patent Application WO/2017/110657
Kind Code:
A1
Abstract:
The objective of the invention is to provide a phase synchronization circuit wherein even if the frequency of an input signal becomes unstable, the frequency can be stabilized. A phase synchronization circuit 12 that corrects an error between the frequency of an output signal LSraw of an oscillator and a predetermined target frequency is characterized by comprising: an ADC 121 that performs an A/D conversion of the output signal LSraw; a reference frequency output means 123 that outputs a reference frequency signal Sref; an error frequency detection means 122a that receives the A/D converted output signal LSraw and the reference frequency signal Sref and calculates an error between the frequency of the output signal LSraw and the target frequency; a correction signal generation means 122b that generates an error correction signal LSerr on the basis of the error; a DAC 124 that performs a D/A conversion of the error correction signal LSerr; and a multiplier 125 that multiplies the output signal LSraw by the D/A converted error correction signal LSerr.

Inventors:
MORISAKA SHINICHI (JP)
Application Number:
JP2016/087454
Publication Date:
June 29, 2017
Filing Date:
December 15, 2016
Export Citation:
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Assignee:
R F ARCH CO LTD (JP)
International Classes:
H03L7/06; H03B5/30; H03B21/01; H03L7/16; H04B1/403
Foreign References:
JP2006279798A2006-10-12
JP2004241886A2004-08-26
JPH11122121A1999-04-30
JPH11122135A1999-04-30
JP2001292030A2001-10-19
JP2011147169A2011-07-28
Attorney, Agent or Firm:
SEVEN COLOR PATENT FIRM (JP)
It is a じいろ patent firm to a patent business corporation. (JP)
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