TECHNICAL FIELD The present application relates, in general, to photo-detection.

SUMMARY In one aspect, a system includes but is not limited to: a photo-detector array having a first charge well; a first charge pump operably coupled with the first charge well; and a first charge counter operably coupled with said first charge pump. In addition to the foregoing, other system aspects are described in the claims, drawings, and text forming a part of the present application.

In one aspect, a method includes but is not limited to: counting charges moved between a first charge pump and a first charge well of a photo-detector array; and calculating an overall charge-level of the first charge well in response to said counting. In addition to the foregoing, other method aspects are described in the claims, drawings, and text forming a part of the present application.

In one or more various aspects, related systems include but are not limited to circuitry and/or programming for effecting the herein-referenced method aspects; the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect the herein- referenced method aspects depending upon the design choices of the system designer.

In addition to the foregoing, various other method and/or system aspects are set forth and described in the text (e.g., claims and/or detailed description) and/or drawings of the present application.

The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and is NOT intended to be in any way limiting. Other aspects, inventive features, and advantages of the devices and/or processes described herein, as defined by the claims, will become apparent in the detailed description set forth herein.

BRIEF DESCRIPTION OF THE FIGURES Figure 1 shows a partial view illustrative of various exemplary photo-detector array device(s) and/or process(es).

The use of the same symbols in different drawings typically indicates similar or identical items.

DETAILED DESCRIPTION

The present application uses formal outline headings for clarity of presentation. However, it is to be understood that the outline headings are for presentation purposes, and that different types of subject matter may be discussed throughout the application (e.g., device(s)/stracture(s) may be described under the process(es)/operations heading(s) and/or process(es)/operations may be discussed under structure(s)/process(es) headings). Hence, the use of the formal outline headings is not intended to be in any way limiting.

/. Sensitive Photo-Detector Array Device(s) and/or Process(es)

With reference now to Figure I3 shown is a partial view illustrative of various exemplary photo-detector array device(s) and/or process(es). Accordingly, the present application first describes certain specific exemplary structures of Figure 1 ; thereafter, the present application illustrates certain specific exemplary processes. Those having ordinary skill in the art will appreciate that the specific devices and processes described herein are intended as merely illustrative of their more general counterparts.

A. Structure(s) and/or Device(s)

Photo-detector array 100 is depicted as having individual photo-detectors arranged in M x N row-column format. Photo-detector array 100 is shown indexed with notation indicative of this row and column format (e.g., the photo-detectors of row 1, column 1 ; row M, column 1 ; and row M, column N are respectively shown as indexed rlcl; rMcl; and rMcTSI). Those having skill in the art will appreciate that photo-detector array 100 is intended to be representative of substantially any suitable type of photo- detector array (e.g., charge coupled device (CCD), complimentary oxide semiconductor (CMOS), or other type photo-detector arrays) arranged in substantially any suitable architecture consistent with the teachin Jg6Us herein.

Continuing to refer to Figure I, exemplary implementations of photo-detectors rMc3 and r5c7 are illustrated in breakout views. Those skilled in the art will appreciate that photo-detectors conventionally convert impinging photons to representative charge, with such representative charge thereafter being accumulated in what may be referred to as "charge wells" or "pixel wells." Conventional aspects of such detection and conversion are not addressed herein for clarity of presentation, but those skilled in the art will recognize that there is typically a known relationship between photons impinging on a surface of a particular photo-detector (e.g., photo-detector rMc3 or r5c7) and charge accumulated in the charge or pixel well of that particular photo-detector (e.g. 8 impinging photons are known to typically generate 4 accumulated electrons).

Referring now to photo-detector rMc3, charge well 102 is shown as coupled to an output of charge-in counter 106 (e.g., a coulomb counter or an electron charge counter). An input of charge- in counter 106 is depicted as coupled to an output of active charge source 104 (e.g., an electron source). A control signal input of active charge source 104 is illustrated as coupled with a control signal output of well-charge-level controller 108.

Charge well 102 is further shown as coupled to an input of charge-out counter 110 (e.g., a coulomb counter or an electron charge counter). An output of charge-out counter 110 is depicted as coupled to an input of active charge sink 112 (e.g., an electron sink). A control signal input of active charge sink 112 is illustrated as coupled with a control signal output of well-charge-level controller 108.

Well-charge-level controller 108 is shown as coupled to an output of well-charge- level detector 114. Well-charge-level detector 114 is depicted as coupled to charge well 102 Well-charge-level controller 108 is further shown as having a photo-detector target charge level control signal.

Well-charge-level detector 114 is further illustrated as having an output coupled to charge calculation unit 116. hi one exemplary implementation, well-charge-level detector 114 includes a processor configured by a program; in another exemplary implementation, well-charge-level detector 114 includes circuitry relatively constantly configured to execute logic.

Imaging circuitry 118 is shown receiving input from charge calculation unit 116. In one exemplary implementation, imaging circuitry 118 is conventional and usually receives input similar to that normally output by an individual photo detector or a photo detector array (e.g., for backwards compatibility with existing technologies). In another exemplary implementation, imaging circuitry 118 is specially constructed to interface with logic of charge calculation unit 116.

With reference now to photo-detector r5c7, shown connected in like fashion as for photo-detector rMc3 are charge-in counter 106, active charge source 104, well- charge-level controller 108, charge-out counter 110, active charge sink 112, and well- charge-level detector 114. Those having skill in the art will appreciate that exhaustive recitation of photo-detector r5c7's component connections is not necessary in light of the herein-described connections of like components of photo-detector rMc3.

Certain of the described structures of Figure 1 may serve as environments wherein certain processes can be illustrated, as set forth herein.

B. Operation(s) and/or Process(es)

Those having ordinary skill in the art will appreciate that there will typically be a predefined charge level for charge well 102 of photo-detector rMc3 such that photo- detector rMc3 will display near-optimal responsiveness to impinging photons, hi one exemplary process, well-charge-level controller 108 more or less continuously adjusts the control signal inputs of active charge source 104 and/or active charge sink 112 such that detected accumulated charge level in charge well 102 stays at or around the predefined charge level where responsiveness is near-optimal. In one exemplary implementation, well-charge-level controller 108 entails aprocessor configured to control either or both active charge source 104 and active charge sink 112 utilizing at least one of a proportional, integral, and derivative control scheme. Other exemplary implementations are described elsewhere herein.

Well-charge-level controller 108 typically gains knowledge of the detected accumulated charge level of charge well 102 from an output of well-charge-level detector 114. Well-charge-level detector 114 relatively continuously senses the level of charge in charge well 102 and generates the output indicative of that charge in a form appropriate to well-charge-level controller 108. In addition, well-charge-level detector 114 relatively continuously senses the level of charge in charge well 102 and generates an output indicative of the level of charge in charge well 102 in a form appropriate to charge calculation unit 116.

Charge calculation unit 116 receives the signal indicative of the level of charge in charge well 102 from the output of well-charge-level detector 114. hi addition, charge calculation unit 116 receives input from and controls either or both charge-in counter 106 and charge-out counter 110. Charge-in counter 106 counts charge sourced into charge well 102 by active charge source 104 over some interval of time under the control of charge calculation unit 116. Charge out counter 110 counts charge sunk out of charge well 102 by active charge sink 112 over some interval of time under the control of charge calculation unit 116. In one exemplary implementation, charge calculation unit 116 entails a processor configured to control either or both charge-in counter 106 and charge- out counter 110. Other exemplary implementations are described elsewhere herein.

For any particular interval of time, charge calculation unit 116 uses (a) knowledge of the level of charge in charge well 102 at the beginning and/or end of the time interval (obtained from well-charge-level detector 114), (b) knowledge of charge sourced to charge well 102 during the time interval (obtained from charge-in counter 106), and/or (c) knowledge of charge sunk from charge well 102 during the time interval (obtained from charge-out counter 110) to calculate an aggregate photo-induced charge received by charge well 102 during the particular time interval. Thereafter, charge calculation unit 116 uses the calculated aggregate photo-induced charge and a recalled known relationship between charge received by charge well 102 and photons impinging on the surface of photo-detector rMc3 to calculate a likely number of impinging photons responsible for the calculated aggregate photo-induced charge (which can serve as an indication of local intensity at that photo-detector), Thereafter, charge calculation unit 116 generates and transmits to imaging circuitry 118 a signal indicative of the calculated likely number of photons impinging within the reference time interval, where the signal is in a form appropriate to imaging circuitry 118 (e.g., a defined amount of charge in implementations where imaging circuitry 118 is implemented using conventional imaging circuitry that ordinarily receives packets of charge, or a logical signal in implementations where imaging circuitry 118 is implemented in computation logic circuitry).. Thereafter, imaging circuitry 118 processes the information indicative of the number of photons impinging on the rMc3 photo-detector over the reference time interval. Those having skill in the art will appreciate that the process just described in the context of photo-detector rMc3 can also be implemented in the context of any other like photo-detectors present, such as photo-detector r5c7.

C. Benefit(s), Variation(s), and/or Implementation(s)

As shown herein, the inventors have devised a number of technologies, examples of which are illustrated in the text and drawings of the present application. In one illustrated technology, the aggregate charge contained within a charge well of a photo- detector array is manipulated such that the aggregate charge in the charge well is more or less maintained within defined bounds (e.g., at or around a charge level where the photo- detector associated with the charge well has good sensitivity). In various implementations, the manipulation of the aggregate charge is achieved by actively sourcmg/sinking charges to/from the charge well. In various implementations, counts of the sourced/sunk charges are used to extrapolate an aggregate charge of the charge well. A benefit of some of the herein described implementations is that, since aggregate charge in a charge well of a photo-detector array is more or less maintained within defined bounds, the dynamic range of the charge well of the photo-detector array can be increased well beyond that possible in the absence of the maintenance of such aggregate charge.

Those having skill in the art will recognize that the present application teaches modifications of the devices, structures, and/or processes within the spirit of the teaching herein. For example, in one alternate exemplary implementation of photo-detector rMc3, charge-in counter and active charge source 104 are omitted, and the charge level of charge well 102 is controlled through the active sinking of a known quantity of current. Other modifications of the subject matter herein will be appreciated by one of ordinary skill in the art in light of the teachings herein. The foregoing detailed description has set forth various embodiments of the devices and/or processes via the use of block diagrams, flowcharts, and examples. Insofar as such block diagrams, flowcharts, and examples contain one or more functions and/or operations, it will be understood by those within the art that each function and/or operation within such block diagrams, flowcharts, or examples can be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or virtually any combination thereof. In one-embodiment, the present invention may be implemented via Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), or other integrated formats. However, those skilled in the art will recognize that the embodiments disclosed herein, in whole or in part, can be equivalently implemented in standard integrated circuits, as one or more computer programs running on one or more computers (e.g., as one or more programs running on one or more computer systems), as one or more programs running on one or more processors (e.g., as one or more programs running on one or more microprocessors), as firmware running on one or more processors, or as virtually any combination thereof, and that designing the circuitry and/or writing the code for the software and or firmware would be well within the skill of one skilled in the art in light of this disclosure, ha addition, those skilled in the art will appreciate that the mechanisms of the present invention are capable of being distributed as a program product in a variety of forms, and that an illustrative embodiment of the present invention applies equally regardless of the particular type of signal bearing media used to actually carry out the distribution. Examples of a signal bearing media include, but are not limited to, the following: recordable type media such as floppy disks, hard disk drives, CD ROMs, digital tape, and computer memory; and transmission type media such as digital and analog communication links using TDM or IP based communication links (e.g., packet links).

In a general sense, those skilled in the art will recognize that the various embodiments described herein which can be implemented, individually and/or collectively, by various types of electro-mechanical systems having a wide range of hardware, software, firmware, or virtually any combination thereof. Consequently, as used herein electro-mechanical includes, but is not limited to, electrical circuitry operably coupled with a transducer (e.g., an actuator, a motor, a piezoelectric crystal, etc.), electrical circuitry having at least one discrete electrical circuit, electrical circuitry having at least one integrated circuit, electrical circuitry having at least one application specific integrated circuit, electrical circuitry forming a general purpose computing device configured by a computer program (e.g., a general purpose computer configured by a computer program which at least partially carries out processes and/or devices described herein, or a microprocessor configured by a computer program which at least partially carries out processes and/or devices described herein), electrical circuitry forming a memory device (e.g., any of the various forms of random access memory), electrical circuitry forming a communications device (e.g., a modem, communications switch, or optical-electrical equipment), and any non-electrical analog thereto, such as optical or other analogous devices.

Those skilled in the art will recognize that it is common within the art to describe devices and/or processes in the fashion set forth herein, and thereafter use standard engineering practices to integrate such described devices and/or processes into image processing systems. That is, at least a portion of the devices and/or processes described herein can be integrated into an image processing system via a reasonable amount of experimentation. Those having skill in the art will recognize that a typical image processing system generally includes one or more of a system unit housing, a video display device, a memory sub-system such as volatile or non-volatile memory, processors such as microprocessors and digital signal processors, computational entities such as operating systems, drivers, and applications programs, one or more human interaction devices, such as a touch pad or screen, control systems including feedback loops and control motors (e.g., feedback for sensing lens position and/or velocity; control motors for moving/distorting lenses to give desired image-focal properties. A typical image processing system may be implemented utilizing any suitable commercially available components, sμch as those typically found in digital still camera systems and/or digital motion camera systems. The foregoing described embodiments depict different components contained within, or connected with, different other components. It is to be understood that such depicted architectures are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or implementing components (e.g., implementing components). Likewise, any two components so associated can also be viewed as being "operably connected" or "operably coupled" to each other to achieve the desired functionality.

While particular embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that, based upon the teachings herein, changes and modifications may be made without departing from this invention and its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as are within the true spirit and scope of this invention. Furthermore, it is to be understood that the invention is solely defined by the appended claims. It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," the term "includes" should be interpreted as "includes but is not limited to," "comprise" and variations thereof, such as, "comprises" and "comprising" are to be construed in an open, inclusive sense, that is as "including, but not limited to," etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should NOT be construed to imply that the introduction of a claim recitation by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim recitation to inventions containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g., "a" and/or "an" should typically be interpreted to mean "at least one" or "one or more"); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean at least the recited number (e.g., the bare recitation of "two recitations," without other modifiers, typically means at least two recitations, or two or more recitations).