CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims the benefit of priority to U.S. Provisional

Application No. 63/176,546, entitled “PHOTON-COUNTING CMOS IMAGE SENSOR FOR TIME OF FLIGHT RANGING APPLICATIONS,” filed on April 19, 2021, which is incorporated herein by reference in its entirety.

BACKGROUND

FIELD OF THE DISCLOSURE

[0002] The present disclosure relates to image sensors, and, more particularly, to photon- counting image sensors for time-of-flight ranging applications.

DESCRIPTION OF THE RELATED ART

[0003] The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0004] CMOS image sensors (CIS) have become ubiquitous. For example, they can be used in cellular phones, medical, security cameras, etc. CMOS Quanta Image Sensors (QIS) have been developed that are sensitive to a single photon (or photoelectron) due to their low sense-node capacitance and high conversion gain. Their specialized pixel is sometimes referred to as a “jot ” Single Photon Avalanche Diodes (SPADs) have also been developed that can detect single photons. They utilize high electric fields in the semiconductor that results in carrier multiplication due to impact ionization. However, these devices have relatively large pixels that are not easily shrunk due to their need for high electric field. They are also more difficult to manufacture, have higher dark current, and dissipate more power, resulting in shorter battery life or heating of the sensor chip compared to CIS or QIS devices. [0005] For direct time-of-flight applications (DTOF) for determining distance to objects, the time it takes a photon to travel from the object to the camera is used to determine the distance to the object through the known speed of light. DTOF sensors have been implemented with SPAD pixel arrays. It is object of the invention to realize a DTOF sensor using a CIS or QIS type pixel so as to allow smaller pixel size, lower power dissipation and lower manufacturing costs. Until now, a DTOF CIS or QIS has not been reported.

SUMMARY

[0006] Aspects of the present disclosure provide a sensor. For example, the sensor can include a photon-counting pixel that does not use avalanche multiplication for gain configured to generate an output voltage change when impinged by a photon, and a binary readout circuitry coupled to the photon-counting pixel, the binary readout circuitry configured to output a first binary signal when receiving the output voltage change and a second binary signal when not receiving the output voltage change. For example, the sensor can be a single-bit quanta image sensor (QIS), a complementary metal-oxide-semiconductor (CMOS) active pixel image sensor, or a pump-gate- type photodetector-device-based image sensor that is modified to allow high speed readout. [0007] In an embodiment, the sensor can further include an amplifier coupled between the photon-counting pixel and the binary' readout, the amplifier configured to amplify the output voltage change. For example, the amplifier includes a source follower.

[0008] In an embodiment, the binary readout circuitry can include a comparator. For example, the comparator can include an inverter. In another embodiment, the binary readout circuitry can further include a switched-capacitor input circuitry coupled between the photon-counting pixel and the comparator. For example, the switched-capacitor input circuitry' can include a first storage capacitor, a first switch coupled between the photon-counting pixel and a first end of the first storage capacitor, a second storage capacitor with a first end coupled to a second end of the first storage capacitor, a second switch coupled between the photon-counting pixel and a second end of the second storage capacitor, an upper switch coupled between the first storage capacitor and the comparator, the upper switch configured to connect the first end of the first storage capacitor to a first input or a second input of the comparator, and a lower switch coupled between the second storage capacitor and the comparator, the lower switch configured to connect the other end of the second storage capacitor to the second input or the second input of the comparator.

[0009] In an embodiment, the sensor further includes one or more third storage capacitors each with a first end coupled to the first input of the comparator, and one or more third switches each coupled to a second end of a corresponding one of the third storage capacitors, the third switches configured to couple the second ends of the third storage capacitors to ground or a reference voltage. In an embodiment, the comparator can include a set of sense amplifiers (SAs) coupled to the switched-capacitor input circuitry, and a latch coupled to the set of SAs. For example, the latch can include a dynamic latch. In an embodiment, at least one of the SAs can include a five- transistor (5T) operational transconductance amplifier (OTA). In another embodiment, at least one of the SAs can include a low power charge transfer amplifier (CTA).

[0010] In an embodiment, the binary readout circuitry' can further include a flip-flop (FF) coupled to the comparator. For example, the FF can be a dynamic FF (DFF).

[0011] In an embodiment, the sensor can further include a cascode amplifier coupled between the photon-counting pixel and the binary readout circuitry, wherein the binary readout circuitry includes an inverter, and the cascode amplifier is configured to amplify the output voltage change such that the amplified output voltage change is large enough to flip the inverter.

[0012] In another embodiment, the binary readout circuitry can have an output fed back to the photon-counting pixel.

[0013] In some other embodiments, the sensor can further include an amplitude filter coupled between the photon-counting pixel and the binary readout circuitry, the amplitude filter configured to suppress noises in the output voltage change.

[0014] Aspects of the present disclosure further provide a time-resolving device for distance sensing. For example, the time-resolving device can include a light source configured to emit a first light, and an array of the sensors configured to sense a second light reflected by the first light.

[0015] The foregoing paragraphs have been provided by way of general introduction, and are not intended to limit the scope of the following claims. The described embodiments, together with further advantages, will be best understood by reference to the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0016] A more complete appreciation of the disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

[0017] FIG. 1 A shows a circuit diagram of an exemplary high-speed signal readout chain according to some embodiments of the present disclosure;

[0018] FIG. 1B is a schematic view of a jot of the readout chain according to some embodiments of the present disclosure;

[0019] FIG. 1C is a schematic view of a stacked-sensor architecture that includes a plurality of the readout chains according to some embodiments of the present disclosure; [0020] FIGs. 2A, 2B, and 2C show cross-sectional views of three different types of illustrative pixels that each incorporates a low-capacitance floating diffusion (FD) according to some embodiments of the present disclosure and a gated or gateless reset; [0021] FIG. 3 shows an exemplary comparator of the readout chain according to some embodiments of the present disclosure;

[0022] FIG. 4 shows a sensor architecture with two stacked chips or wafers according to some embodiments of the present disclosure;

[0023] FIG. 5 is an operation timing diagram of a 1-bit ADC of the readout chain according to some embodiments of the present disclosure;

[0024] FIGs. 6 A and 6B show the output voltage change of a jot and the output of the readout chain in the time domain according to some embodiments of the present disclosure;

[0025] FIG. 7A is a functional block diagram of a characterization system for testing a device according to some embodiments of the present disclosure;

[0026] FIG. 7B shows an example of the measured frames with a sampling frequency of 33MHz and frame time of 11μs according to some embodiments of the present disclosure;

[0027] FIG. 7C shows an example of a photon-counting histogram (PCH) from

FIG. 7B; [0028] FIG. 8 shows a circuit diagram of another exemplary high-speed signal readout chain according to some embodiments of the present disclosure;

[0029] FIG. 9 is a schematic diagram illustrating an event-driven QIS with feedback reset according to some embodiments of the present disclosure;

[0030] FIGs. 10A to 10C show theoretical results of an output voltage change of the jot, the output voltage change being amplified, and an output voltage of the readout chain of FIG. 8 according to some embodiments of the present disclosure;

[0031] FIG. 11 shows an example of the simulation result of the readout chain of

FIG. 8 according to some embodiments of the present disclosure;

[0032] FIG. 12 shows a circuit diagram of yet another exemplary high-speed signal readout chain according to some embodiments of the present disc losure;

[0033] FIG. 13 shows a circuit diagram of still another exemplary high-speed signal readout chain according to some embodiments of the present disclosure;

[0034] FIG. 14 is a schematic diagram illustrating an event-driven QIS without feedback reset according to some embodiments of the present disclosure;

[0035] FIG. 15 shows a circuit diagram of still another exemplary high-speed signal readout chain according to some embodiments of the present disclosure;

[0036] FIGs. 16A to 16C show theoretical results of an output voltage change of the jot, the output voltage change being amplified, and an output voltage of the readout chain of FIG. 15 according to some embodiments of the present disclosure;

[0037] FIG. 17 shows an example of the simulation result of the readout chain of

FIG. 15 according to some embodiments of the present disclosure;

[0038] FIG. 18 shows a circuit diagram of further another exemplary high-speed signal readout chain according to some embodiments of the present disclosure;

[0039] FIG. 19 shows column-parallel address-event representation (AER) readout architecture used for event-driven QIS according to some embodiments of the present disclosure; and

[0040] FIG. 20 is a schematic diagram illustrating a time-resolving device that employs an event-driven QIS according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF EMBODIMENTS [0041] The terms “a” or “an”, as used herein, are defined as one or more than one. The term “plurality”, as used herein, is defined as two or more than two. The term “another”, as used herein, is defined as at least a second or more. The terms “including” and/or “having”, as used herein, are defined as comprising (i.e., open language). Reference throughout this document to "one embodiment", “certain embodiments”, "an embodiment”, “an implementation”, “an example” or similar terms means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of such phrases or in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments without limitation.

[0042] The exemplary embodiments are described in the context of methods having certain steps. However, the methods and compositions operate effectively with additional steps and steps in different orders that are not inconsistent with the exemplary embodiments. Thus, the present disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein and as limited only by the appended claims.

[0043] Furthermore, where a range of values is provided, it is to be understood that each intervening value between an upper and lower limit of the range - and any other stated or intervening value in that stated range - is encompassed within the disclosure. Where the stated range includes upper and low'er limits, ranges excluding either of those limits are also included. Unless expressly stated, the terms used herein are intended to have the plain and ordinary meaning as understood by those of ordinary skill in the art. Any definitions are intended to aid the reader in understanding the present disclosure, but are not intended to vary or otherwise limit the meaning of such terms unless specifically indicated.

[0044] A CMOS quanta image sensor (QIS) contains a large array of sub-diffraction-limit, high conversion-gain, low-full-well-capacity specialized pixels, called jots. A QIS is capable of counting single photoelectrons at high speed without avalanche. In current QIS, the frame rate (e.g., 1,000 fps or 1 msec timing resolution) is not high enough to count single photons with high timing resolution. A single-photon avalanche diode (SPAD) image sensor or avalanche photodiode (APD) image sensor, however, can achieve a very high timing resolution (e.g., in the range of nanoseconds or picoseconds). However, it is difficult to shrink their pixel size due to required isolation between pixels due to the high electric fields, and the large in-pixel circuitry. The high electric fields for avalanche also result in high dark count rate. A CMOS QIS jot, however, has a low dark count rate, a high fill factor, a higher spatial resolution, an improved manufacturing yield, and does not require high voltages and avalanche multiplication, albeit at the cost of slower timing resolution compared to SPADs.

[0045] In the present disclosure, a high-speed (or high timing resolution) photon-counting CMOS QIS is disclosed. A jot-parallel 1-bit analog-to-digital converter (ADC) with a novel sw itch ed-c apaci tor input circuitry makes it possible to record the arrival time of the incident photons. Individual photoelectrons are distinguished owing to the high conversion gain of the jot. The new' method achieves a high timing resolution T and can detect single photons or photoelectrons at high speed (e.g., 100 MHz or 10 nsec timing resolution equal to a distance resolution D of D=cT/2, where c is the speed of light or 150cm) similar to a SPAD image sensor. Additionally, tw o event-driven readout circuitries w'ith a small layout area (e.g., 5μmx 5μm) are disclosed. The CMOS QIS is therefore feasible for highly time-resolved applications such as time-of- flight (ToF) 3D imaging and optical communications.

[0046] Illustrative embodiments of an image sensor having photon-counting jots and high-speed readout circuitry are disclosed. Such embodiments are well suited, for example, for achieving high-speed, single-photon detection. Some embodiments of the present disclosure are expected to achieve the counting of single photons with a timing resolution of several nanoseconds.

[0047] FIG. 1 A shows a circuit diagram of an exemplary high-speed signal readout chain (or image sensor) 100 according to some embodiments of the present disclosure. The image sensor 100 can be a QIS, a CMOS active pixel image sensor, or a pump-gate-type photodetector-device- based image sensor. The output signal of a jot 110 is sent to a continuous-sampling amplifier 120, follow'ed by a 1-bit ADC 130, binary readout circuitry. By way of non-limiting example, the continuous-sampling amplifier 120 may be a PMOS common source amplifier. The ADC 130 is configured to sample at a speed of at least 50MSa/s, for example 66.7 MSa/s. In the example embodiment, the ADC 130 can include a switched-capacitor input circuitry 132, a comparator 134 for analog-to-digital conversion, and a flip-flop such as a dynamic flip-flop (DFF) 136 to record the output of tire comparator 134. The switched-capacitor input circuitry 132 is operated in a way that the previous sample is always sent to the second input IN2 of the comparator 134 and the new sample is always sent to the first input INI of the comparator 134. The output OUT of the ADC 130, specifically, the DFF 136, is fed back to control the resetting of the comparator 134. When a photon is detected, the ADC 130 will output a digital “1,” which will turn on (or “close”) a reset switch OUT of the comparator 134. Accordingly, a reference voltage VREF will be injected to reset the output OUT of the ADC 130 to be digital “0.”

[0048] FIG. 1B is a schematic view of the jot 110 according to some embodiments of the present disclosure. FIG. 1C is a schematic view of a stacked-sensor architecture 180 that includes a plurality of the image sensors 100 according to some embodiments of the present disclosure.

The stacked-sensor architecture 180 can include stacked pixel wafer and ASIC wafer. The jot 110 and limited electronics, e.g., the amplifier 120, of each of the image sensors 100 can be formed on the pixel wafer, and additional readout electronics, e.g., the ADCs 130, can be formed on the ASIC wafer. For example, the pixel wafer can include five 1x2 shared jots with a pitch of 2.2x1.1 μm.

[0049] By way of example, FIGs. 2A, 2B, and 2C show cross-sectional views of three different types of illustrative pixels, e.g., the jot 110, that each incorporates a low-capacitance floating diffusion (FD) according to some embodiments of the present disclosure and a gated or gateless reset. More specifically, FIG. 2A schematically depicts a portion of a pixel jot 200a that includes a pinned photodiode (PPD) 210a formed laterally adjacent to an FD 220a and connected to the FD 220a using a lightly-doped layer N with the same dopant (N+) as the FD 220a, whereas FIG. 2B schematically depicts a portion of a pixel jot 200b that includes a photodiode 210b formed beneath a transfer gate (TG) 230b and configured as a vertical pump-gate with an FD 220b spaced away (distal) from the TG 230b to reduce and/or eliminate TG-FD overlap capacitance, and FIG. 2C schematically depicts a portion of a pixel jot 200c that includes a PPD 210c formed laterally adjacent to a TG 230c with a distal FD 220c. A gateless type reset or tapered-reset-gate (TRG) reset is illustrated to further reduce FD-node capacitance, as is known to those skilled in the art, although other reset methods such as a traditional gated reset might instead be employed. Either configuration can be illuminated from the front side or back side, and either can include color and/or polarization filters (not shown) as is well known to those skilled in the art. A continuous readout of the photoelectrons from the photodiodes 210a to 210c may be enabled by building a monotonically increasing potential profile from the photodiode storage well SW to the FD 220a for the pixel jot 200a illustrated in FIG. 2A, and by turning on the TGs 230b and 230c for the pixel jots 200b and 200c shown in FIGs. 2B and 2C.

[0050] FIG. 3 shows an exemplary comparator 300, e.g., the comparator 134, according to some embodiments of the present disclosure. For example, the comparator 300 can include a set of (e.g., a cascade of two) sense amplifiers (SAs) 310 and 320 and a dynamic latch 330. A 5T (five transistors) operational transconductance amplifier (OTA) may be utilized as the SAs 310 and 320. As is known to those skilled in the art, other types of amplifiers such as a low-power charge transfer amplifier (CTA) may also be implemented. By way of non-limiting example, a power-efficient dynamic latch can be used as the dynamic latch 330 since no static power is consumed. In the example embodiment, the dynamic latch 330 can include two cross-coupled inverters, e.g., M1-M3 and M2-M4. In operation, when OUT+ increases (OUT- decreases), the transistor M2 increases the current drawn from node, thereby decreasing its voltage; as a result, the transistor Ml will have reduced gate to source voltage, thus decreasing the current through Ml, causing voltage at OUT+ to increase. The cascade of the SAs 310 and 320 functions as the gain stage to amplify the output signal from the jot 110 to a level which is higher than the intrinsic input-referred offset voltage of the dynamic latch 330.

[0051] As is well known to those skilled in the art, the readout can be monolithically coupled to the jot pixels or can be configured by stacking two chips or wafers, with frilly parallel, cluster parallel, or edge connections between the two chips or wafers, one with the jot pixels, e.g., the jot 110, and limited electronics, e.g., the amplifier 120, and the other with additional readout electronics, e.g., the ADC 130. By way of example, a sensor (e.g., an image sensor) architecture 400 is shown in FIG. 4. As embodiments of the present disclosure are not limited to a particular sensor architecture, for clarity FIG. 4 focuses on the jot and per-jot readout portion of an image sensor and does not show other sensor features, such as driver circuitry and timing control logic. The output of the jot from the jot wafer is sent to the ASIC wafer to read out via interconnections such as hybrid bonding (not shown). Each jot has its readout circuitry. In the exemplary image sensor 100, the output signal of the jot 110 will be continuously amplified by the amplifier 120. The amplified signal is then digitized by the 1-bit ADC 130. The jot-parallel ADC, e.g., the ADC 130, is capable of sampling at a very high speed (e.g., 100 MSa/s).

[0052] The jot 110 has a high conversion gain (CG) (e.g., 345 μV/e-). The mean read noise at room temperature is so small (e.g., 0.23 e- rms) that the single photoelectron quantization effect can be easily observed. Once a photon is detected, the FD voltage will have a step drop. During the photodetection, the jot 110 is reset by pulsing both the reset gate (RG) and the TG high, and the TG will be kept high, or at a mid-level voltage after reset to enable continuous sampling. Further, the incident photon strikes the jot 110 and generates a photoelectron in the photodiode, e.g., the photodiodes 210a to 210c. The photoelectron will be transferred to the FD, e.g., the FDs 220a to 220c immediately and causes a step response of the FD voltage above background noise. The step voltage change will then be amplified. The 1-bit ADC 130 monitors any change that happens to the FD voltage. After a number of counts, the jot 110 needs to be reset. The operation timing diagram of the 1-bit ADC 130 is shown in FIG. 5. The amplified jot output is processed by the ADC 130 in four phases I to IV.

[0053] Phase I: SH1 = 0, SH2 = 1, SHC = 1.

[0054] Store new sample V _i output from the jot 110 in a second storage capacitor C2 (shown in FIG. 1) via the “closed” second switch SH2 (“1”). Connect a first storage capacitor Cl (where a previous sample V _i is stored) to the second input IN2 of the comparator 134 via the “switched- down” upper switch SHC (“1”), and the second storage capacitor C2 (where the new sample Vi is stored) to the first input INI of the comparator 134 via the “switched-down” lower switch SHC (“1”).

[0055] Phase II: SH1 = 0, SH2 = 0, SHC = 1.

[0056] Compare the previous sample Vj_i in the second input IN2 and the new sample V _; in the first input INI, when both the first switch SHI and the second switch SH2 (“0”) are “opened” and no new sample will be output from the jot 110 in the first storage capacitor Cl and the second storage capacitor C2.

[0057] Phase III: SH1 = 1, SH2 = 0, SHC = 0.

[0058] Store a next new sample V _i+1 output from the jot 100 in the first storage capacitor Cl via the “closed” first switch SHI (“1”). Connect the second storage capacitor C2 (where the previous new sample V, is stored) to the second input IN2 via the “switched-up” lower switch SHC (“0”), and the first storage capacitor Cl (where the next new sample V _i+1 is stored) to the first input IN1 via the “switched-up” upper switch SHC (“0”)..

[0059] Phase IV: SH1 = 0, SH2 = 0, SHC = 0.

[0060] Compare the previous new sample Vi in the second input IN2 and the next new sample V _i+1 in the first input INI, when both the first switch SHI and the second switch SH2 (“0”) are “opened” and no new sample will be output from the jot 110 in the first storage capacitor C l and the second storage capacitor C2. If the next new sample V _i+1 = the previous new sample V;, i.e., no photoelectron being added to the FD capacitor of the jot 110, the state of the comparator 134 will not change and stay at “0.” If the next new sample V _1+i > the previous new sample V,, i.e., a photoelectron being added to the FD capacitor of the jot 110 causing the FD voltage to drop and thus the output of the amplifier 120 (e.g., PMOS common-source amplifier) to increase, the state of the comparator 134 will change and output a “1.” The output will then be fed back, and turned on (if “1”) the reset switch of the comparator 134, leading to the injection of the reference voltage VREF to the first input INI to reset the state of the comparator 134 to “0.” In this way, the incident single photon is converted to a digital “1” at the output OUT. In the case where no photon impinges the jot 110, the output OUT will remain at “0.” Therefore, the arriving time of the incident photons will be recorded in the jot 110.

[0061] The high-speed QIS can also be used to construct a 2D image using computational imaging. The signal integration will be performed in the digital domain rather than the traditional analog domain (e.g., charge accumulation inside the photodiode). The integrated signal which forms the pixel value will be a sum of the digital ‘T’s over a certain period, i.e., the frame time. The frame image will be composed of an array of the summed signal at each jot location. Moreover, the high-speed QIS enables precise pixel binning. There will be no error due to the binning process since the binning is performed in the digital domain.

[0062] The photon-counting CMOS QIS with high-speed binary readout according to some embodiments of the present disclosure may be further understood through the time-domain jot output voltage change as photons impinge and the corresponding digital output, as shown in FIG. 6A. Each detected photon will generate a photoelectron that will be transferred to FD immediately and cause a step drop response ΔV. The step voltage drop ΔV will be converted to a digital “1” at the output, as illustrated in FIG. 6B. For example, three photons are detected at times t ₀ , t ₁ , and t ₂ , respectively, which results in the cumulative ΔV decreasing of the output of the jot 110 from the voltage V ₀ to voltages V ₀ - ΔV, V ₀ -2ΔV, and V ₀ -3ΔV, respectively.

[0063] FIG. 7A is a functional block diagram of a characterization system 700 for testing a device, e.g., the stacked-sensor architecture 180, according to some embodiments of the present disclosure. FIG. 7B shows an example of the measured frame with a sampling frequency of 33MHz and frame time of 11μs. Three digital ‘T’s are detected, indicating three photons impinging the jot 110. 3,000 frames were captured to construct the photon-counting histogram (PCH) 700b. An example of the PCH 700b is shown in FIG. 7C. The specifications of the image sensor 100 are summarized in the following Table.

[0064] A compact jot size is desired for a stacked jot-parallel readout. Simpler readout circuitry with fewer components can be employed to reduce the layout area. For example, a simple area efficient two-transistor inverter can be used as a l-bit comparator. FIG. 8 shows a circuit diagram of an exemplary high-speed signal readout chain (or image sensor) 800 according to some embodiments of the present disclosure. In the image sensor 800, a QIS is with an event- driven readout. A jot 810 outputs a step voltage drop when there is a photon detected. This step voltage change will be amplified by an amplifier 820, followed by a comparator 830 for digitization. The comparator 830 can be simply a CMOS inverter. The gain at the amplifier 820 needs to be large enough such that the output voltage of the amplifier 820 will cross the flip point of the inverter 830 and trigger an event at the output OUT of the inverter 830. The output OUT of the inverter 830 is fed back to control the resetting of the jot 810. Once there is an event detected, the voltage of the output OUT goes high and the jot 810 will be reset to its original status, ready for the next event detection.

[0065] By way of example, the schematic of the event-driven QIS 900 with feedback reset is shown in FIG. 9. The amplifier 820 shown in FIG. 8 is implemented as a common source amplifier 920 coupled to the output of a jot 910. A cascode configuration (or cascode amplifier stage) 940 is utilized to boost the gain (~800) to ensure that the output voltage of the amplifier 920 is large enough to flip a 1-bit comparator 930 (an inverter), which follows the amplification for digitization, and trigger an event at the output OUT. The event is interpreted as a digital pulse at the output OUT. By way of non-limiting example, the output OUT can be directly fed back to the reset gate RG of the jot 910, or fed back to the gate of an additional reset transistor 950, as shown in FIG. 9, depending on the applications. The whole circuit can be laid out with a small footprint (e.g., 5 μm > 5 μm jot pitch in a 45nm/65nm stacked process).

[0066] A theoretical result is shown in FIGs. 10A to 10C. When the jot 910 outputs a voltage change (V _IN ) ΔV, as shown in FIG. 10A, there will be a voltage change (V _AMP ) A×ΔV at the output of the cascode configuration 940, as shown in FIG. 10B, with A being the gain, which will cause the inverter 930 to flip, as shown in FIG. 10C. The feedback mechanism will reset the jot 910 and thus the output of the jot 910 will recover to its original status.

[0067] FIG. 11 shows an example of a simulation result. Similar to the theoretical result, the feedback mechanism converts the photon detection event to a digital pulse. The output voltage change (V _IN ) ΔV of the jot 910 when a photon is detected is set to be approximately 350μV, considering the measured average conversion gain A of the jot 910 is 350μV/e-. The gain A of the cascode amplifier stage 940 is designed to be high (e.g. 838V/V). The amplified step voltage change (V _AMp ) AΔV is thus hundreds of mV (e.g., 292mV), and able to flip the inverter 930. In this way, the single-photon triggered small step voltage is converted to a digital pulse (V _OUT ) at the output OUT. The jot source follower 920 is biased at 1μA and the cascode common source amplifier 940 is biased at 10 μA, while the inverter 930 consumes no static power. The power rail VDD is 2.5V. Therefore, the total power consumption is 27.5μW. Moreover, it can be seen from FIG. 11 that it takes a very short time (e.g., lps) to output an event. Therefore, the maximum detection rate for this configuration is high (e.g., 1 MHz). [0068] Amplitude filtering circuitry may be employed, as shown in FIG. 12, which shows a circuit diagram of an exemplary high-speed signal readout chain (or image sensor) 1200 according to some embodiments of the present disclosure. The image sensor 1200 differs from the image sensor 800 shown in FIG. 8 in that the image sensor 1200 further includes an amplitude filter 1250. Noise can lead to false triggering for event-driven QIS, especially when the FD-referred noise is as high as several electrons. The amplitude filter 1250 can suppress or filter the possible high-amplitude noise such as kTC noise and random telegraph noise (RTN). Generally, 1/f noise in QIS is much smaller than kTC noise or RTN (e.g., 0.29e- rms vs. ~8e- mis). False triggering due to kTC or RTN noise therefore may be suppressed by the amplitude filter 1250 such that only the wanted signal can trigger an event.

[0069] Lower amplitude noise like 1/f noise could also cause a false trigger if the amplifier's gain is not large enough. Noise on the order of 0.5e- or -200 uV would be amplified to ~40 mV with the gain of 200 of a common source amplifier, e.g., the amplifier 120, causing the comparator, e.g., the comparator 134, to trigger falsely. To reduce this occurrence, a capacitor connected to ground and the reference voltage VREF via a switch can be implemented at the first input IN1 of the comparator 134, as shown in FIG. 13, which is a circuit diagram of an exemplary high-speed signal readout chain (or image sensor) 1300 according to some embodiments of the present disclosure. A third storage capacitor C3, e.g., a single-pole double- throw switch, connects to ground during the sampling phase, e.g., Phases I and III, via a “closed” third switch (“1”) to lower the voltage on the first input INI slightly. The signal entering the first input IN1 of the amplifier 134 would then have to overcome this additional voltage threshold to trigger the comparator 134, decreasing the probability of false triggers. During reset, the third storage capacitor C3 would then recharge back to the reference voltage VREF.

The third storage capacitor C3 is sized to implement a negative threshold large enough to prevent false triggers from low-amplitude noise without reducing the sensor's photon detection accuracy. Similar topologies to prevent false triggers from low-amplitude noise may utilize a voltage divider or resistor in series with the first input INI, for example.

[0070] Alternatively, an event-driven QIS without feedback reset, e.g., a readout chain (or an image sensor) 1400, is disclosed and the block diagram is shown in FIG. 14 according to some embodiments of the present disclosure. Different from the image sensor 800 with feedback reset, the event in the image sensor 1400 is converted to a rising/falling edge (of the output OUT of a comparator 1430 (e.g., an inverter)) instead of a digital pulse.

[0071] By way of a non-limiting example, FIG. 15 shows an exemplary circuitry 1500 of the image sensor 1400, without feedback reset, according to some embodiments of the present disclosure. The circuitry 1500 can be laid out with a small footprint (e.g., 5μmx5μm jot pitch in a 45nm/65nm stacked process.

[0072] The theoretical result is shown in FIGs. 16A to 16C. When the jot 810 of the image sensor 1300 outputs a voltage change (V _IN ) ΔV, as shown in FIG. 16A, the amplifier 820 will output AxΔV (V _AMP ), as shown in FIG. 16B. This will cause the inverter 1430 to flip (V _OUT ), as shown in FIG. 16C, and an event is recorded. In this way, the single-photon triggered small step voltage is reflected as a digital code change (i.e., rising/falling edges) at the output OUT.

[0073] FIG. 17 shows a simulation result. Similar as the event-driven QIS with feedback reset, the jot source follower 920 is biased at ImA and the cascode common source amplifier 940 is biased at 10μA, while the inverter 1430 consumes no static power. Therefore, the total power consumption is 27.5μW. As can be seen from FIG. 17, the settling time for the output remains small (3μs). Thus, the maximum detection rate for this configuration is high (0.33MHz).

[0074] Similarly, the amplitude filter 1250 can be added in another exemplary high-speed signal readout chain (or image sensor) 1800, as shown in FIG. 18. According to some embodiments of the present disclosure, the image sensor 1800 can further include the jot 810, the amplifier 820 and the comparator (e.g., an inverter) 1430.

[0075] By way of non-limiting example, a column-parallel address-event representation (AER) readout architecture 1900 can be used for event-driven QIS, as shown in FIG. 19, according to some embodiments of the present disclosure. The column AER readout architecture 1900 can include photosensitive elements, i.e., a jot array, output transistors M _OUT , N encoding transistors M ₀ -M _N-1 , pull-up resistors PURs, and DFFs. The photons from the scene are assumed to be sparse, such that one event from a jot on a column is processed at a time. The row address is encoded by the N pull-down transistors and N column bus lines while N is log2(M) and M is the number of rows. Once there is an event, the address ADDR of the jot where the event is detected will be latched. In this way, the events appear at the output nOUT of the sensor as an asynchronous stream of digital pixel addresses. The address ADDR can be directly saved to a PC or be used to locate a memory element for storage. This readout is power-efficient since it consumes no power when there is no event. The data redundancy is effectively suppressed thanks to the AER protocol. Assuming a 1 mega jot array (1024Hx 1024V), 10 bits are needed to decode the row. Therefore, 10 additional transistors are needed to locate where an event happens. Overall, the layout area is small compared to the jot pitch (e.g., 2μm ² vs. 25μm ² ). The column- parallel readout architecture 1900 is scalable to a large array. Other readout circuitries, especially those for bioinspired vision sensors or SPAD image sensors, can be adapted to the event-driven QIS.

[0076] Event-driven QIS according to some embodiments of the present disclosure can be employed in a time-resolving device or system 2000 used for distance sensing applications, as illustrated in FIG. 20. A light source (e.g., a laser source) 2010 emits a light beam (e.g., a modulated pulse) at a target and the light beam reflects off the target and returns to the timeresolving system 2000 where the image sensor (e.g., the event-driven QIS) 2020 detects the reflected light beam. A controller 2040 is coupled to the image sensor 2020 and the light source 2010 and is configured to generate a synchronization signal, which synchronizes the pulses of the light beam emitted from the light source 2010 with corresponding modulation signals that control the plurality of pixels in the image sensor 2020. Upon striking the QIS 2020, the light beam is converted to electrons in the pixel and readout of the image sensor 2020 using the previously described event-driven circuitry. Next, the signal is timestamped using a timing circuit such as a time-to-digital converter (TDC) (not shown) and the result may be stored in a histogram memory 2030. The timestamps are then used to calculate the object's distance. Other components, including, but not limited to, software, optics, navigation, and GPS, can also be present in the time-resolving system 2000 to record additional information.

[0077] Thus, the foregoing discussion discloses and describes merely exemplary embodiments of the present inventions. As will be understood by those skilled in the art, the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Accordingly, the disclosure of the present inventions is intended to be illustrative, but not limiting of the scope of the inventions, as well as other claims. The disclosure, including any readily discernible variants of the teachings herein, defines, in part, the scope of the foregoing claim terminology such that no inventive subject matter is dedicated to the public.

[0078] Embodiments of the present disclosure may also be as set forth in the following parentheticals.

[0079] (1) A sensor, comprising: a photon-counting pixel that does not use avalanche multiplication for gain configured to generate an output voltage change w'hen impinged by a photon; andbinary readout circuitry coupled to the photon-counting pixel, the binary readout circuitry configured to output a first binary signal when receiving the output voltage change and a second binary signal when not receiving the output voltage change.

[0080] (2) The sensor of (1), further comprising an amplifier coupled between the photon-counting pixel and the binary readout circuitry, the amplifier configured to amplify the output voltage change.

[0081] (3) The sensor of (2), wherein the amplifier includes a source follower.

[0082] (4) The sensor of (1), wherein the binary readout circuitry includes a comparator.

[0083] (5) The sensor of (4), wherein the comparator includes an inverter.

[0084] (6) The sensor of (4), wherein the binary readout circuitry further comprises a switched-capacitor input circuitry coupled between the photon-counting pixel and the comparator.

[0085] (7) The sensor of (6), wherein the switched-capacitor input circuitry comprises: a first storage capacitor; a first switch coupled between the photon-counting pixel and a first end of the first storage capacitor; a second storage capacitor with a first end coupled to a second end of the first storage capacitor; a second switch coupled between the photon-counting pixel and a second end of the second storage capacitor; an upper switch coupled between the first storage capacitor and the comparator, the upper switch configured to connect the first end of the first storage capacitor to a first input or a second input of the comparator; and a lower switch coupled between the second storage capacitor and the comparator, the lower switch configured to connect the other end of the second storage capacitor to the second input or the second input of the comparator.

[0086] (8) The sensor of (7), further comprising: one or more third storage capacitors each with a first end coupled to the first input of the comparator; and one or more switches each coupled to a second end of a corresponding one of the third storage capacitors, the third switches configured to connect the second ends of the third storage capacitors to the reference voltage or ground.

[0087] (9) The sensor of (6), wherein the comparator comprises: a set of sense amplifiers

(SAs) coupled to the switched-capacitor input circuitry; and a latch coupled to the set of SAs. [0088] (10) The sensor of (9), wherein the latch includes a dynamic latch.

[0089] (11) The sensor of (9), wherein at least one of the SAs includes a five-transistor

(5T) operational transconductance amplifier (OTA).

[0090] (12) The sensor of (9), wherein at least one of the SAs includes a low-power charge transfer amplifier (CTA).

[0091] (13) The sensor of (6), wherein the binary readout circuitry further includes a flip- flop (FF) coupled to the comparator.

[0092] (14) The sensor of (13), wherein the FF is a dynamic FF (DFF).

[0093] (15) The sensor of (1), further comprising a cascode amplifier coupled between the photon-counting pixel and the binary readout circuitry, wherein the binary readout circuitry comprises an inverter, and the cascode amplifier is configured to amplify the output voltage change such that the output voltage change being amplified is large enough to flip the inverter. [0094] (16) The sensor of (1), wherein the binary readout circuitry has an output that is fed back to the photon-counting pixel.

[0095] (17) The sensor of (1), further comprising an amplitude filter coupled between the photon-counting pixel and the binary readout circuitry, the amplitude filter configured to suppress noise in the output voltage change.

[0096] (18) The sensor of (1), wherein the sensor is a single-bit quanta image sensor

(QIS).

[0097] (19) The sensor of (1), wherein the sensor is a complementary metal-oxide- semiconductor (CMOS) active pixel image sensor.

[0098] (20) A time-resolving device for distance sensing, the device comprising: a light source configured to emit a first light; and an array of the sensors of (1), each of the sensors being configured to sense a second light reflected by the first light.