Cross-reference to related application

[0001] This application claims the benefit of priority of United States provisional patent application no. 61/224,256 filed on 9 July 2009, the contents of which is hereby incorporated by reference in its entirety for all purposes.

Technical Field

[0002] Embodiments relate to a piezoresistive sensor and a method of controlling giant piezoresistive coefficient or gauge factor (GF) of at least one piezoresistive element.

Background

[0003] In general, metal offers relatively low gauge factors of typically below 2, thus restricting the usage of metal for highly sensitive sensor applications. For semiconductor, the resistance change is larger than metal by a factor of about 50 and is dependent on doping, temperature, crystalline orientation, for example.

[0004] Recently, silicon-nanowire (SiNW) was known to offer giant piezoresistance due to the carrier depletion by mechanical stress. However, this requires the use of relatively high voltages to obtain the depletion region, which may not be compatible with low power application-specific integrated circuit (ASIC). Further, implementation of the SiNW for sensor application may also be difficult. [0005] Therefore, there is a need to provide an alternative piezoresistive sensor or a method of controlling the giant piezoresistance which may overcome or at least alleviate some of the above- mentioned problems.

Summary

[0006] Various embodiments provide a piezoresistive sensor and a method of controlling giant piezoresistive coefficient of at least one piezoresistive element which may allow tuning of the giant piezoresistive coefficient at low voltages as per sensor requirements in general. Further, the piezoresistive sensor and the method of controlling giant piezoresistive coefficient of the at least one piezoresistive element may allow for precise control of the giant piezoresistive coefficient.

[0007] In various embodiments, a method of controlling giant piezoresistive coefficient of at least one piezoresistive element may be provided. The method may include providing an electric field to the at least one piezoresistive element to thereby create a depletion region in the at least one piezoresistive element; applying a stress onto the at least one piezoresistive element to modulate concentration and mobility of charge carriers along the at least one piezoresistive element; and varying the electric field applied onto the at least one piezoresistive element to control the giant piezoresistive coefficient of the at least one piezoresistive element.

[0008] In various embodiments, a piezoresistive sensor may be provided. The piezoresistive sensor may include at least one piezoresistive element; an electric field source configured to provide an electric field to the at least one piezoresistive element to thereby create a depletion region in the at least one piezoresistive element; a stress applicator configured to apply a stress onto the at least one piezoresistive element to modulate concentration and mobility of charge carriers along the at least one piezoresistive element; and a controller configured to vary the electric field applied within the at least one piezoresistive element to thereby control giant piezoresistive coefficient of the at least one piezoresistive element.

Brief Description of the Drawings

[0009] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of various embodiments. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:

FIG. 1 shows a flowchart of a method of controlling giant piezoresistive coefficient of at least one piezoresistive element according to an embodiment;

FIG. 2 shows a piezoresistive sensor, the piezoresistive sensor comprising a nanowire positioned in a mechanically deformable structure according to an embodiment;

FIG. 3A shows a schematic of a test setup of a piezoresistive sensor showing a nanowire embedded next to an anchor of a cantilever and a mechanical stylus contacting and deflecting the cantilever according to an embodiment; FIG. 3B shows a scanning electron microscopy (SEM) image of the released cantilever according to an embodiment; FIG. 3C shows a distribution of holes concentration in the nanowire as a function of gate-source voltage (V _GS ) according to an embodiment;

FIGs. 4A to 4D shows respective measurements of drain current as a function of stress with gate voltage as a parameter according to an embodiment;

FIG. 5 shows an extracted gauge factor as a function of gate voltage according to an embodiment; FIG. 6 shows a cross-section schematic of a piezoresistive sensor, the piezoresistive sensor comprising a gate-all-around nanowire field-effect transistor (GAA NWFET) with a nanowire channel body, a gate oxide layer and a conductive surrounding gate according to an embodiment;

FIG. 7A shows a defect-review scanning-electron-microscope (DRSEM) image of a piezoresistive sensor after silicon nanowire formation according to an embodiment; FIG. 7B shows a DRSEM image of the piezoresistive sensor after gate patterning according to an embodiment;

FIG. 8A show a DRSEM image of a beam structure, wherein two nanowires are positioned in or on the beam structure according to an embodiment; FIG. 8B show a DRSEM image of a membrane, wherein a nanowire is positioned in or on the membrane according to an embodiment; and

FIG. 9A show a DRSEM image of a piezoresistive sensor including a nanowire resistor according to an embodiment; FIG. 9B show a DRSEM image of a piezoresistive sensor including a nanowire transistor according to an embodiment.

Description

[0010] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. [0011] Giant piezoresistance in SiNWs by the modulation of an electric field induced with an external electrical bias may be demonstrated. Positive bias for a p-type device (negative bias for an n-type device) partially depleted the NWs forming a pinch-off region or depletion region, which resembled a funnel through which an electrical current is squeezed. This pinch-off region determines the total current flowing through the NWs. The electrical biasing may be combined with the application of a mechanical stress, which impacts the charge carriers' concentration, to achieve an electrically controlled giant piezoresistance in NWs. The phenomenon may be used to create a stress-gated FET, exhibiting a maximum gauge factor of about 5000, 2 orders of magnitude increase over bulk value. Giant piezoresistance may be tailored to create highly sensitive mechanical sensors operating in a discrete mode such as nanoelectromechanical switches.

[0012] An embodiment may provide for a method of controlling giant piezoresistive coefficient of at least one piezoresistive element. The method may include providing an electric field to the at least one piezoresistive element to thereby create a depletion region in the at least one piezoresistive element; applying a stress onto the at least one piezoresistive element to modulate concentration and mobility of charge carriers along the at least one piezoresistive element; and varying the electric field applied onto the at least one piezoresistive element to control the giant piezoresistive coefficient of the at least one piezoresistive element.

[0013] By combining the formation of the pinch-off region with mechanical stress, a modulation of the GF by about 2 orders of magnitude from 50 to 5000 may be achieved, creating an electrically controlled giant piezoresistance in nanowires. In this regard, the application of stress alone may not change the giant piezoresistive coefficient, it may only change the resistance by changing the concentration and mobility of the charge carriers. [0014] In an embodiment, providing the electric field to the at least one piezoresistive element may include providing the electric field in at least one direction substantially perpendicular to a longitudinal extension of the at least one piezoresistive element. The electric field may be provided in a single direction substantially perpendicular to the longitudinal extension of the at least one piezoresistive element, for example when the electric field source may include a planar conductive substrate positioned adjacent to the at least one piezoresistive element. Alternatively, the electric field may be provided in a few directions around the at least one piezoresistive element, all of the directions substantially perpendicular to the longitudinal extension of the at least one piezoresistive element, for example when the electric field source may include a conductive gate configured to surround the at least one piezoresistive element.

[0015] In an embodiment, the at least one piezoresistive element may be a portion of a piezoresistive sensor, the piezoresistive sensor may further include a conductive substrate positioned adjacent to the at least one piezoresistive element; wherein providing the electric field to the at least one piezoresistive element may include providing a bias voltage across the conductive substrate and one end of the at least one piezoresistive element so as to induce the electric field in the at least one piezoresistive element.

[0016] In an embodiment, the at least one piezoresistive element may be a portion of a piezoresistive sensor, the piezoresistive sensor may further include a conductive gate configured to surround the at least one piezoresistive element; wherein providing the electric field to the at least one piezoresistive element may include providing a bias voltage across the conductive gate and one end of the at least one piezoresistive element so as to induce the electric field in the at least one piezoresistive element.

[0017] In an embodiment, applying the stress onto the at least one piezoresistive element may include applying the stress directly or indirectly onto the at least one piezoresistive element. Applying the stress directly on the at least one piezoresistive element may include positioning a stress applicator in direct contact with the at least one piezoresistive element whereas applying the stress indirectly onto the at least one piezoresistive element may include positioning the piezoresistive element within a further structure, for example a cantilever or a beam and then applying the stress onto the further structure such that the stress applied onto the further structure may be translated onto the piezoresistive element.

[0018] In an embodiment, applying a stress onto the at least one piezoresistive element may include applying a pressure, a force or a molecular absorption onto the at least one piezoresistive element for example.

[0019] In an embodiment, the stress or mechanical strain may be a result of a molecular absorption on a surface of the piezoresistive element and the molecules may include biomolecules such as proteins, nucleic acids or peptides. In relation to molecular absorption, the biomolecules may be absorbed on the surface of the cantilever immersed in a liquid environment. This may result in a different stress distribution that may be sensed by the piezoresistive element.

[0020] In an embodiment, the stress or mechanical strain may also be a result of a pressure applied onto the piezoresistive element, a contact from a mechanical part onto the piezoresistive element or a contact or movement from a living organism (s), such as a cell (s), tissue, or organ (s) onto the piezoresistive element.

[0021] The stress may be applied directly onto the at least one piezoresistive element by applying a pressure, a force or a molecular absorption directly onto the at least one piezoresistive element. The stress may also be applied indirectly onto the at least one piezoresistive element by positioning the at least one piezoresistive element within a mechanically deformable structure and then applying the stress onto any suitable portions along the mechanically deformable structure such that stress applied onto the mechanically deformable structure may be translated onto the at least one piezoresistive element.

[0022] In an embodiment, the at least one piezoresistive element may be a portion of a piezoresistive sensor, the piezoresistive sensor may further include a mechanically deformable structure, the at least one piezoresistive element may be positioned in or on a mechanically deformable structure; wherein applying the stress onto the at least one piezoresistive element may include exerting a mechanical stylus or any other suitable mechanical means at a free-end portion of the mechanically deformable structure spaced apart from the conductive substrate such that the free-end portion may be configured to move towards or away from the conductive substrate or a horizontal plane of the conductive substrate so as to apply a stress onto the at least one piezoresistive element. The free-end portion of the mechanically deformable structure may be positioned over the conductive substrate such that the free-end portion may be configured to overlap or not overlap with the conductive substrate. The mechanically deformable may be configured to be relatively rigid so that stress applied onto the mechanically deformable structure may be translated to the at least one piezoresistive element.

[0023] In an embodiment, a piezoresistive sensor may be provided. The piezoresistive sensor may include at least one piezoresistive element; an electric field source configured to provide an electric field to the at least one piezoresistive element to thereby create a depletion region in the at least one piezoresistive element; a stress applicator configured to apply a stress onto the at least one piezoresistive element to modulate concentration and mobility of charge carriers along the at least one piezoresistive element; and a controller configured to vary the electric field applied within the at least one piezoresistive element to thereby control giant piezoresistive coefficient or gauge factor of the at least one piezoresistive element. The number of piezoresistive element may vary depending on user and design requirements. In the case of a plurality of piezoresistive elements, each of the plurality of piezoresistive elements may be positioned adjacent and parallel to each other.

[0024] In an embodiment, the electric field source may be configured to provide the electric field to the at least one piezoresistive element in at least one direction substantially perpendicular to a longitudinal extension of the at least one piezoresistive element.

[0025] In an embodiment, the electric field source may include a conductive substrate positioned adjacent to the at least one piezoresistive element. The conductive substrate may be a substantially planar conductive substrate and may include a material selected from a group consisting of silicon, polysilicon, metals, for example.

[0026] In an embodiment, the electric field source may include a conductive gate configured to surround the at least one piezoresistive element. The conductive gate may be configured to completely surround or substantially surround the at least one piezoresistive element. The conductive gate may be of the same or different material as the conductive substrate. The conductive gate may include a material selected from a group consisting of silicon, polysilicon, metals, for example.

[0027] In an embodiment, the electric field source may further include a bias voltage source connected between the conductive substrate or the conductive gate and one end of the at least one piezoresistive element so as to induce the electric field in the at least one piezoresistive element.

[0028] In an embodiment, the piezoresistive sensor may further include a mechanically deformable structure, wherein the at least one piezoresistive element may be positioned in or on the mechanically deformable structure. The at least one piezoresistive element may be positioned at any suitable position within the mechanically deformable structure, for example at a location where the stress is most effectively being translated thereupon. [0029] In an embodiment, the mechanically deformable structure may be positioned adjacent to the conductive substrate and configured such that the mechanically deformable structure may be in contact with the conductive substrate at a contact portion and spaced apart from the conductive substrate at a free-end portion. The contact portion serves as an anchor for the mechanically deformable structure such that the mechanically deformable structure is free to deflect so as to translate the stress onto the piezoresistive element.

[0030] In an embodiment, the piezoresistive sensor may further include a plurality of stiffeners positioned between the mechanically deformable structure and the conductive substrate, wherein at least one of the plurality of stiffeners may be embedded in the contact portion of the conductive substrate. The number of stiffeners may vary depending on user and design requirements. Each of the plurality of stiffeners may be made from silicon oxide (SiO ₂ ) trenches and the plurality of stiffeners may be used to prevent bucking of the mechanically deformable structure.

[0031] In an embodiment, the stress applicator may be positioned adjacent and in a direction substantially perpendicular to the free-end portion of the mechanically deformable structure and configured to apply pressure on the free-end portion such that the free-end portion may be configured to move towards or away from the conductive substrate so as to apply a stress onto the at least one piezoresistive element. The stress applicator may also be positioned adjacent and along the same horizontal plane as the mechanically deformable structure to apply pressure on the free-end portion along the longitudinal extension of the at least one piezoresistive element.

[0032] In an embodiment, the positioning of the at least one piezoresistive element close to the anchor of the mechanically deformable structure may result in a creation of a compressive stress in the at least one piezoresistive element when a vertical load is applied onto the mechanically deformable structure. [0033] In an embodiment, the stress applicator may include a mechanical stylus or molecular absorption on the at least one piezoresistive element. The mechanical stylus may be a PZT controlled stylus or any other suitable stylus.

[0034] In an embodiment, the at least one piezoresistive element may be positioned at a bending portion along the mechanically deformable structure such that an applied pressure on the free- end portion may be translated to the stress onto the at least one piezoresistive element, the bending portion positioned between the contact portion and the free end portion.

[0035] In an embodiment, the mechanically deformable structure may include a cantilever, a beam structure or a membrane, for example.

[0036] In an embodiment, the at least one piezoresistive element may include at least one nanowire resistor or at least one nanowire transistor. Each of the at least one nanowire resistor or at least one nanowire transistor may include one nanowire or a plurality of nanowires depending on user and design requirements. The plurality of nanowires may be arranged in any suitable arrangement within the at least one nanowire resistor or at least one nanowire transistor.

[0037] In an embodiment, the piezoresistive element refers to either nanowire resistor or nanowire transistor. The piezoresistive sensor refers to the sensor including the nanowire resistor or nanowire transistor as sensing element.

[0038] The at least one nanowire transistor may include multi-gate devices or multiple gate field effect transistors (MuGFETs). Examples of the multi-gate devices or MuGFETs may include planar double-gate transistors, Flexfet, FINFETs, tri-gate transistors, GAA FETs.

[0039] For both the nanowire resistor and the nanowire transistor type of piezoresistive element, an electric field is applied to control their giant piezoresistance coefficient. However, the ways of applying the electric field may be different. For the nanowire resistor, the electric field is applied through the conductive substrate which forms the gate terminal of the nanowire resistor. With such configuration, the electric field is applied from only one direction. For the nanowire transistor, the electric field is applied through the surrounded gate or conductive gate and the electric field is applied from more than one direction.

[0040] hi an embodiment, for a nanowire resistor type of piezoresistive element, the conductive substrate may form a gate terminal of the at least one nanowire resistor. The respective ends of the at least one piezoresistive element or nanowire may form the respective source terminal and the drain terminal of the at least one nanowire resistor.

[0041] hi an embodiment, for a nanowire transistor type of piezoresistive element, the conductive gate may form a gate terminal of the at least one nanowire transistor. Similarly, the respective ends of the at least one piezoresistive element or nanowire may form the respective source terminal and the drain terminal of the at least one nanowire transistor.

[0042] In an embodiment, the stress may be a tensile stress or a compressive stress. The stress may be a longitudinal stress, a transverse stress or a shear stress with respect to the at least one piezoresistive element for example.

[0043] hi an embodiment, the at least one piezoresistive element may include a semiconductor material selected from a group consisting single crystalline silicon, poly silicon, germanium and gallium arsenic. The at least one piezoresistive element or nanowire may also include any suitable semiconductor material with piezoresistive feature such that the conductivity of the semiconductor material with piezoresistive feature may be affected by an external electric field.

[0044] hi an embodiment, the at least one piezoresistive element may include a plurality of piezoresistive elements. The number of the piezoresistive elements may vary depending on user and design requirements. The controller may be configured to control the electric field applied within each of the plurality of piezoresistive elements to thereby control the giant piezoresistive coefficient of each of the plurality of piezoresistive elements independently. [0045] In an embodiment, the method of tuning giant gauge factor for piezoresistive sensor with low voltages may be disclosed. In particular, the depletion regions may be effectively modulated to achieve giant piezoresistance. The method of tuning the piezoresistance may be performed at low voltages as per the sensor requirements. Temperature compensation and calibration of the sensor prior to data acquisition may be incorporated as well.

[0046] In an embodiment, the method of controlling giant piezoresistive coefficient of the piezoresistive element may be used for various piezoresistive based sensors. The method may also enable temperature compensation and self testing capability for the sensors which may be an attractive feature for physical sensors. The method may also be applied for biomedical applications including implantable microsystems. The method may enable miniaturised sensors and may be implemented in pressure, force, accelerometer and flow sensors.

[0047] In an embodiment, the piezoresistive properties of a material are usually characterized by their piezoresistive coefficients {π) or gauge factors (GF). Piezoresistive coefficient is the fractional change in resistivity dp/p per unit stress σ: dp/p dp/p

π =

^Eε Equation (1) where E is the Young's modulus of the material and e is the applied mechanical strain.

[0048] Gauge factor (GF) is the relative change in electrical resistance dR/R per unit mechanical strain e: dR/R

GF = = 1 + 2v + En-

Equation (2) where v is the Poisson's ratio of the material. For most of the semiconductor materials, the third term in the above formula is most dominant. Hence, the relationship between piezoresistive coefficient and gauge factor can be simplified as:

GF = Eπ _Equa tion (3)

[0049] FIG. 1 shows a flowchart 100 of a method of controlling giant piezoresistive coefficient of at least one piezoresistive element 108 according to an embodiment.

[0050] In 102, the method may include providing an electric field to the at least one piezoresistive element 108 to thereby create a depletion region in the at least one piezoresistive element 108. Next in 104, the method may further include applying a stress onto the at least one piezoresistive element 108 to modulate concentration and mobility of charge carriers along the at least one piezoresistive element 108. In 106, the method may then include varying the electric field applied onto the at least one piezoresistive element 108 to control the giant piezoresistive coefficient of the at least one piezoresistive element 108.

[0051] FIG. 2 shows a piezoresistive sensor 110, the piezoresistive sensor 110 including a nanowire 112 positioned in a mechanically deformable structure 116 according to an embodiment.

[0052] The piezoresistive sensor 110 as shown in FIG. 2 may be a nanowire resistor 154 type of piezoresistive sensor. The piezoresistive sensor 110 may include the nanowire 112; an electric field source 118 configured to provide an electric field to the nanowire 112 to thereby create a depletion region in the nanowire 112; a stress applicator 120 configured to apply a stress onto the nanowire 112 to modulate concentration and mobility of charge carriers (not shown) along the nanowire 112; and a controller 122 configured to vary the electric field applied within the nanowire 112 to thereby control giant piezoresistive coefficient or gauge factor of the nanowire 112. The piezoresistive sensor 110 may include one nanowire 112 or a plurality of nano wires 112 depending on user and design requirements.

[0053] For the nanowire resistor 154 type of piezoresistive sensor, the electric field source 118 may be configured to provide the electric field to the nanowire 112 in one single direction substantially perpendicular to a longitudinal extension of the nanowire 112 (as shown by the arrows). The electric field source 118 may include a conductive substrate 124 positioned below the nanowire 112 and the electric field is applied to the nanowire 112 from the backside. The conductive substrate 124 may be substantially planar or may be of any suitable dimension or shape as long as the electric field is being induced onto the nanowire 112. The conductive substrate 124 may include a material which may be able to form the electric field between the conductive substrate 124 and the nanowire 112 thus modulating the conductivity of the nanowire 112. Some examples of materials for the conductive substrate 124 may include a material selected from a group consisting of silicon, polysilicon, metal, for example.

[0054] Further, the electric field source 118 may include an electrode layer 126 disposed on the conductive substrate 124. In FIG. 2, the electrode layer 126 is seen to be disposed below the conductive substrate 124, but the electrode layer 126 may be disposed at any position in contact with the conductive substrate 124. The dimension of the electrode layer 126 and the amount of overlap between the electrode layer 126 and the conductive substrate 124 may vary depending on design and user requirements. The electrode layer 126 may include a metallic material selected from a group consisting of aluminum, gold, for example.

[0055] The controller 122 may further include a bias voltage source (V _GS ) connected between the electrode layer 126 and one end of the nanowire 112 so as to induce and vary the electric field in the nanowire 112. [0056] The piezoresistive sensor 110 may further include the mechanically deformable structure 116, wherein the nanowire 112 may be positioned in the mechanically deformable structure 116. The nanowire 112 may be positioned at any suitable position on or within the mechanically deformable structure 116, for example at a location where the stress is most effectively being translated thereupon. As shown in FIG. 2, the mechanically deformable structure 116 may include a cantilever 114. However, the mechanically deformable structure 116 may include any other suitable structures which include some degree of flexibility for bending. The dimension and shape of the mechanically deformable structure 116 may vary depending on user and design requirements.

[0057] The mechanically deformable structure 116 may be positioned adjacent to the conductive substrate 124 and configured such that the mechanically deformable structure 116 may be in contact with the conductive substrate 124 at a contact portion 128 and vertically spaced apart from the conductive substrate 124 at a free-end portion 130. The contact portion 128 serves as an anchor for the mechanically deformable structure 116 such that the mechanically deformable structure 116 is free to deflect so as to translate the stress onto the nanowire 112.

[0058] The piezoresistive sensor 110 may further include a plurality of stiffeners 132 positioned between the contact portion 128 of the mechanically deformable structure 116 and the conductive substrate 124, wherein some of the plurality of stiffeners 132 may be embedded in the conductive substrate 124. The number of stiffeners 132 may vary depending on user and design requirements. Each of the plurality of stiffeners 132 may be made from silicon oxide (SiO ₂ ) trenches and the plurality of stiffeners 132 may be used to prevent bucking of the mechanically deformable structure 116. The number of stiffeners 132 and the arrangement of each of the plurality of stiffeners 132 relative to each other may vary depending on user and design requirements. [0059] The stress applicator 120 may be positioned substantially perpendicular and in contact with the free-end portion 130 of the mechanically deformable structure 116 so as to apply a downward pressure on the free-end portion 130 such that the free-end portion 130 may be configured to move towards or away from the conductive substrate 124 so as to apply a stress onto the nanowire 112. The direction of the pressure may vary depending on user and design requirements. Mechanical stress applied on the piezoresistive element 108 or nanowire 112 may cause an increase of the charge carriers' concentration.

[0060] The stress applicator 120 may be a PZT controlled stylus or any other suitable mechanical suitable stylus. As a further example, the stress applicator 120 may also include molecular absorption on the nanowire 112.

[0061] The nanowire 112 may be positioned at a bending portion 134 along the mechanically deformable structure 116 such that an applied pressure on the free-end portion 130 may be translated to the stress onto the nanowire 112, the bending portion 134 positioned between the contact portion 128 and the free-end portion 130. The location of the nanowire 112 close to the contact portion or anchor 128 of the mechanically deformable structure 116 may result in a creation of a compressive stress in the nanowire 112 when a vertical load is applied onto the mechanically deformable structure 116.

[0062] For the nanowire resistor 154 type of piezoresistive sensor, the conductive substrate 124 and the electrode layer 126 may form a gate terminal 136 of the nanowire resistor 154. The one end of the nanowire 112 may form a source terminal 138 of the nanowire resistor 154 and be connected to a source pad 140. A further end of the nanowire 112 positioned opposite to the one end may form a drain terminal 142 of the nanowire resistor 154 and be connected to a drain pad 144. The bias voltage source 122 connected between the conductive substrate 124 or the electrode layer 126 and one end of the nanowire 112 may be termed "VQ _S "- And there may be a further bias voltage source 146 connected between the one end or source terminal 128 and the further end or the drain terminal 142 of the nanowire 112. The further bias voltage source 146 may be termed "VQS"-

[0063] The stress may be a tensile stress or a compressive stress. Further, the stress may be a longitudinal stress, a transverse stress or a shear stress with respect to the nanowire 112.

[0064] The nanowire 112 may include a semiconductor material such as e.g. single crystalline silicon, poly silicon, germanium and/or gallium arsenic, for example. The nanowire 112 may also be doped accordingly.

[0065] FIG. 3 A shows a schematic 302 of a test setup of the piezoresistive sensor 110 showing a nanowire 112 embedded next to an anchor 128 of a cantilever 114 and a mechanical stylus 120 contacting and deflecting the cantilever 114 according to an embodiment.

[0066] To investigate piezoresistive properties as a function of transverse electric field, silicon dioxide (SiO ₂ ) cantilevers 114 with embedded silicon NWs 112 above an electrically conductive substrate 124 similar to that as shown in FIG. 2 have been designed and fabricated as shown in FIG. 3 A. The electromechanical characterization of NWs 112 has always been a challenging task due to their small dimensions. The NWs 112 are typically measured in conjunction with direct force loading by an atomic force microscope (AFM) or indirectly by a bulge test or four-point bending. As long as the NWs 112 are naked with the surface unprotected, direct AFM contact or environment can modify their surface properties and thus influence the measurement. Embedding the nanowires 112 within the cantilever 114 may eliminate this. Specific stress profiles may be induced in the NWs 112 by poking the free-end portion 130 of the cantilever 114 with a nanoindentation stylus 120. This platform enables the possibility to measure the electrical conductance of the NWs 112 under controlled mechanical load while modulating the transverse electric field. [0067] The NWs 112 are fabricated using conventional integrated circuit technology with silicon-on-insulator (SOI) wafers as starting substrates as an example. Silicon NWs 112 oriented in the <110> direction with a width of 100 nm and a length of 5 μm are lithographically defined on 200 mm SOI wafers with 100 nm thick top silicon and 145 nm thick buried SiO ₂ . Once the silicon layer is patterned, the NW line width is trimmed by oxidation. Subsequently, the NWs 112 are doped by ion implantation Of BF ₂ ⁺ at 1 x 10 ¹² ion/cm ² . The silicon layer is covered with 0.5 μm thick SiO ₂ layer deposited by plasma-enhanced chemical vapor deposition (PECVD). Contact holes are opened, implanted with BF ₂ ⁺ at 1 x 10 ¹⁵ ion/cm ² to form non-rectifying contacts. After impurities activation by rapid thermal processing (RTP), an aluminum-silicon alloy layer (A14%Si) is sputtered, patterned, and sintered in a forming gas (5% H ₂ in N ₂ ) for about 20 min at about 450 ⁰ C to provide electrical connection between the NWs 112 and the bonding pads. Trenches with dimensions of about 18 μm deep and 1 μm wide are etched into the silicon layer or silicon substrate 124 to form mechanical stiffeners (not shown). A second layer of PECVD SiO ₂ is deposited to fill the trenches and provide a passivation of the aluminum- silicon alloy layer. Microcantilevers 114 of about 8 μm wide, 2.6 μm thick, and 80 μm long are defined with the NWs 112 located next to the anchor 128 of the cantilever 114. A pair of NWs 112 is located close to the bottom of the cantilever 114 (1.2 μm from the neutral axis of the cantilever 114), to maximize the stress amplitude on the NWs 112 or nanostructures. As a last step, the cantilevers 114 are released by removing the silicon substrate underneath by XeF ₂ vapor or any other suitable method.

[0068] FIG. 3B shows a scanning electron microscopy (SEM) image 304 of the released cantilever 114 according to an embodiment. The NWs 112 embedded within the cantilever 114 are sandwiched between a bottom 150 nm thick thermal SiO ₂ and a top 2.45 μm thick of PECVD SiO ₂ , which is responsible for the relief on the top of the cantilever 114. [0069] The insert as shown in FIG. 3 B shows a transmission electron microscope (TEM) image of a cross-section of a NW 112 and the dimension may be about 100 x 100 run ² .

[0070] FIG. 3C shows a distribution 306 of holes concentration in the nanowire 112 as a function of gate-source voltage (V _GS ) 122 according to an embodiment.

[0071] The nanowire 112 taken together with the conductive substrate 124 may resembled a MOSFET. Therefore, the two terminals of the NW 112 may be respectively termed as "source terminal 138" and "drain terminal 142", while the conductive substrate 124 may be called "gate terminal 136". Using the process simulator SUPREM FV and the device simulator Medici, it may be seen in FIG. 3C that the substrate (gate) voltage 122 may strongly influence the MOSFET device performance and can even fully deplete the entire silicon layer for a p-type <110> oriented NW 112. As shown in FIG. 3C, the gate voltage (V _G s) 122 varies from 0 V to 7.5 V in steps of 2.5 V (left to right), with OV on the source terminal 138 and 5V on the drain terminal 142 as simulated by MEDICI device simulator. These results demonstrated that V _GS 122 can deplete carriers within the NW 112 creating a pinch-off region 148.

[0072] As demonstrated by the distribution 306 of holes concentration in FIG. 3 C, the drain current along the NW 112 is determined by properties of a tiny pinch-off region 148 next to the source terminal 138 or source contact. The NW structure 112 can then be represented as two resistors in series, the "funnel" (pinch-off region) 148 and "bulk" 150. Small modulation of the funnel size (resistance) controls the current flowing through the NW 112. Illustratively, current flowing through this pinch-off region 148 is squeezed like a liquid passing through a funnel. The current amplitude in the NW 112 is then defined by the "size" of the funnel aperture, that is, properties of the pinch-off region 148. Modulating the carrier's concentration by stress in a pinch-off region 148 will have great influence on the total resistance of the piezoresistive sensor or NW device 110. [0073] FIGs. 4A to 4D shows respective measurements of drain current (IQ) as a function of stress with gate voltage or gate bias (VG _S ) 122 as a parameter according to an embodiment.

[0074] FIGs. 4A to 4D shows respective electrically controlled piezoresistance of p+ <110> oriented silicon NWs 112. FIG. 4A shows a plot 402 of IQ versus VQ _S . FIG. 4A shows a steady- state behavior of I _D as a function of VGS 122 from about -10 to about +5 V with tip displacement as parameter, keeping the drain-source voltage (V _DS ) 146 fixed at about 5 V. The unstressed NW 112 is indicated by line 410 and compressively stressed NW 112 by displacing the tip of the cantilever 114 are respectively indicated by 1 μm (line 412), 2 μm (line 414), and 3 μm (line 416). All experiments are conducted at about 24 ⁰ C in dark conditions. Real-time electromechanical measurements of I _D in the NWs 112 as a function of mechanical stress are carried out. The stress is controlled by lowering the PZT-held tip at about 250 nm/s for about 3 μm. The tip is then stopped for 20 s and disengaged at the same speed. Stylus displacement at 1 μm (squares), 2 μm (circles), and 3 μm (triangles) are indicated in FIGs. 4B to 4D.

[0075] FIGs. 4B and 4C shows respective plots 404, 406 of I ₀ versus time. FIGs. 4B and 4C respectively shows that unless the pinch-off region 148 is formed, the NW 112 has conventional piezoresistive properties resembling bulk, regardless of the substrate bias 122 applied, as shown for small relative I _D change for V _GS 122 of about -10 V in FIG. 4B and V _GS 122 of about -2 V n FIG. 4C.

[0076] FIG. 4D shows a plot 408 of I _D versus time. FIG. 4D shows that once the pinch-off region 148 is formed at V _GS 122 of about 4 V, the I _D changes by about 2 orders of magnitude revealing impressive piezoresistive properties of NWs 112.

[0077] The electrical response of the NW 112 under stress to the substrate bias 122 is affected by the air gap formed underneath the cantilever 114. For distances ranging from 0 μm (prior to release) to 50 μm, measurements confirmed that the voltage required to deplete the NW 112 is proportional to the air gap, as the substrate bias 122 is distributed between the air gap and the SiO ₂ in the reverse ratio of their capacitances. The drain current I _D across the NW 112 is measured as a function of the substrate bias or gate-source voltage (V _GS ) 122 with the tip of the cantilever 114 vertical displacement as a parameter as shown in FIG. 4A. This schematic applied a constant strain on the NWs 112 and allowed us to decouple the dynamic effects of the mechanical strain from the electrical measurements. Under compressive stress, the conductance across the NW 112 varies nonlinearly with the applied V _GS 122. I _D increased by about 2 orders of magnitude from about 4 pA to about 360 pA at V _GS 122 of about 4 V. Although highly depleted NWs 112 (I _D < 10 pA) exhibited hysteresis during the double sweep I _D versus V _GS 122 measurements, the hysteresis in the I _D of the NW 112 is only about 1.3 times.

[0078] Electromechanical responses of materials can be subjected to hysteresis or time lag. Real-time measurements of I _D as a function of stress with V _GS 122 as parameter do not reveal such behaviors. However, the application of V _GS 122 about -10 V as shown in FIG. 4B exposed an unexpected discrete step change (spiking) upon the initial contact between the probe tip and the cantilever 114. This step is sharp and can be considered as a discrete change as no displacement amplitude is able to stabilize the I _D between the baseline at the beginning of the experiment and the change observed after the contact.

[0079] The electromechanical response at V _GS 122 of about -2 V as shown in FIG. 4C resembled that of a typical bulk piezoresistor. Further, increase of VQ _S 122 to about 4 V as shown in FIG. 4D depleted the carriers in the NWs 112 resulting in a huge increase in I _D of about 2 orders of magnitude.

[0080] The piezoresistive properties of a material are usually characterized by their gauge factor (GF), which is the ratio of the normalized change of the electrical conductance of the material (Δσ/σ ₀ ) to the applied compressive stress (e). As V _DS 146 is fixed, the drain current I _D is proportional to the electrical conductance of the NW 112. The GF of the NW 112 can then be represented by :

GF = d/

L άs

Equation (4)

[0081] When the stylus deflects the tip of the cantilever 114, I _D changes with time, /o is the current selected at the origin of a linear electromechanical response. The gradient of the current I _D versus the time t as shown in FIGs. 4B to 4D is proportional to the ratio of d/to the change in the tip deflection of the cantilever 114 dδ where v is the poking speed of the stylus as shown below : d/ v d/

I ₀ at [ _Q dό

Equation (5)

[0082] The gradient with R-square greater than 0.9 is chosen for the analysis of the GF of the NW 112. The value R-square quantifies goodness of fit. It is a fraction between 0.0 and 1.0, and has no units. Higher values indicate that the model fits the data better. The induced mechanical strain in the NW 112 is determined from the cantilever beam deflection formula. The relationship between the tip deflection of a rectangular cantilever 114 to the average induced strain e∞Λn NWs 112 is given by

3(L - ?/2)cε _a<B

δ =

Equation (6)

where L is the length of the cantilever 114, / is the length of NW 112, and c is the vertical location of the NW 112 from its neutral axis. Derivation for eave as a function of δ is detailed below.

[0083] FIG. 5 shows a plot 500 of an extracted gauge factor as a function of gate voltage

(V _GS ) 122 according to an embodiment. [0084] For V _GS 122 from about -10 to about -3 V, the piezoresistive sensor or NW device 110 is in a piezoresistive state or behaves as conventional piezoresistor with GF of about 50. For V _GS 122 between about -3 and about 1 V, the NW device 110 is in an intermediate state, where the combination of piezoresistance and carrier depletion allows the I _D control and the GF increases to almost about 300. With further V _GS 122 increase above about IV, the NW device 110 is in a depleted state. Within the depleted state, any further increase in V _GS 122 resulted in a GF of up to about 5000 at about 3.75 V when the pinch-off region 148 has the strongest influence on the device behavior. At V _GS 122 above about 4 V, the NW structure 112 is fully depleted and only leakage current is detected decreasing the GF. Results from 8 pairs of NWs 112 are shown, where line 502 indicates mean, line 504 indicates median, inverting triangle indicated positive standard deviation, and triangle indicates negative standard deviation.

[0085] Therefore, from FIG. 5, it may be seen that the maximum GF of about 5400 is achieved at V _GS 122 of about 3.75 V corresponding to an increase of about 2 orders of magnitude. For higher V _GS 122, the NWs 112 are fully depleted, independent of the applied stress.

[0086] FIG. 6 shows a cross-section schematic of a piezoresistive sensor 110, the piezoresistive sensor 110 including a gate all around nanowire transistor (GAA NWFET) 152 with a nanowire channel body 112, a gate oxide layer 158 and a conductive surrounding gate 166 according to an embodiment.

[0087] For the GAA NWFET 152 type of piezoresistive element as shown in FIG. 6, a bias voltage is applied between the nanowire channel body 112 and the conductive surrounding gate 166 to thereby create a depletion region in the nanowire channel body 112; a stress applicator (not shown) configured to apply a stress onto the nanowire channel body 112 to modulate concentration and mobility of charge carriers (not shown) along the nanowire channel body 112; and the conductive surrounding gate 166 is configured to vary the electric field applied within the nanowire channel body 112 to thereby control giant piezoresistive coefficient or gauge factor of the nanowire channel body 112.

[0088] For the GAA NWFET 152, the conductive surrounding gate 166 may be configured to provide the electric field to the nanowire channel body 112 in more than one direction substantially perpendicular to a longitudinal extension of the nanowire channel body 112 (as shown). The conductive gate 166 may be configured to completely surround or substantially surround the nanowire channel body 112. The conductive gate 166 may include a material selected from a group consisting of silicon, polysilicon, metals, for example. There may be the gate oxide layer 158 positioned between the nanowire channel body 112 and the conductive gate 166.

[0089] The conductive gate 166 may form a gate terminal 136 of the GAA NWFET 152. Further, one end of the nanowire channel body 112 may form a source terminal (not shown) of the GAA NWFET 152 and a further end opposite to the one end of the nanowire channel body 112 may form a drain terminal (not shown) of the GAA NWFET 152.

[0090] FIG. 7 A shows a DRSEM image 700 of a piezoresistive sensor 110 after silicon nanowire formation according to an embodiment and FIG. 7B shows a DRSEM image 702 of the piezoresistive sensor 110 after gate patterning according to an embodiment.

[0091] FIG. 7A shows the SiNW 112 formed between the source region 174 and the drain region 176. FIG. 7B shows the SiNW (not shown) positioned between the source region 174 and the drain region 176 and being surrounded by a conductive gate layer 166. The piezoresistivity of the SiNW 112 may be controlled by the surrounded gate voltage and the formation of the depletion layer (not shown) within the SiNW 112 may be controlled with a low applied gate voltage. The temperature compensation for the variation of the gauge factor may also be nullified by adjusting the gate voltage. [0092] FIG. 8 A show a DRSEM image 1000 of a beam structure 162, wherein four nanowires (not clearly shown in FIG. 8A but as shown in FIG. 9A) are positioned in or on the beam structure 162 according to an embodiment. Respective exploded views of the boxed area showing two nanowires are as shown in FIGs. 9 A and 9B. In the boxed area, metal traces or metal contacts 172 respectively coupled to the two nanowires may be positioned at one of four beams 170 between a centre structure 156 with an outer circumference 168 and nearer to the outer circumference 168 such that any application of stress onto the centre structure 156 may translate into stress onto the two nanowires. The two nanowires may also be positioned at any one of the four beams 170. Further, other nanowires may also be positioned along any of the four beams 170 depending on user and design requirements.

[0093) FIG. 8B show a DRSEM image 1200 of a membrane 164, wherein the nanowire (not clearly shown in FIG. 8A but as shown in FIG. 9A) is positioned in or on the membrane 164 according to an embodiment.

[0094] The membrane 164 may be held by an anchoring structure 180 surrounding the membrane 164. The membrane 164 may include an elastic material or any suitable materials such that any application of stress onto the membrane 164 may be translated onto the nanowire.

[0095] Similar to FIG. 8A, respective exploded views of the boxed area in FIG. 8B showing the nanowire are as shown in FIGs. 9A and 9B. As shown in the boxed area in FIG. 8B, the nanowire is positioned at the tip of the metal trace 172. However, the nanowire may be positioned at any other suitable positions relative to the membrane 164. Further, the number of nanowire may vary depending on user and design requirements.

[0096] FIG. 9A show a DRSEM image 1100 of a nanowire resistor 154 according to an embodiment. As shown in FIG. 9A, the nanowire resistor 154 may include two nanowires 112. Each of the two nanowires 112 may be positioned between two metal contacts 172. The electric field is applied to the two nanowires 112 through a conductive substrate 124 which forms a gate terminal 136 of the nanowire resistor 154. With such a configuration, the electric field is applied onto the two nanowires 112 from only one direction.

[0097] The nanowire resistor 154 may be a type of transistor in which there may not be any junctions. The nanowire resistor 154 has full CMOS functionality and is made using silicon nanowires 112. The nanowire resistor 154 has near-ideal sub-threshold slope, extremely low leakage currents, and less degradation of mobility with gate voltage and temperature than classical transistors.

[0098] FIG. 9B show a DRSEM image 1102 of a nanowire transistor 152 according to an embodiment. The nanowire transistor 152 may include three regions, namely a source region 174, a drain region 176 and a gate region 178. The nanowire channel (not shown) may be formed between the source region 174 and the drain region 176. For the nanowire transistor 152, the electric field is applied through the gate region 178 formed by a surrounded gate layer 166. Therefore, the electric field is applied from more than one direction.

[0099] One difference between the nanowire resistor 154 as shown in FIG. 9A and the nanowire transistor 152 as shown in FIG. 9B is that the nanowire transistor 152 has the gate region or terminal 178 between the source region or terminal 174 and the drain region or terminal 176. The nanowire resistor 154 does not have this.

[00100] While the invention has been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.