Title:
PIPELINED DATA RELOCATION AND IMPROVED CHIP ARCHITECTURES
Document Type and Number:
WIPO Patent Application WO2005114670
Kind Code:
B1
Abstract:
The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improve are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.
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Inventors:
GOROBETS SERGEY ANATOLIEVICH (GB)
CONLEY KEVIN M (US)
CONLEY KEVIN M (US)
Application Number:
PCT/US2005/016341
Publication Date:
February 09, 2006
Filing Date:
May 09, 2005
Export Citation:
Assignee:
SANDISK CORP (US)
GOROBETS SERGEY ANATOLIEVICH (GB)
CONLEY KEVIN M (US)
GOROBETS SERGEY ANATOLIEVICH (GB)
CONLEY KEVIN M (US)
International Classes:
G06F3/00; G11C7/10; G11C16/34; G11C29/00; (IPC1-7): G11C7/10; G11C16/34
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