**PIPELINED FORWARD ERROR CORRECTION FOR VECTOR SIGNALING CODE CHANNEL**

CARNELLI, Dario (S.A.EPFL Innovation Park Building I, 1015 Lausanne, Lausanne, CH)

INVENTION MINE, LLC (216 South Jefferson Street, Suite 102Chicago, Illinois, 60661, US)

*;*

**H04B3/02***;*

**H04B17/364***;*

**H04L1/00***;*

**H04L25/03**

**H04L25/08**US20160211929A1 | 2016-07-21 | |||

US20090150754A1 | 2009-06-11 | |||

US8245107B2 | 2012-08-14 | |||

US20080016432A1 | 2008-01-17 | |||

US20140068391A1 | 2014-03-06 | |||

US20160197747A1 | 2016-07-07 | |||

US9059816B1 | 2015-06-16 | |||

US20120036415A1 | 2012-02-09 |

CLAIMS 1. A method comprising: decoding, using a vector signal code receiver, a predetermined number of sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires; generating, using a forward error correction (FEC) check circuit, an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix; and upon decoding of a final vector signaling codeword of the predetermined number of received vector signaling codewords, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values. 2. The method of claim 1 , wherein generating the incremental updates of the plurality of error correction syndrome values comprises performing a logical XOR operation on a previously-stored error correction syndrome value based on a given set of data bits of the sequential sets of data bits. 3. The method of claim 1 , wherein the plurality of error correction syndrome values are initialized to logic zero values, and wherein performing the final incremental update of the plurality of error correction syndrome values comprises comparing the plurality of error correction syndrome values to a plurality of received error correction check words. 4. The method of claim 1 , wherein the plurality of error correction syndrome values are initialized according to a plurality of received error correction check words prior to generating the incremental updates of the plurality of error correction syndrome values. 5. The method as in any of claims 1 -4, wherein the symbol position index is determined by forming a binary reciprocal of the first error correction syndrome value, and forming a modulo-reduced multiplication with a second error correction syndrome value of the plurality of error correction syndrome values. 6. The method of claim 5, wherein the binary reciprocal is formed using a lookup table (LUT). 7. The method as in any of claims 1 -4, wherein the first error correction syndrome value is updated by performing a logical XOR function on bits of the sequential sets of data bits sharing a common bit position. 8. The method as in any of claims 1 -4, wherein the selected set of data bits is altered by performing a bit-wise XOR of the selected set of data bits with the bit error mask to create a corrected set of data bits. 9. An apparatus comprising: a vector signal code receiver configured to decode a predetermined number of sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires; a forward error correction (FEC) check circuit configured to generate an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix; and an error correction circuit configured, in response to decoding of a final vector signaling codeword of the predetermined number of received vector signaling codewords and a final incremental update of the plurality of error correction syndrome values, to modify data bits within the sequential sets of data bits, the error correction circuit configured to select a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, and to alter the selected set of data bits according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values. 10. The apparatus of claim 9, wherein the FEC check circuit is configured to generate the incremental updates of the plurality of error correction syndrome values by performing a logical XOR operation on a previously-stored error correction syndrome value based on a given set of data bits of the sequential sets of data bits. 1 1. The apparatus of claim 9, wherein the plurality of error correction syndrome values are initialized to logic zero values, and wherein the final incremental update of the plurality of error correction syndrome values is performed by comparing the plurality of error correction syndrome values to a plurality of received error correction check words. 12. The apparatus of claim 9, wherein the plurality of error correction syndrome values are initialized according to a plurality of received error correction check words prior to the FEC check circuit generating the incremental updates of the plurality of error correction syndrome values. 13. The apparatus as in any of claims 9-12, wherein the error correction circuit is configured to determine the symbol position index by forming a binary reciprocal of the first error correction syndrome value and forming a modulo-reduced multiplication with a second error correction syndrome value of the plurality of error correction syndrome values. 14. The apparatus as in any of claims 9-12, wherein the FEC check circuit is configured to update the first error correction syndrome value by performing a logical XOR function on bits of the sequential sets of data bits sharing a common bit position. 15. The apparatus as in any of claims 9-12, wherein the error correction circuit is configured to alter the selected set of data bits by performing a bit-wise XOR of the selected set of data bits with the bit error mask to create a corrected set of data bits. |

FIELD OF THE INVENTION

[0001] Present embodiments relate to communications systems circuits generally, and more particularly to reduction of communication errors over a high-speed multi-wire interface used for chip-to-chip communication.

BACKGROUND

[0010] In modern digital systems, digital information is processed in a reliable and efficient way. In this context, digital information is to be understood as information available in discrete, i.e., discontinuous values. Bits, collection of bits, but also numbers from a finite set can be used to represent digital information.

[0011] In most chip-to-chip, or device-to-device communication systems, communication takes place over a plurality of wires to increase the aggregate bandwidth. A single or pair of these wires may be referred to as a channel or link and multiple channels create a communication bus between the electronic components. At the physical circuitry level, in chip-to-chip communication systems, buses are typically made of electrical conductors in the package between chips and motherboards, on printed circuit boards ("PCBs") boards or in cables and connectors between PCBs. In high frequency applications, microstrip or stripline PCB traces may be used.

[0012] Common methods for transmitting signals over bus wires include single-ended and differential signaling methods. In applications requiring high speed communications, those methods can be further optimized in terms of power consumption and pin-efficiency, especially in high-speed communications. More recently, vector signaling methods have been proposed to further optimize the tradeoffs between power consumption, pin efficiency and noise robustness of chip-to-chip communication systems. In such vector signaling systems, digital information at the transmitter is transformed into a different representation space in the form of a vector codeword that is chosen in order to optimize the power consumption, pin-efficiency and speed trade-offs based on the transmission channel properties and communication system design constraints. Herein, this process is referred to as "encoding". The encoded codeword is communicated as a group of signals from the transmitter to one or more receivers. At a receiver, the received signals corresponding to the codeword are transformed back into the original digital information representation space. Herein, this process is referred to as "decoding".

BRIEF DESCRIPTION

[0013] In conventional bit-serial communications systems, data words provided by a transmitting or source process are serialized into a sequential stream of bits, in one exemplary embodiment using a digital shift register. At the receiver, sequentially detected bits are deserialized using comparable means, so that a receiving or destination process may be presented with complete data words equivalent to those provided at the transmitter. Vector signaling code communication systems perform comparable operations, although in these embodiments the serialization process generally breaks words into symbol groups (e.g. into five bit elements for a CNRZ-5 system,) and the equivalent deserialization process assembles received groups (of five bits, continuing the same example,) into words again.

[0014] Forward Error Correction (FEC) methods have been developed which introduce redundancy into such transmitted data streams as part of a check code that both detects and facilitates correction of errors. In cases where the native communications link has relatively low uncorrected BER (e.g., 1 x 10 ^{-9 } to 1 x 10 ^{-10 }) and the target BER is of the order of 1 x 10 ^{-15 } to 1 x 10 ^{-20 }, a novel solution is described that can be computed at transmission during the serialization of emitted values, and can be verified during reception during deserialization, so that in the non-error case little or no additional latency is introduced into the communications path.

[0015] In some embodiments, a method includes decoding, using a vector signal code receiver, a predetermined number of sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating, using a FEC check circuit, an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword of the predetermined number of received vector signaling codewords, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

BRIEF DESCRIPTION OF FIGURES

[0016] FIG. 1 is a block diagram of a prior art communications system to transmit data S from a transmitter 110 over a set of 125 collectively comprising the communications medium 120 to a receiver 130 outputting received dataR .

[0017] FIG. 2 shows one embodiment of a transmitter incorporating the described Forward Error Correction in a data path utilizing multiple processing phases.

[0018] FIG. 3 shows one embodiment of a receiver incorporating the described Forward Error Correction in a data path utilizing multiple processing phases.

[0019] FIGs. 4A-4C are block diagrams for CRC word calculation, in accordance with some embodiments.

[0020] FIGs. 5A and 5B are block diagrams illustrating components of an error correction circuit, in accordance with some embodiments.

[0021] FIG. 6 is a block diagram for identifying an erroneous data word position, in accordance with some embodiments.

[0022] FIG. 7 is a flowchart of a method, in accordance with some embodiments.

[0023] FIG. 8 is a flowchart of a method of iteratively updating error correction syndrome values, in accordance with some embodiments.

DETAILED DESCRIPTION [0024] As described in [Cronie I], [Cronie II], and [Shokrollahi II], vector signaling codes may be used to produce extremely high bandwidth data communications links, such as between two integrated circuit devices in a system. As illustrated by the embodiment of FIG. 1, a data communications channel 120 composed of multiple wires 125 carries symbols of the vector signaling code, acting together to communicate codewords of the vector signaling code. Depending on the particular vector signaling code used, the number of channels including a communications link may range from two to eight or more, and may also communicate one or more clock signals on separate communications channels or as subchannel components of the vector signaling code. In the example of FIG. 1, communication link 120 is illustrated as being composed of eight wires 125, collectively communicating five data values 100 and one clock 105 between transmitter 1 10 and receiver 130. Further descriptions of such communications links are provided in [Shokrollahi II].

[0025] Individual symbols, e.g. transmissions on any single communications channel, may utilize multiple signal levels, often three or more. Operation at channel rates exceeding 10 Gbps may further complicate receive behavior by requiring deeply pipelined or parallelized signal processing. Embodiments described herein may also be applied to prior art permutation sorting methods not covered by the vector processing methods of [Shokrollahi II]. More generally, embodiments may apply to any communication or storage methods requiring coordination of multiple channels or elements of the channel to produce a coherent aggregate result.

[0026] Due to the characteristic of transmitting multiple symbols essentially in parallel, vector signaling codes are generally considered as communicating data in symbol groups, for example in five-bit increments for the CNRZ-5 code (also known as Glasswing Code) of [Shokrollahi II]. Thus, this document may subsequently describe transport as occurring in increments of K * n bits, where n is that code's symbol group or payload size. That reference additionally notes, however, that the encoded subchannels transporting individual bits are mathematically distinct, and in certain embodiments may be treated as independent transport channels.

Serialization and Deserialization

[0027] In conventional bit-serial communications systems, data words provided by a transmitting or source process are serialized into a sequential stream of bits, in one exemplary embodiment using a digital shift register. At the receiver, sequentially detected bits are deserialized using comparable means, so that a receiving or destination process may be presented with complete data words equivalent to those provided at the transmitter. Vector signaling code communication systems perform comparable operations, although in these embodiments the serialization process generally breaks words into symbol groups (e.g. into five bit elements for a CNRZ-5 system,) and the equivalent deserialization process assembles received groups (of five bits, continuing the same example,) into words again.

[0028] As is readily apparent, serialization and deserialization introduce latency into the communication channel, with the amount of latency dependent on the number of transmitted elements into which a given data word is serialized, as the entire word is not available until its last-transmitted element has been received and the received word fully reassembled.

[0029] In some high-speed communications systems, serialization and deserialization may additionally incorporate multiple processing phases operating essentially in parallel, to provide additional processing time within each phase and/or to permit processing operation using a lower clock rate to reduce power consumption. In one representative embodiment, data words presented by the transmission or source process are broken into words, with consecutive words being assigned to sequentially chosen processing phases which perform the necessary encoding, formatting, etc. As each processing phase completes its operations, the processed results are transferred to an output driver for transmission over the communications medium. Thus, in the case where four processing phases are used, each phase will have approximately four transmit unit intervals of time to perform the necessary operations. Similar multiphase processing may occur at the receiver; consecutively received words being detected by sequentially assigned processing phases and reassembled into output words.

[0030] Embodiments incorporating multiple processing phases are used herein as descriptive examples, so as to provide the broadest and most complete illustration of features and behaviors. Other embodiments may utilize fewer or more processing phases, including a single instance, and may incorporate greater or lesser amount of transmit and/or receive processing into the essentially parallel processing phases, with no limitation implied by these examples. Link Error Correction

[0031] Communications system designs emphasize error-free transport of data, despite the inevitable presence of noise and other signal disruptions. Error probabilities over the communications path are expressed as a Bit Error Rate (BER), representing the ratio of bit errors received to overall bits transmitted.

[0032] Solutions to detect bit errors, including cyclic check codes, parity, and redundant transmission, are known in the art. Similarly, solutions are known for correction of errors, most notably the closed-loop retransmission methods of the TCP/IP protocol suite, in which a receiver detects an error, uses a return channel to request a retransmission by the transmitter, and then transparently inserts the corrected data into its output stream. Further, the term of art "cyclic redundancy check (CRC)" is used herein to describe any set of computed bits augmenting a data stream to enable error identification and correction.

Forward Error Correction

[0033] Where use of a return channel is impossible or the round-trip latency of waiting for a retransmission is unacceptable, Forward Error Correction (FEC) methods have been developed which introduce redundancy into the transmitted data stream as part of a check code that both detects and facilitates correction of errors. The more redundancy introduced into the transmitted data stream (e.g. by use of a longer FEC sequence,) the greater the ability of the FEC to correct bit errors, but also the greater the protocol overhead, presenting itself as a lower effective data transmission rate.

[0034] As noted in [Bhoja et al], several FEC techniques have been proposed for use over high speed communications links, including the KR4 and KP4 codes as defined for 802.3bj, as well as BCH codes, for example of length 2864 and dimension 2570. Further examples include the Reed-Solomon codes described in [Shokrollahi I] and the Hamming, Hadamard, Reed-Muller, Golay, and Low-Density Parity Check (LDPC) codes of [Cronie II]. These error correction methods target communications links with relatively high uncorrected BER (on the order of l x l0 ^{-5 } to l x l0 ^{-3 } ) while delivering corrected error rates on the order of 1 x 10 ^{-15 }, thus they rely on computing a relatively long check sequence over a large block of data. The resulting error correction latencies are on the order of many tens of nano-seconds (e.g. 100 ns, as reported by [Bhoja et al.]) with correspondingly large computational power consumption.

[0035] In cases where the native communications link has relatively low uncorrected BER (e.g., 1 x 10 ^{-9 } to 1 x 10 ^{- 10 }) and the target BER is of the order of 1 x 10 ^{-15 } to 1 x 10 ^{-20 }, other solutions can be found with much lower latency. This is the case, for example, for in-package die-to-die links that use vector signaling codes, such as the Glasswing or CNRZ-5 code of [Shokrollahi II].

[0036] For vector signaling codes transmitting n bits at a time over m wires, it is advantageous to work with an FEC operating in the Galois field GF(2") since an error in the communication link is likely to cause errors on all n bits.

Pipelining Error Correction processing

[0037] One embodiment of a link-optimized Forward Error Correction uses sequential data word transmission by the transport level vector signaling code to minimize perceived error correction latency. In such an embodiment, a vector signaling code transport communicates groups of n bits over m wires. Transmission of N consecutive groups thus transfers N * n bits, consisting of K * n data bits and R * n CRC bits for error correction. At the transmitter, a data source provides the K * n data bits, typically as multiple transfers over a wide parallel interface, with a similar interface delivering the received K * n data bits to a data sink at the receiver.

[0038] As a specific example offered without implying limitation, we consider n = 5 and m = 6 for a CNRZ-5 transport and N = 32 a typical message length. This may equivalently be interpreted as 5 simultaneous streams each transmitting 32 consecutive bits. A Forward Error Correction code over GF(2") operating on 5 -bit words will be capable of correcting one bit error. If p is the input BER, and assuming random and independent errors on every stream from UI to UI (but not independent among the 5 bits making up the word in every UI), then the output BER after decoding is at most where q = 1— (1— p) ^{5 }, andN = 32. To achieve an output BER of 1 x 10 ^{-15 }, an input BER p of 8 x 10 ^{-10 } is sufficient. The rate of this code is 15/16 = 93.75%, hence the rate loss is 6.25%. In such embodiments, at 26.66 Gbaud, the interface may transmit 5 * 26.66 * 0.9375 = 125 Gbps of data over 6 wires.

Transmission with FEC

[0039] At the transmitter, this embodiment performs the following operations:

[0040] The 5 bits to be transmitted at each Unit Interval (UI) are treated as elements of the field GF(32). For example, If n0, nl, n2, n3, n4 denote the 5 bits, wherein n0 is the lowest significant bit of n and n4 is the highest significant bit, then n corresponds to the element n0 + nl * x + n2 * x ^{2 } + n3 * x ^{3 } + n4 * x ^{4 } mod f(x) (Eqn. 2) and f(x) is the polynomial x ^{5 }+x ^{3 }+l

[0041] A check matrix of elements of GF(32) with 2 rows and 30 columns is used. In one embodiment, the elements in column j of this matrix are 1 and a _{j }, where the element a _{j } of GF(32) is the binary expansion of an integer j, that is, a _{j } is represented as the binary vector [j0 j l j2 j3 j4], where j0 + 2*j l + 4*j2 + 8*j3 + 16*j4 = While other embodiments may use alternate check matrices, use of the check matrix using the binary expansion of the integer j as the second row of elements results in efficiencies in calculating the error position vector that identifies which received symbol contains the error(s). In particular, this obviates the need to use the Berlekamp Massey algorithm (including the associated Chien search). In addition, directly calculating the bit error mask using the row of Γ s in the check matrix obviates the need to use Forney' s formula to determine the error magnitude. Equation 3 for calculating r0 and r\ using the check matrix described above is given below:

[0042] In equation 3, the check matrix including two rows of constants (one row of all l 's and one row of 00-029) is modulo-multiplied by a vector including the 30 data symbols m0-m29 to generate the CRC words r0 and r\ . [0043] If the incoming 30 5-bit data words (the bits of which will be communicated essentially simultaneously on the 5 CNRZ-5 sub-channels) are denoted by mO, ml , m29, then the two CRC 5 -bit words, denoted r0 and rl, are obtained as

denotes the multiplication of a and b in the field GF(32) and denotes the bit-wise XOR operation. Thus, rl may be generated by incrementally updating the previously stored value of rl in the jth unit interval by providing a bit- wise XOR of the previously stored value of rl with the modulo-multiplied result of aj ^{■ } mj, and the final value of rl is generated upon the final incremental update.

[0044] The message data m0, ml, ... m29 corresponds to 5-bit words at time instance 0, 1, ... , 29; therefore, the computation of CRC words r0, rl can be done incrementally, as the data becomes available. The computation is equivalent to

[0045] FIG. 4A includes a schematic for calculating values of r0, in accordance with some embodiments. As shown, a given value of rO is updated by XORing 403 the previously stored value 402 of r0 with a corresponding bit in an associated position of data word mj. For example, r0[0] may be XOR'd with mj[0], r0[l] may be XOR'd with mj[\], etc. Thus for index Such an embodiment may operate recursively, e.g. when each bit mj[i] becomes available. In such an embodiment, each data bit mj[i] may be provided via a shift register, for example. Alternatively the computation may be performed all at once when all of the data words are available, using a logical XOR tree shown in FIG. 4B for example.

[0046] As described above, calculating rl includes modulo-reduced multiplication of a a _{j } element from the GF(32) matrix with a corresponding data word mj, and XORing the results together. In some embodiments, an FEC encoder may form an XOR tree 404 as shown in FIG. 4B. Such an XOR tree may be formed using a known logic combination, such as the combinations for calculating r0 and rl given in Appendix A. Such an embodiment may obtain all the data bits (150 in the above examples) prior to performing the calculation using an XOR tree. FIG. 4B illustrates one particular example for calculating rl [0]. In such an embodiment, the inputs 405 may be predetermined, and selected according to the bits used to update rl [0] according to Appendix A.

[0047] FIG. 4C is a schematic of an alternative logic circuit for incrementally updating a given bit r 1 [0] as part of CRC word r\ , in accordance with some embodiments. In the schematic of FIG. 4C, the values of r\ may be incrementally updated according to CRC calculations corresponding to a modulo -multiplications of a set of data bits of a given symbol with a symbol index from the check matrix. In such an embodiment, the updating may be performed as the bits from each set of data bits of symbols m0-m29 becomes available, thus reducing latency. As shown, FIG. 4C includes a storage element 407 holding a current value of rl [0]. The current value rl [0] is XOR'd 410 with a sequence of the K*n data bits determined by the CRC calculation, the zth bit of the FEC data bits denoted as inp[z]. The notational sequence inp[z] represents the input data being processed, where inp[0..4] are the 5 bits of data word mO, inp[5..9] are the 5 bits of data word ml, ... ., inp[145..149] are the 5 bits of symbol m29 using the above embodiment having K=30 sets of n=5 data bits.

[0048] The current value r\ [0] may not be updated for every bit of the K*n data bits, thus an associated enable signal EN is used to selectively update the current value of r\ [0] according to a predetermined set of bits (See Appendix A). As shown, the K*n data bits are serially input into the XOR 410 using a shift register 415, which may obtain the bits from data buffer 210 in the transmitter, in some embodiments (not shown).

[0049] In receiver embodiments calculating r\ ', shift register 415 may be connected to processing phases 330, as shown in FIG. 4C. Alternatively, each phase may have a corresponding shift register, all of which may be multiplexed (not shown). In some embodiments, shift register 415 may be parallel loaded. In such embodiments, shift register 415 may include a plurality of D Flip-Flops that may be loaded in parallel, and serially shifted out to XOR 410. Block 417 illustrates one storage element of shift register 415, in accordance with some embodiments. As shown, storage element 417 is connected to the outputs of MIC0 of each of the four processing phases 330, denoted here as p0[0]-p3[0]. Further, a phase selection signal denoted 'phase_sel' is used to select which phase to load the storage element 417 with. In some embodiments, the selected phase may be provided to the block via a multiplexor accepting the phases, and the select signal may take the form of a two-bit clock counter to select which phase loads the register (not shown). While storage element 417 receives outputs from MIC0 of each processing phase, each other storage element of the shift register 415 may similarly receive a corresponding MIC output of the plurality of processing phases. For example, storage element 419 may receive the output of MIC 1 of each processing phase.

[0050] FIG. 4C further includes a counting circuit used to generate partial enable signals, including partial enable signals 4, 5, and 7, which may then be combined to form a corresponding global enable signal EN for bit rl [0]. As shown, the counting circuit includes a counter 420 and a plurality of AND logic gates 422a, 422b, and 422c. In some embodiments, the counter is configured to count from i = 0 to i = K*n - 1, i being an index associated with a corresponding data bit inp[z] of the K*n data bits. The output of the current value i of the counter 420 may be represented as a set of bits (shown as Χ,Υ,Ζ in FIG. 4C). AND logic gates 422a-c receive bits Χ,Υ,Ζ, each AND gate 422a-c having a corresponding combination of inverting and non-inverting inputs such that for each count value i, only one of the partial enable signals is logic Ί ' at a given count value, and all the rest are logic 'Ο'. In some embodiments, a respective global enable signal EN for each bit of the CRC words rl is formed by OR'ing 425 the partial enable signals associated with the indices i of the bits in the predetermined set of known bits. In the illustrative example of FIG. 4C, rl [0] is only updated using bits inp[4] and inp[7]. Thus, the global enable EN is formed by OR'ing partial enables 4 and 7, and rl [0] is updated when count i = 4 and 7, using bits inp[4] and inp[7], respectively. For illustrative purposes only, counter 420 only shows 3 bits Χ,Υ,Ζ forming a binary count value i, however it should be noted counter 420 may include any number of bits. For example, in the examples given above and in Appendix A, the counter may form count values i having 8 bits to count from i = 0 to i = 149 (resetting at z=149), to update the bits of CRC word rl .

[0051] The embodiments illustrated by FIGs. 4A-4C are just some examples of a logic circuit that may be hardwired to implement the calculation of each bit of the CRC words r0 and rl. There may be various other logic designs to perform such a calculation. For example, alternative embodiments may utilize a processor running a software application to calculate the variables.

[0052] Once the incoming data is processed completely CRC words r0 and rl are transmitted as the last two words, herein identified as m30 and m3\ . In an alternative embodiment, the transmitter may first calculate r0 and rl based on the available buffered transmit data and transmit the five bits of r0 and the five bits of rl using the first and second vector signaling codewords. In this embodiment, the decoder may then advantageously initialize the decoding circuit (FEC check circuit used to calculate syndrome values) using those two check values.

[0053] Since the elements α0, αΐ, ... , a29 are known in advance, whereas m0, ml, ... , m29 are variable, each of the multiplications in GF(32) can be done through a sequence of XOR operations on the 5 bits. This is done via a "regular representation of the field GF(32)" as is known to those of skill in the art. In this representation, each of the elements α0, αΐ, ... , a29 is represented as a 5x5 matrix of bits, and the multiplication a[j] · m[j] then corresponds to the multiplication of this matrix with the vector representing m\j].

[0054] One embodiment of a sequence of such operations is provided in Appendix A for a particular regular representation of GF(32), without implying limitation. Many other representations can also be used which would lead to similar results.

[0055] The computations at the transmitter are preferably done concurrently with the serialization step; that is, as each incremental data group becomes available and is prepared for transmissioa This "pipelining" of the FEC computation avoids the additional latency that is often encountered when using forward error correction techniques. In embodiments utilizing multiple essentially parallel processing phases in the transmission process, elements of the computation of r0, rl can be done within each processing phase. In some embodiments, at least one such processing phase incorporates XOR logic to facilitate at least a portion of such computation.

[0056] FIG. 2 illustrates one embodiment of a transmitter using the CNRZ-5 code of [Shokrollahi II.] Transmit Data is accepted into Data Buffer 210; typically, the source of this data will preferentially transfer data as words of, as examples offered without limitation, 16, 32, or 64 bits. Data Buffer 210 accepts these input word transfers, and outputs symbols mO. m1, ... m29 corresponding to sets of data bits (in this example, each symbol corresponding a set of five data bits) with successive symbol distributed 215 to processing phases phase0, phasel , phase2, phase3, and so on in a circular sequence over all processing phases 220. Within each processing phase 220, the previously described FEC computation 221 is performed on each set of five data bits, as they are simultaneously CNRZ-5 Encoded 222. Under control of Clock Generator 250, each processing phase produces a result that is selected by multiplexor 230, with the output symbols 235 presented to Line Driver 240 to be emitted over the communications channel comprised of wires Wo - W7. As described in [Shokrollahi II], Tx Clock 255 is also produced by Clock Generator 250 and emitted by Line Drivers 240 as part of the transmitted output on wires W6 and W7 in the example of FIG. 2.

[0057] The multiple instances of FEC computation 221 may access a common set of registers or storage elements to update CRC words r0, rl during processing of the first 30 output words utilizing data obtained from Data Buffer 210, following which a FEC processing element in a processing phase will output r0 as the 31 ^{st } output word to be encoded by encoder 222, and a FEC processing element in the next selected processing phase will output rl as the 32 ^{nd } output word to be encoded by vector signal encoder 222.

Reception and Error Correction

[0058] At the receiver, a compatible embodiment performs a similar set of CRC computations. 32 5 -bit words are received one after another, with the first 5 -bit word, called mO arriving at time 0, and the 32 ^{nd } 5 -bit word, called m3\ , arriving at time (UI * 31), where UI is the transport's unit interval for symbol transmission. In such an embodiment, local CRC words r0' and rl ' are generated, and error correction syndrome values r0" and rl " are finalized by comparing local CRC words r0' and rl ' to received CRC words r0 and rl . Alternatively, FEC check circuit 332 may be initialized by receiving CRC words r0 and rlfrom the transmitter first, and incrementally updating the plurality of error correction syndrome values initialized by received CRC words r0 and rl according to the sequential sets of data bits. [0059] In a first step of receive error correction, the operations in Appendix A are executed, preferably concurrent with the deserialization step for the first 30 data words, to incrementally calculate values for local CRC words r0' and rl '. As with the transmitter, each of these incremental calculations is performed using only the 5 bit word value received and the values being incrementally computed. As described for the transmitter, one embodiment incorporates XOR logic to perform at least part of this computation in at least one of multiple receive processing phases. In some embodiments, similar circuits as shown in FIGs. 4A-4C may be used to calculate the values of r0' and rl '. In some embodiments, local CRC words r0' and rl ' may be calculated as bits from the data words m0-m29 become available, while alternative embodiments may calculate r0' and rl ' once all of the data words have been received.

[0060] Once the first 30 received sets of data bits are processed to incrementally update a plurality of error correction syndrome values, preferably during the deserialization step, r0' is XOR'd with the received CRC word m30 (r0) and rl ' is XOR'd with the received CRC word m3l (rl) to generate error correction syndrome values r0" and rl ", respectively.. For the purposes of description, r0" and rl" may be referred to both as error correction syndrome values (upon the final incremental update), as well as syndrome words At this point, r0" and rl" contain the so-called "syndromes" of the forward error correcting code. If either r0" or rl " is zero, then there has been no error among the transmitted sets of data bits mO, m29, and no further processing is necessary. It is possible that there could have been an error among these words that was not caught by the incremental updates of the error correction syndrome values, but the frequency of such undetected errors is within the corrected BER as calculated above. At least one embodiment utilizes multiple receive processing phases, each receive processing phase incorporating logic configured to perform at least a portion of the operations in Appendix A or their logical equivalent, and configured to perform the described XOR operations to obtain the FEC syndromes.

[0061] In some embodiments, the plurality of error correction syndrome values of the FEC circuit at the receiver may be initialized by receiving CRC words r0 and rl from the transmitter in the first two unit intervals, and thus r0" and rl" can be calculated directly due to the incremental updates based on the obtained sequential sets of data bits. In some embodiments, the FEC check circuit may perform bit-wise iterative calculations in the circuit, as shown in FIG. 4C, however, alternative embodiments may implement predetermined combinatorial logic circuits based on logical expressions, e.g., those listed in Appendix A, to update the error correction syndrome values using one or more of the set of decoded data bits. Such a circuit may be similar to the combinatorial logic circuit of FIG. 4B, however as not all the data bits may not be available to the receiver at one time, the combinatorial logic circuit may be hardcoded to update the error correction syndrome values using bits selected according to the index of the current received set of data bits in the current received symbol. For example, error correction syndrome value rl [l] may be updated using one bit of symbol mO (inp[l] of Appendix A), and then rl [l] may subsequently be updated using three bits of symbol ml (inp[5], inp[6], and inp[7]). A control logic may be hardcoded according to Appendix A to provide such incremental updates. Alternatively, a control logic may be coded to implement binary modulo arithmetic according to the algorithm for calculating rl described in the pseudocode above.

[0062] If both error correction syndrome values r0" and rl " are non-zero, the received data bits are corrected for errors; r0" is the 5 -bit error mask, and the symbol position index of the symbol containing the error is determined by the vector rl'Vr0", where division is interpreted in the field GF(32). The error correction operations of computing the error index rl "/r0" and the XOR of the error mask onto the word mt may occur after the deserialization step. Here symbol position index t =pos-\ , where pos is the integer representation of rl 'Vr0". In one embodiment offered as an example without implying limitation after pos = rl 'Vr0" is computed, a barrel shifter performs a bit-wise XOR function by applying the bit error mask r0" to values of the selected set of data bits mt.

[0063] More precisely, the decoding can be described by the following pseudo-code:

IF r0"≠ 0 AND r 1 "≠ 0 THEN

Compute x[0],... ,x[4] via the procedure in Appendix B

Set pos = x[0] + 2x[l] + 4x[2] + 8x[3] + 16x[4]

Set t =pos-\

Set mt[0] := mt[0] r0"[0]

[0064] As stated above, rl " is divided by r0" in order to obtain the symbol position index (represented in the following equation 4 as b):

[0065] FIG. 5 A is a block diagram of one embodiment of an error correction circuit 560 connected to FEC check circuit 510, in accordance with some embodiments. In some embodiments, error correction circuit 560 may correspond to error correction 360 shown in FIG> 3. As shown, FEC check circuit 510 sequentially obtains the 150 data bits from the thirty decoded 5 -bit data words, and 10 bits making up the received CRC words r0, and rl . The FEC check circuit 510 generates incremental updates to a plurality of error correction syndrome values. In some embodiments, error correction syndrome values in the FEC check circuit are initialized to be quiescent (all zeroes), and the FEC check circuit generates local CRC words r0', rl ' based on the received data bits, and in the final incremental update, the FEC check circuit XORs r00r0' and rl 0 rl ' to generate error correction syndrome values r0" and rl", respectively. Alternatively, as previously described, the CRC words r0 and rl may be received from the transmitter in the first unit intervals, and the error correction syndrome values may be initialized with the received CRC words. The FEC check circuit 510 may then subsequently generate incremental updates to the error correction syndrome values, and upon the final incremental update, the error correction syndrome values r0" and rl" are complete without the need to perform the additional XOR step of the previous embodiment. In some embodiments, the FEC check circuit 510 may operate similarly to the CRC word generators shown in FIGs. 4A-4C, with the added functionality of generating the error correction syndrome values r0" and r 1 ". Then, the error correction circuit 560 may use the completed error correction syndrome values to identify if an error is present. As mentioned above, if either r0" or rl" are 0, then no error correction is performed by the error correction circuit. If error mask r0" is "00000", then an XOR of the selected symbol is unchanged, while rl" being "00000" indicates the error is in the received CRC words r0 or rl, and thus the correction circuit may disregard this scenario, and there is no correction of the data bits. If both of the error correction syndrome values r0" and rl" are non-zero, the location of the set of data bits of the symbol containing the error is determined by performing the above-mentioned rl 'Vr0" to identify a 5 bit symbol position index x[0]-x[4] used to identify the symbol position containing the error. In FIG. 5A rl'Vr0" is performed by calculating by finding

the bit-representation of the reciprocal of r0". In some embodiments, the conversion 520 may be done using a lookup table. Following this conversion, rl" may be multiplied 525 by— using modulo reduction techniques to find the symbol position index x[0]-x[4] of the erroneous data word. As described above, the decimal representation of symbol position index x[0]-x[4] may be referred to below as pos, and continuing the above example, \<pos<30.

[0066] The bits x[0]-x[4] of the symbol position index, the bit error mask r0", and the sequential sets of data bits of the received data may be provided to a set of registers 565 to provide the error correction by altering a selected set of data bits. FIG. 5B illustrates a set of registers 565, in accordance with some embodiments. As shown, registers 565 include a first register 530 holding the sequential sets of data bits corresponding to received data. A second register 535 contains the bit error mask r0" used to correct a set of data bits of the received data in a position determined by the bits x[0]-x[4] of the symbol position index, and the rest of the second register 535 includes logic zero values so as to not alter any other bits of the received data The first and second registers may be element- wise XOR'd in order to produce a corrected set of data in a third register 540, which may then be output from the system. In the example of FIG. 5B, the symbol position index identifies that the set of data bits corresponding to symbol m\4 need to be corrected, and the received set of bits corresponding to symbol m\4 are XOR'd with the bit error mask corresponding to error correction syndrome value r0".

[0067] As described above, a LUT may be implemented to find the reciprocal of r0". An example LUT performing such a function is given in Appendix C. Once the reciprocal of r0" is obtained, it can be multiplied by rl" to obtain the values of x[0]- x[4] discussed above. The following logical circuit-based operation may perform such a multiplication, in some embodiments, where inv_r0" is the reciprocal (or multiplicative inverse) of r0" obtained using the LUT of Appendix C, the "&" symbol represents a logical AND, and the "0" symbol represents the logical XOR:

[0068] The above computation and the associated LUT describe only one possible embodiment of the error correction circuit, and many alternative logic functions performing equivalently the same functions may be used. In some embodiments of the error correction circuit, the above may be implemented through the use of a physical logic circuit, while alternative embodiments may perform the calculations using software running on a processor.

[0069] Once the error correction circuit obtains the location pos-l of the erroneous data word and the bit error mask r0", the error correction circuit aligns the error mask with the correct symbol in the received data 530, using e.g., registers, and perform an XOR operation. FIG. 5B illustrates a correction of symbol m\4. As shown, the bit error mask r0" may be loaded into a location of a correction register 535, the location determined by a symbol position index associated with symbol ml 4. In at least one embodiment, the starting bit of the selected set of data bits corresponding to the erroneous data word may be the length of each received data word '« ' times the symbol position index (pos - 1). Lastly, a data register 530 containing the 150 bits of received data and the correction register 535 including the bit error mask r0" and the rest logic zero values may be XOR'd together to obtain a set of corrected data bits 540, which may then be output from the system.

[0070] FIG. 6 illustrates one particular example of a logic circuit for implementing division block 515 of error correction circuit 560. As shown, the logic circuit is configured to calculate a portion x[k] of the symbol position index pos of the erroneous data word in accordance with some embodiments. As shown, FIG. 6 includes storage element 605 holding a current value, shown as x[0] in this example. The value x[0] is updated by XOR'ing 610 the current value of x[0] with a selected combination of bits of the error correction syndrome values r0" and rl". In some embodiments, the process is hard-coded using a multiplexor 615 connected to an AND gate network 620, and a selection signal (a simple count for example) incrementally selects a combination of bits of error correction syndrome values r0" and rl". In at least one embodiment, the sequence of logic combinations provided to the XOR gate 610 selected by the select signal to update x[0] may be pre-determined according to the incremental process of Appendix B. Further, a similar logic circuit may implement respective predetermined updating sequences for the other bits of index x[k] The logic circuit of FIG. 6 is simply one example of how a given bit of x[k] may be generated, there may be alternative circuit implementations that accomplish the same goal. Alternatively, a processor may run a software algorithm to implement the process of Appendix B.

[0071] Because some of the error correction processing occurs outside of deserialization, it is desirable to reduce the total delay caused by these operations as much as possible to minimize the impact on perceived latency. Such design optimization may be addressed using known art design automation tools. However, it may be beneficial to furnish such a tool with a good starting point for the search of a representation that minimizes the logic depth of the computation, and one suitable embodiment is given in Appendix B. Without further optimization, the logic depth of that embodiment is at most 7. Embodiments described above may be useful in correcting errors caused by bursts of energy hitting the wires of the multi-wire bus. For example, if a burst of electromagnetic energy hits one or more wires on the multi-wire bus, it could introduce one or more errors into bits of a decoded data word. These errors may be identified by a bit error mask at the output, the bit error mask used to correct the one or more bit errors in a selected erroneous data word identified by so-called error correction syndrome values.

[0072] FIG. 3 illustrates a typical CNRZ-5 vector signal code receiver embodiment utilizing Multi-Input Comparators 320 to detect five data results MIC0 - MIC 4 and one received clock CK. Wire signals Wo - W5 are equalized by Continuous Time Linear Equalizer (CTLE) 310, and presented to the set of MICs 320 described by [Shokrollahi II], producing the detected data values MIC0 - MIC4. Furthermore, wires We and W7 may also be equalized by CTLE 310 (not shown) As shown in FIG. 3, the set of MICs 320 includes five comparator circuits, each MIC corresponding to a linear amplifier circuit performing a linear combination of wire signals present on wires W0- W5 only, the wire signals corresponding to symbols of a vector signaling codeword of a vector signaling code. As described in [Shokrollahi II], each MIC may perform a respective linear combination defined by a respective sub-channel of a plurality of mutually orthogonal sub-channels, that may be defined by a receiver matrix. In FIG. 3 wires We and W7 are wires dedicated to carrying a differential clock signal, and differential comparator 340 operates on wires We and W7 to generate the received clock signal CK. Other embodiments may forego using dedicated wires We and W7 to carry a differential clock signal and may transmit a clock using a dedicated sub-channel of the aforementioned mutually orthogonal sub-channels, e.g., as output MIC4. Alternatively, a clock signal may be extracted using transition information from the detected data outputs MIC0-MIC4 (i.e., data-derived clock recovery).

[0073] The detected data values MIC0 - MIC4 are presented to four processing phases 330, each of which processes the received data for one unit interval, and the received clock CK is presented to Clock Recovery 390, which in turn produces generates four sequential clock phases ph000, ph090, phi 80, ph270 that collectively coordinates operation of processing phases 330. Within each processing phase, comparator outputs MIC0 - MIC4 are Sampled 331 at the time determined by that phase's clock, producing sequential sets of five- bit words m0-m29 and received CRC words (r0 and rl) which are presented to Buffer 370. The receiver of FIG. 3 also includes an FEC check circuit 332 configured to incrementally update a plurality of error correction syndrome values based on each sequential set of data bits. In some embodiments, the plurality of error correction syndrome values are initialized to logic zero values, and FEC check circuit generates a set of n-bit local CRC words rO ',rV based on the received sequential sets of data bits, and forms n-bit error correction syndrome values (r0" and rl") upon decoding of a final vector signaling codeword by forming a comparison of the local CRC words r0', rl ' to the received CRC words r0, rl. The error correction syndrome values r0" and rl" identify if an error is present. In alternative embodiments, the transmitter may transmit CRC words r0 and rl first to initialize the plurality of error correction syndrome values and may subsequently transmit the plurality of sets of data bits. In such an embodiment, upon the decoding of the final vector signaling codeword, the plurality of error correction syndrome values r0" and rl " are complete, and thus the final comparison step may be omitted. As in the transmitter, receiver Buffer 370 accepts five bit received data values from processing phases 330 and assembles them into data words Receive Data Out. The receiver further includes an Error Correction circuit 360 configured to alter bits received in error within buffer 370 as described by the error correction algorithm of Appendix B. In some embodiments, in response to there being an error present, Error Correction circuit 360 generates a corrected set of data bits by correcting one or more errors in a selected set of data bits associated with a symbol position index determined from the plurality of error correction syndrome values, the one or more errors corrected using a bit error mask determined from a first error correction syndrome value r0".

[0074] FIG. 7 is a flowchart of a method 700, in accordance with some embodiments. As shown, method 700 includes receiving, at step 702, a sequence of codewords having m symbols, and responsively forming a plurality of sets of n comparator outputs at step 704, wherein n is an integer greater than or equal to 3. At step 706, the comparator outputs are sampled, and a plurality of n-bit words are detected 706, the plurality of n- bit words including data words and cyclic-redundancy check (CRC) words. At step 708, a set of n-bit local CRC words are generated based on the received data words. At step 710, n-bit syndrome words (e.g., the aforementioned error correction syndrome values) are formed based on (i) a set of local CRC calculations determined according to the received plurality of n-bit data words, and (ii) the received CRC words, the syndrome words identifying if an error is present. In response to an error being present, the method corrects 712 one or more errors in an erroneous data word having an index identified by a combination of the n-bit syndrome words, the one or more errors corrected using a bit error mask corresponding to one of the syndrome words.

[0075] In some embodiments, generating the local CRC words includes performing logical XOR functions on bits of the data words. In some embodiments, performing the logical XOR includes generating bits in position index i of a first local CRC word by XORing bits in position index i of each data word, wherein 0<i≤n-\ . In some embodiments, generating at least one local CRC word includes performing a modulo- reduced multiplication of each data word and a corresponding index of the data word, and recursively performing a logic XOR of each modulo-reduced multiplied data word.

[0076] In some embodiments, the set of local CRC words are updated recursively as each data word is received. Alternatively, the local CRC words may be generated subsequent to all of the data words being received.

[0077] In some embodiments, an error is present if each syndrome word is non-zero.

[0078] In some embodiments, identifying the index of the erroneous data word includes forming a binary reciprocal of the bit-error mask representing one of the syndrome words, and forming a modulo-reduced multiplication with a second syndrome word. In some embodiments, the binary reciprocal may be formed using a lookup table (LUT). In some embodiments, correcting the error comprises XORing the erroneous data word with the bit-error mask.

[0079] FIG. 8 is a flowchart of a method 800, in accordance with some embodiments. As shown, method 800 includes decoding 802, using a vector signal code receiver, a predetermined number of sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires. Incremental updates of a plurality of error correction syndrome values are generated 804 by an FEC check circuit based on each sequential set of data bits according to a check matrix. Upon decoding of a final vector signaling codeword of the predetermined number of received vector signaling codewords and performing a final incremental update of the plurality of error correction syndrome values, data bits are modified within the sequential sets of data bits by selecting 806 a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, and altering 808 the selected set of data bits according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

[0080] In some embodiments, generating the incremental updates of the plurality of error correction syndrome values includes performing a logical XOR operation on a previously-stored error correction syndrome value based on a given set of data bits. In some embodiments, the logical XOR operation is performed by performing a bit-wise XOR of the previously stored error correction syndrome value with the given set of data bits. Such an operation may be applicable when incrementally updating error correction syndrome values corresponding to r0". Alternatively, the logical XOR operation is performed by performing a logical XOR of the previously stored error correction syndrome value with bits determined by a CRC calculation corresponding to a result of a modulo-multiplication of the given set of data bits of a received data word mj with a binary expansion of symbol index integer j. Such an XOR operation may be applicable when incrementally updating error correction syndrome values corresponding to rl ". For example, CRC calculation may include modulo-multiplying the 5-bit data word m\3 by the 5-bit binary expansion of the integer j = ' 13 ', the CRC calculation subsequently XOR'd with the previously stored 5 bit rl error correction syndrome value may.

[0081] In some embodiments, the plurality of error correction syndrome values are initialized to logic zero values, and wherein performing the final incremental update of the plurality of error correction syndrome values includes comparing the plurality of error correction syndrome values to a plurality of received CRC words. Alternatively, the plurality of error correction syndrome values are initialized according to a plurality of received CRC words prior to generating the incremental updates of the plurality of error correction syndrome values.

[0082] In some embodiments, the symbol position index is determined by forming a binary reciprocal of the first error correction syndrome value, and forming a modulo- reduced multiplication with a second error correction syndrome value of the plurality of error correction syndrome values. In some embodiments, the binary reciprocal is formed using a lookup table (LUT), such as the LUT of Appendix C. [0083] In some embodiments, the first error correction syndrome value is updated by performing a logical XOR function on bits of the sequential sets of data bits sharing a common bit position.

[0084] In some embodiments, the selected set of data bits is altered by performing a bit- wise XOR of the selected set of data bits with the bit error mask to create a corrected set of data bits. In some embodiments, the sequential sets of data bits are stored in a first register, and wherein the bit error mask is stored in a second register, and wherein the corrected set of data bits are stored in a third register. In such embodiments, the symbol position index may identify a location in the second register to store the bit error mask.

[0085] As will be well understood by one familiar with the art, the methods used to buffer and reformat data in transmitter and receiver may utilize a variety of known art methods, including storage in random access memory, in a collection of data latches, or FIFO buffer elements. Conversion between data words and transmission-unit-sized bit groups may be facilitated by digital multiplexors, shift registers or barrel shifters, or dual-ported memory structures, either as stand-alone elements or integrated with the aforementioned storage elements. As previously mentioned, data path widths described in the above examples are based on the descriptive example offered without limitation of CNRZ-5 transport, with other data path widths and transport media being equally applicable. Similarly, an example set of four processing phases was used without implying limitation for both transmitter and receiver; other embodiments may utilize more or fewer processing instances without limit, including a single instance.

Appendix A - Incremental computation of r0, rl

One embodiment of the computation of r0 and rl may be performed by execution of the following sequence of operations, which are organized such that consecutive elements of the transmitted data stream may be processed in transmit order and grouping, with the processing delay of those operations pipelined or overlapped with transmission.

In the descriptive notation below, r0 [i] is biti of r0, similarly rl [z] is biti of rl. The notational sequence inp [] represents the input data being processed, wherein inp [0..4] are the bits of mO, inp [5..9] are the bits of ml, inp [145..149] are the bits of m29. denotes the Boolean XOR operator.

Appendix B - Error correction

Given a nonzero element of the finite field GF(32) in its 5-bit representation r0"[0], r0"[4] and another element rl"[0], rl"[4], the following procedure computes the bit representation of the element x = rl"/r0" in GF(32), that is, the bits x[0], x[4]. In the notation used below, 0 denotes the Boolean XOR and & the Boolean

AND operator.

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