Title:
PIXEL BASED GOBO RECORD CONTROL FORMAT
Document Type and Number:
WIPO Patent Application WO2000045218
Kind Code:
A8
Abstract:
A gate array schematic of this alternate embodiment in which a transfer controller (1106) is part of the FPGA. A transparency device (1100) which calculates values associated with transparency. A dual-port RAM (1102) which receives the VLIW at one port thereof, and outputs that value to a multiplexer (1104), which output it as a 32 bit signal used by a CPU/DSP (1105). The transfer controller (1106) is controlled directly by the CPU data received on line (1105). The transfer controller (1106) can have two lists of parameters (1110 and 1112), each 64 bits in width. These values are received on the list receivers.
Inventors:
HUNT MARK A (GB)
HEWLETT WILLIAM E (GB)
CLARKE IAN (GB)
KNOBEL KILLE (GB)
FINDLEY DREW (GB)
HOLT JONATHAN C (GB)
VARIN CHRISTOPHER (GB)
HEWLETT WILLIAM E (GB)
CLARKE IAN (GB)
KNOBEL KILLE (GB)
FINDLEY DREW (GB)
HOLT JONATHAN C (GB)
VARIN CHRISTOPHER (GB)
Application Number:
PCT/US2000/002600
Publication Date:
October 26, 2000
Filing Date:
February 01, 2000
Export Citation:
Assignee:
LIGHT & SOUND DESIGN LTD (US)
HUNT MARK A (GB)
HEWLETT WILLIAM E (GB)
CLARKE IAN (GB)
KNOBEL KILLE (GB)
FINDLEY DREW (GB)
HOLT JONATHAN C (GB)
VARIN CHRISTOPHER (GB)
HUNT MARK A (GB)
HEWLETT WILLIAM E (GB)
CLARKE IAN (GB)
KNOBEL KILLE (GB)
FINDLEY DREW (GB)
HOLT JONATHAN C (GB)
VARIN CHRISTOPHER (GB)
International Classes:
G02B26/08; G03F3/08; G09G5/36; G09G3/34; (IPC1-7): G02B26/00
Download PDF: