CMOS image sensors are integrated circuits designed specifically to capture and process incident light. The core of the sensor is generally made up of an array of pixels or picture elements. The pixels consist of photodiodes to sense the light, and CMOS transistors that take care of the amplification and transfer of the signal sensed by the photodiode.

As light strikes the array of pixels, it is converted into current, which in turn is converted into digitized data by an Analog-to-Digital Converter (ADC). This technology can be used in digital cameras, videophones, bar codes readers and other electronic equipment such as cameras used in machine vision.

The process of amplification and translation involves a substantial amount of analog circuitry, in order to establish a link between the pixel output and an ADC.

Despite the fact that CMOS image sensors present a wide variety of applications and advantages in comparison to other sensors, there are also major disadvantages linked to them, not only for still photography but also for moving pattern recognition. Some of these disadvantages are high power consumption and long integration time. High power consumption exists due to the amount of analog circuitry in the sensor chip, as

well as, the ADC; and integration time is a technology dependent factor, which has to be long enough if high-resolution ADC is to be achieved. For moving pattern recognition, long integration time is a major drawback since during this time a given pixel is not hit by the same part of a pattern, but rather by different moving parts of it.

In addition to long integration time and power consumption, moving pattern recognition introduces linear picture distortion. This is caused by the delay between activation of pixels located in consecutive rows. The delay between the first and last row of the array of pixels can sometimes be as long as 30 ms.

The disadvantages outlined above are difficult to eliminate due to the fundamental reason that the output of the pixel cell is analog in nature and has to be analog when a high-resolution picture is needed. There is however, a wide range of different applications where limited resolution, even ono-bit, is enough. For example, bar code recognition or barrier detection for autonomic vehicles and robots only needs a"binary"output, i. e. one-bit picture resolution.

Therefore, there is a need for novel pixel cell architecture for low resolution image sensors.

Summary of the Invention The invention is directed to a CMOS pixel cell for an image sensor comprising a photodiode and a voltage comparator having a first input coupled to the photodiode and a second input adapted to be coupled to a reference voltage. After the integration time of the preset photodiode, the resultant voltage on the photodiode capacitance is compared to the reference voltage providing a readout of the light intensity on the photodiode. The voltage comparator may be a one-bit analog-to- digital converter to provide a binary output.

In accordance with another aspect of the invention, the pixel cell further includes a storage element coupled to the voltage comparator for storing the binary output. The storage element may be a bus-latch having two cross-coupled inverters.

In accordance with a further aspect of this invention, the pixel cell further includes means for applying a predetermined reset voltage to the photodiode.

In accordance with another aspect of the invention, the pixel cell further includes means for presetting one of the cross-coupled inverters and means coupled between the comparator and the one inverter to apply the comparator output to the inverter input.

In accordance with a further aspect of this invention, the voltage comparator may be a PMOS transistor while the reset means, the selection means, the inverter preset means and the inverter input means may be NMOS transistors that are integrated on a chip with the photodiode.

In accordance with a further aspect of the invention, the photodiode comprises a doped semiconductor area placed on a semiconductor substrate to form a p-n junction and the comparator is a transistor having a source, a drain and a gate, with the transistor built into the doped semiconductor area. The semiconductor area may be n+ doped and the comparator transistor may be a PMOS transistor.

Other aspects and advantages of the invention, as well as the structure and operation of various embodiments of the invention, will become apparent to those ordinarily skilled in the art upon review of the following description of the invention in conjunction with the accompanying drawings.

Brief Description of the Drawings The invention will be described with reference to the accompanying drawings, wherein: Figure 1 illustrates a pixel architecture in accordance with the present invention; Figure 2 illustrates an alternate pixel architecture; Figure 3 illustrates a cross-sectional view of a transistor built in the photodiode area; Figure 4 illustrates an electrical schematic representing the photodiode and built-in transistor; Figure 5 illustrates a further embodiment of an active pixel cell in accordance with the present invention; Figure 6 illustrates a 6-transistor active pixel cell having a bus-latch reset by

the GMUX line; Figure 7 illustrates a 6-transistor active pixel cell having a bus-latch reset by selection line; Figure 8 illustrates a 5-transistor active pixel cell having a bus-latch reset by GMUX line; Figure 9 illustrates a 5-transistor active pixel cell having a buslatch reset by selection line; and Figure 10 illustrates a 4-transistor active pixel cell.

Detailed Description of the Invention Figurel illustrates a pixel cell 100 architecture in accordance with the present invention. It includes a photodiode 101, an NMOS reset transistor 102 coupled between a voltage source Vres and the photodiode 101. The photodiode 101 is further coupled to one input of a voltage comparator 103, the other input of the voltage comparator 103 is coupled to a reference voltage source Vref. The output of the voltage comparator 103 is coupled to the input of a storage element 104 that is activated by a strobe signal Strb. The storage element 104 is coupled to a selection transistor 105, which is activated by a control signal Select.

In operation, when the RESET signal is applied to the reset transistor 102, the photodiode 101 is precharged by applying the voltage Vres to the photodiode capacitance Cp. The photodiode 101 then converts the light impinged upon it into an electric current as the photodiode is discharged. The voltage comparator 103 works as a one-bit ADC by keeping track of the voltage level at the anode of the photodiode 101 and compares it with the reference voltage Vref. If the photodiode output is higher than the reference voltage Vref, then the comparator 103 will output a digital state of "1". If it is lower, then the output will be a digital state of"0". The digital output of the comparator 103 is stored in the one-bit storage element 104 after the integration time is completed. Writing to the storage element 104 is activated by the strobe signal Strb. When strobe signal Strb is at a high state, the output of the voltage comparator 103 becomes connected to the storage element 104. Subsequently, when transistor 105 is activated by the signal Select, it transfers the digital output from the storage

element 104 to the data bus.

Vres is a voltage used to load the photo-diode capacitance Cp at the beginning of each integration cycle. The value of this voltage is usually not less than the value of supply voltage Vdd, i. e. Vres 2 Vdd.

Vrefis a reference voltage used in the detection of the voltage level on the photo-diode capacitance Cp. The potential Vref depends on the integration time used.

The specified integration time results in the value of the voltage drop on the photodiode capacitance Cp i. e. AVpdc. For silicon diodes, the light-dependent voltage drop is relatively low, and usually, for integration time as long as a few tens of milliseconds, the maximum AVpdc is less than 1.5V.

Since Vres and Vref are required at different periods of time and since the components to which they are applied are controlled, an alternative embodiment of the pixel cell architecture 200, as shown in figure 2, is possible. In this embodiment, both voltages Vres and Vref are delivered from a variable voltage source by the same connection 206. This improvement simplifies the layout of the pixel array on a chip.

Normally Vres X Vref ; therefore, if they are sequentially applied to the same connection 206, the timing of the application of the proper voltage to connection 206 is important.

The voltage Vres should be applied to connection 206 at least a short time before the integration period starts and as for long as required to charge the photodiode 201 capacitance Cp. Also the voltage Vref should be applied to connection 206 at least some time before the end of the integration time and may be applied during the whole integration time. The voltage applied to connection 206 may be changed from Vref after the information from the voltage comparator 103 is stored in the storage element 104.

As shown in figure 3, the voltage comparator 103,203 of figures 1 and 2 may include a PMOS transistor 303 built into the photodiode 301 area of the chip as a unit

307. Photodiode 301 comprises an n+ region 3011 on a p-substrate 3012 forming the photodiode p-n junction that exhibits a capacitance Cp. The n+ region further includes anode terminal 3013. The PMOS transistor 303 includes spaced p+ regions located in the photodiode 301 n+ region with a source terminal 3031, a drain terminal 3032 and a gate terminal 3033. Vref is tied to the gate 3033 of the PMOS 303, the source 3031 is tied to a known potential such as ground, and the drain3032 is the output of the voltage comparator 303. The photodiode 301 and the transistor303 are effectively coupled through the n+ region whereby the photodiode 310 capacitance Cp potential Vpdc is compared to voltage Vref on the gate 3033. Transistor 303 will conduct when Vpdc > Vref and will not conduct when Vpdc < Vref. This construction uses the n+ region 3011 of the photodiode 301 area as an n+ well area for the PMOS transistor 303 resulting in a reduction of the total area required for thepixel cell.

Figure 4 is a schematic representation of the unit 407 that combines the photodiode 401 and the PMOS transistor 403 where the latter is used as the voltage comparator 103,203.

In general, the threshold voltage Vt of a MOSFET transistor defines the minimum value of a voltage between the gate and body (substrate) which is needed to create the strong inversion layer between the drain and source of the MOSFET. As the body potential VB goes low for a PMOS transistor with a threshold voltage Vtp, the gate potential VG has to be shifted low as well in order to retain the VB-VG > VtP relationship, which gives rise to the inversion layer and thus a current flow from source to drain.

During the comparison stage, the PMOS transistor 403 body potential is equal to the Vpdc i. e. the photodiode capacitance Cp potential, and the potential on the gate is equal to Vref which means that the relationship VU VU > Vtp can be written as Vpdc- Vref > Vtp. Next, taking into account that Vpdc= Vres-AVpdc, after the completion of the integration time, the new relationship Vres-AVpdC-Vref > Vtp can be obtained.

This leads to the conclusion that the inversion layer in the PMOS transistor is created when: Vref < Vres - #Vpdc - Vtp (1) This means that the inversion layer is not created when: <BR> <BR> <BR> <BR> <BR> <BR> Vref > Vres - #Vpdc - Vtp<BR> <BR> <BR> <BR> <BR> (2) Assuming that for a specified integration time, the V, dc = VrS-AVpdc is the highest level of photodiode capacitance Cp voltage, which is interpreted as the presence of light striking the pixel area, the relationship: <BR> <BR> <BR> <BR> <BR> <BR> Vref = Vres - #Vpdc - Vtp<BR> <BR> <BR> <BR> <BR> (3) defines the Vref voltage which distinguishes between the light and no-light states.

Figure 5 shows another embodiment of the invention that is based on the pixel circuit 200 described with respect to figure 2. In figure 5, the photodiode201 and the voltage comparator 203 shown in figure 2 are replaced by a photodiode 501 and a PMOS transistor 503 as a unit 507 similar to unit 407 shown in figure 4. In addition, a latch 504 is used for the storage element204. Latch 504 includes two cross-coupled inverters 5041,5042 and three NMOS transistors 5043,5044 and 5045. Transistor 5043 has its drain tied to the supply voltage Vdd and its gate tied to the RESET signal.

Transistor 5044 has its gate tied to Strb, its source tied to the drain of PMOS transistor 503 and the drain tied to the input of inverter 5041. Transistor 5045 has its gate tied to Strb-bar, its source tied to the input of inverter 5041 and its drain tied to the output of inverter 5042. When RESET is in a high state, transistor 502 becomes active and applies Vres. less the voltage drop across transistor502, to the photodiode capacitance Cp. Transistor 5043 also becomes active and applies a high potential to the input of inverter 5041 and thus the latch 504 is preset to an initial low state.

Once the reset state has ended, the RESET signal is switched to a low state. At this point the integration time begins. Before the end of the integration time period,

the potential at the gate of the PMOS transistor503 has to be changed from Vres to Vref. Once the integration time is completed, the Strb signal goes high and the potential on the drain of the PMOS transistor 503, which is the comparison result, is applied to transistor 5041 via transistor 5044 which becomes active when Strb goes into a high state. The drain of the PMOS transistor 503 either discharges the input capacitance of the inverter 5041 by inversion layer resistance while the Strb signal is in a high state or is in a high-impedance state, which does not affect the latch state when no inversion layer is induced. These two states of the drain of the PMOS transistor 503 can also be defined by Equations 1 and 2 respectively. Therefore, if the light intensity on the photodiode is relatively high during the integration period, the output of inverter 5041 will be in a high state, and if the light intensity on the photodiode is relatively low during the integration period, the output of inverter5041 will be in a low state. When Strb is returned to a low state, transistor5044 turns off and inverter 5041 becomes disconnected from the PMOS transistor503. Transistor 5045 becomes active, thereby connecting the output of the inverter 5042 to the input of inverter 5041 and completing the latch 504. The comparison result is then stored in the latch 504. When the SELECT signal is in a high state, the information stored on the latch 504 is transferred to the output bus to the image processing software through the selection transistor 505. The pixel cell presented here consists of nine transistors outside of the photodiode area.

The pixel cell 600 embodiment illustrated in figure 6 includes six transistors in a configuration having a reset transistor 602, a photodiode601 and a PMOS transistor 603 in unit 607, a bus-latch 604 which is a latch with only data input and no control signals, and a selection transistor 605. The latch 604 includes two cross-coupled inverters 6041 and 6042. The inverter 6041 driving the latch's 604 data input should be"weak"enough to allow for new data to be written; this can be achieved by using PMOS and NMOS transistors with high resistance channels. The PMOS transistor 603 in unit 607 is used to realize two different functions. In addition to acting as a voltage comparator as described in the previous embodiments, it also functions as a typical pass-transistor for presetting the bus-latch 604 to an initial state.

In order for the embodiment in figure 6 to work in accordance with the invention, the voltage drop on the photodiode capacitance Cp has to be such that during the integration time Vhlatch-Vph < 0.7V, where Latch ifs the source voltage on the PMOS transistor 603 and is also the voltage of the bus-latch 604 when Q = 1, and where Vph is the voltage on the photodiode capacitance Cp, the PMOS substrate voltage. This condition, which ensures no current flow by drain-body junction, can be achieved with appropriate selection of Vres.

Pixel cell 600 is controlled in the following manner. At the beginning of a new picture capture, the RESET and GMUX signals are set to logic high and Vre/Vref line 606 is set to the Vres. As a result, the photodiode capacitance Cpis loaded to a potential close to Vres and the integration time begins. Next, the RESET signal is set to logic low and the Vres/Vref line 606 is switched to the ground voltage. The photodiode 601 is disconnected from the Vre/Vref line 606, and the bus-latch 604 is preset to logic low (Q = 0) by the activated PMOS transistor603. After pre-setting the bus-latch 604, the Vres/Vref line 606 goes back to the Vres potential, and the GMUX signal has to be switched to logic low state. This event causes the PMOS transistor 603 to switch off and change to a voltage comparator configuration. In addition, this ensures no current flow by the drain-body junction of the PMOS transistor603. Once the integration time has been completed, the VresNref line 606 is switched to the Vref potential for a short time, which is functionally equivalent to the strobe pulse for the pixel cell 500 configuration in figure 5. If the drain of PMOS transistor603 is in a high impedance state, it will not affect the initial bus-latch 604 state. If it is not in a high impedance state, it will create a voltage divider with the PMOS transistor in inverter 6041. If this voltage divider's resulting voltage is low enough, the bus-latch 604 changes its state to opposite that of the initial state. After completing the storage process, the VresNref line 606 goes back to the Vres potential. Next, the RESET signal should go to logic high in order to avoid any current leakage by the p-n junction of the embedded PMOS transistor 603 as well as loading the photodiode capacitance Cpto a potential close to Vres. To pass the value stored in the latch 604, the SELECT signal has to be high in order to activate the selection transistor605.

In a further embodiment of the present invention shown in figure 7, the pixel cell 700 is similar to the cell described with respect to figure6 except that the GMUX line has been removed, resulting in a pixel cell 700 having a simpler control and layout. In this embodiment, the bus-latch 704 is preset from the data bus by the selection transistor 705 via a bi-directional I/O terminal connecting the pixel cell 700 with the data bus.

During pixel cell 700 initialization, the data bus has to be switched to a logic low state and the SELECT signal set to a logic high state which preset the bus-latch to its initial state Q = 0. The rest of the pixel cell 700 control is similar to that the pixel cell 600 of the configuration described with respect to figure 6. Before the readout of the bus-latch 704 state, the data bus has to be switched to a high-impedance state.

To properly operate the bus-latch 704, it should present the weak'1'on both its outputs to allow for new data to be written from both the comparator 703 side and the data bus side. This can be achieved by using PMOS transistors in inverters 7041 and 7042 with high resistance channels.

In a further embodiment of the present invention shown in figure 8, the pixel cell 800 is similar to the cell 600 described with respect to figure 6 except that the RESET transistor 602 has been removed, resulting in a pixel cell 800 which is simpler to implement and control, and which includes only five transistors, i. e. only two more than the typical analog, three-transistor cell.

At the start of the cycle, the GMUX line should be at the Vres potential and the Vres/Vref line 806 set to a logic low state. This leads to the bus-latch 804 being preset to the initial, low state (Q = 0) by the activated PMOS pass-transistor 803. The photodiode capacitance Cp is pre-charged to Vres-0. 7V by the forward-biased source- body junction of the PMOS transistor 803, the source terminal being the terminal connected to the GMUX line. After completing the initialization, the Vres/Vrefline 806 is switched to the Vres potential and, shortly thereafter, the GMUX line is switched to ground potential. As a result, the source-body junction of the PMOS transistor 803 is

reverse-biased i. e. the initial pro-charging of the photodiode capacitance Cp ends and integration time begins. The PMOS transistor803 switches off and goes into the voltage comparator configuration. To ensure the source-body junction reverse-biasing during the whole integration time, the Vres voltage should be selected in such a manner that Vres > Vdd + AVpd, where AVpdc is the maximum voltage drop on the photodiode capacitance Cp during the integration time. Once the integration time is completed, the Vres/Vref line 806 is switched to the Vref potential for a short time and the storage process begins as described with respect to the embodiments in figures6 and 7.

In another embodiment of the present invention shown in figure 9, the pixel cell 900 is similar to the cell 800 described with respect to figure 8 except that the GMUX line has been removed and the selection transistor 905 is connected to the Q- bar output of the bus-latch 904. As a result, the pixel cell 900 has a simpler layout.

The bus-latch 904 is preset and the photodiode 901 is pre-charged from the data bus by the selection transistor 905. To ensure proper operation, the inverter 9042 of the bus-latch 904 should be"weak"enough to allow for new data to be written and to reduce the current flow during initialization. This can be achieved by using PMOS and NMOS transistors with high resistance channels.

During pixel cell 900 initialization, both the data bus and the Vres/Vref line 906 have to be switched to the Vres potential, and selection transistor 905must be activated. Consequently, the photodiode capacitance Cp is pre-charged to Vres-0. 7V by the forward-biased drain-body junction of the PMOS transistor 903, and the bus- latch 904 is preset to the initial state Q = 0. After initialization is complete, the selection transistor 905 switches off. In effect, the drain potential of the PMOS transistor 903 goes to Vdd, forced by the inverter 9042, and the drain-body junction of the PMOS transistor 903 goes into reverse-bias. To ensure this reverse-bias during the whole integration time, the Vres voltage should be selected in such a manner that Ves > Vdd + AVpdc, where AVpdC is the maximum voltage drop on the photodiode capacitance Cp during the integration time. When the integration time is complete the Vres/Vref line 906 switches to the Vref potential and the storage process begins. Before

the readout of the state of the bus-latch 904, the data bus has to be switched into a high-impedance state.

In a further embodiment of the present invention shown in figure 10, the pixel cell 1000 is similar to the cell 800 described with respect to figure 8 except that the selection transistor 805 is removed. As a result, the pixel cell 1000has only a two- line interface and consists of only four transistors, i. e. only one more than the typical, analog, three-transistor cell. In this configuration, the PMOS transistor 1003 has the additional role as a selection pass-transistor. In effect, the Vre/VrefIine 1006 works as the selection control signal which means that the Vres/Vrefline 1006 is common for a group of pixel cells creating a"word"i. e. they are initialized and readout at the same time.

During the initialization period, the Vres/Vref control line 1006 switches to logic low (or ground) state and the I/O line inputs the Vres potential. As a result, the photodiode capacitance Cp is pre-charged to Vres-0. 7V by the forward-biased source- body junction of the PMOS transistor 1003, and the bus-latch 1004 is preset to the initial state Q = 0 by this same transistor 1003 acting as a pass-tansistor. After initialization is complete, the Vres/Vrefline 1006 switches to the Vres potential and, shortly thereafter, the I/O line switches to logic low (or ground) potential.

Consequently, PMOS transistor 1003 switches off and goes into voltage comparator configuration. Shortly after, the source-body junction of PMOS transistor 1003 goes into reverse-bias i. e. the initial pre-charging of the photodiode capacitance Cp ends and integration time begins. Once the integration time is complete, the Vr,, N, f line 1006 switches to the Vref potential for some time and the write-in process (latching the comparator output) begins which is identical to that described with regard to figures6, 7,8 and 9. After this process is complete, the I/O and VrelVref lines 1006 switch to the Vres potential and the pixel cell 1000 goes into storage mode, waiting to be read out.

Before the readout, the I/O has to be set as an output line i. e. disconnected from any voltages. Once the Vres/Vref line 1006 switches to logic low (or ground) the readout of bus-latch state begins by activating the PMOS pass-transistor 1003.

It should be understood that various alternatives to the embodiment of the invention described could be used. For example, different types of storage elements as shown in Figs. 5,6,7,8,9 and 10 fall within the scope of the invention.

The embodiments of the pixel cell architecture address the demands of an ideal"binary"image sensor by providing no delay between activation of consecutive rows of pixels, low power consumption and enabling shorter integration time. In addition, the embodiments allow pixel arrays to be treated as standard memory blocks.

While the invention has been described according to what is presently considered to be the most practical and preferred embodiments, it must be understood that the invention is not limited to the disclosed embodiments. Those ordinarily skilled in the art will understand that various modifications and equivalent structures and functions may be made without departing from the spirit and scope of the invention as defined in the claims. Therefore, the invention as defined in the claims must be accorded the broadest possible interpretation so as to encompass all such modifications and equivalent structures and functions.