The present invention relates to a pixel circuit and in particular, but not exclusively, to a pixel circuit that has a high dynamic range and a low dark current. The invention also relates to a CMOS image sensor that includes an array of pixel circuits. The term "pixel" as used herein refers to an individual photosensor. The pixel may exist on its own, for example as part of a single pixel device, or it may form part of an image sensor, for example a CMOS image sensor, that comprises an array of photosensors. A high dynamic range (HDR) pixel is one that is sensitive to a very wide range of light intensities, for example exceeding lOOdB. Image sensors made using the CMOS process are the principal sensors used in typical cameras. These sensors include an array of pixels, each pixel consisting of a photosensitive diode and a few transistors that work as amplifiers. In a typical pixel, the photodiode is reverse biased to a reset voltage. A photocurrent is generated when light falls on the photodiode. The reverse voltage on the photodiode also gives rise to a thermally generated leakage current that flows in parallel with the photocurrent.

CMOS image sensors, and in particular wide dynamic range sensors like the logarithmic pixels, suffer from poor performance under low light condition. This limitation is due to the inherent leakage current that flows through the photosensitive diode even in the absence of light and appears as a so-called "dark current". Typical approaches to reducing this leakage current involve manufacturing process modifications, which are costly, risky, time consuming and often not in the control of the designer. Many existing patents, for example US7397076 and US7239003 focus on this aspect and on improving the isolation boundary of the photodiode.

Another approach is to compensate for the dark current by evaluating the difference between a lit pixel and a dark pixel: this approach is described for example in US7879641 and US20070023614A1. The compensation approach generally uses an additional photodiode to compensate for the undesired leakage current effect.

An alternative approach that uses a double current mirror pixel to reduce the photodiode potential is described by B. Choubey, D. Joseph, S. Aoyama and S. Collins, "Dark current reduction techniques for wide dynamic range logarithmic CMOS pixels" Proceedings of the 30th International Congress of Imaging Science, pp. 155-159, May 2006. However, the pixel was found to have a larger dark current than a conventional pixel and accordingly was considered not to be useful.

Certain objects of the present invention are to provide a pixel circuit and a CMOS image sensor comprising a plurality of pixel circuits that mitigate one or more of the aforesaid problems.

According to one aspect of the present invention there is provided a pixel circuit comprising a power supply that provides a supply voltage V _DD A, a current mirror circuit having first and second parallel branches, and a reverse-biased photodiode that is connected in series in the first branch of the current mirror circuit, wherein the photodiode is configured to provide a photocurrent I _p in response to incident light that flows through the first branch of the current mirror circuit and is matched by a corresponding mirror current in the second branch of the current mirror circuit, wherein the pixel circuit further comprises a bias voltage supply that applies a bias voltage V _BI AS to minimise a photodiode potential V _P d across the photodiode. By applying a bias voltage V _BI AS it is possible to reduce the photodiode potential V _P d at low photocurrents (e.g. less than 10 ^"15 A) to a fraction of the potential that occurs in the absence of a bias voltage. For example, the photodiode potential V _P d can typically be reduced to a value in the range 2-8mV, as compared to a value greater than 50mV without the bias voltage. This reduction in the photodiode potential V _P d results in a very low dark current, thereby increasing the sensitivity of the pixel at very low light levels.

The pixel circuit includes a current mirror circuit that is configured to reduce the reverse bias voltage applied to the photodiode. If the currents flowing in the two branches of the mirror circuit were equal the photodiode voltage Vpd should be zero. However, a second order dependence of the MOS drain source potential, due to the Drain Induced Barrier Lowering effect, leads in practice to a non-zero potential Vpd across the photodiode PD. In the present invention this higher order effect is removed by applying at least one external bias voltage, VBIAS, which reduces the potential Vpd across the photodiode PD close to zero and removes all higher order effects. The bias voltage V _BI AS is selected through an optimisation process to bring the photodiode voltage Vpd as close to zero as possible.

In an embodiment the photodiode potential V _P d is less than lOOmV, preferably less than 20mV, more preferably less than lOmV.

In an embodiment the photodiode that is connected in series with a first transistor in the first branch of the current mirror circuit, wherein the bias voltage V _BI AS is selected to regulate the body-source voltage V _B S in this first transistor, so that the body-source voltage V _B S is related to the supply voltage VDDA by the relationship VBS = -X.VDDA where the coefficient x is in the range 0-0.7, preferably in the range 0.2-0.5.

In one embodiment, where the bias voltage is applied to the anode of the photodiode and the cathode of the photodiode is connected to the source terminal of one of a pair of nMOS transistors, the bias voltage VBIAS is related to the supply voltage VDDA by the relationship VBIAS = X.VDDA, where the coefficient x is in the range 0-0.7, preferably in the range 0.2-0.5.

In another embodiment where the bias voltage is applied to the cathode of the photodiode and the anode of the photodiode is connected to the source terminal of one of a pair of pMOS transistors, the bias voltage VBIAS is related to the supply voltage VDDA by the relationship VBIAS = VDDA - X.VDDA, where the coefficient x is in the range 0-0.7, preferably in the range 0.2-0.5. In another embodiment, where the photodiode is connected between the power supply V _DD A and the source terminal of one of a pair of pMOS transistors and the bias voltage is applied to the body terminals of the pMOS transistors, the bias voltage V _BI AS is related to the supply voltage VDDA by the relationship VBIAS > VDDA, or more specifically VBIAS = VDDA + X.VDDA where the coefficient x is in the range 0-0.7, preferably in the range 0.2-0.5.

In another embodiment, where the photodiode is connected between ground and the source terminal of one of a pair of nMOS transistors and the bias voltage is applied to the body terminals of the nMOS transistors, the bias voltage V _BI AS is a negative voltage relative to ground, or more specifically VBIAS = 0 - X.VDDA where the coefficient x is in the range 0-0.7, preferably in the range 0.2-0.5.

In another embodiment, where a first bias voltage V _BI AS is applied to the anode of the photodiode and the cathode of the photodiode is connected to the source terminal of one of a pair of nMOS transistors, the supply voltage V _DD A is applied to the body terminals of a pair of pMOS transistors, and a second bias voltage V _BI AS2 is applied to the source terminals of the pMOS transistors, the first bias voltage VBIAS is related to the supply voltage VDDA by the relationship VBIAS = X.VDDA, and the second bias voltage VBIAS2 is related to the supply voltage VDDA by the relationship VBIAS2 = VDDA - X.VDDA, where the coefficient x is in the range 0-0.7, preferably in the range 0.2-0.5.

The current mirror circuit may be a double current mirror circuit. For example, in an embodiment the double current mirror circuit may comprise an nMOS current mirror circuit and a pMOS current mirror circuit. Alternatively, other current mirror circuits may be used.

In an embodiment the current mirror circuit comprises a pair of FETs, and wherein each of said FETs has a channel aspect ratio (W/L) of less than 1 : 1 , preferably less than 1 :2, more preferably less than 1 :4. For example, the current mirror circuit may consist of a pair of nMOS FETs and a pair of pMOS FETs, wherein each of said nMOS and pMOS FETs has a channel aspect ratio (W/L) of less than 1 : 1 , preferably less than 1 :2, more preferably less than 1 :4. The most preferable aspect ratio depends on the manufacturing process used, but for a typical manufacturing process with a feature size of HOnm the nMOS and/or pMOS FETs may, for example, each have a channel aspect ratio (W/L) of about 1 :6. Alternatively, both the length and the width of the channel can be increased to avoid the short channel effects and achieve current mirroring. In this embodiment it is possible to achieve a low dark current by increasing both W and L so that the W/L ratio is greater than unity (for example, W/L = 1.01). This arrangement would require more space and may not be so efficient, but it may provide a reduction in dark current that is adequate for certain applications.

In one embodiment the current mirror circuit is located between the power supply and the photodiode, and wherein the photodiode has a cathode terminal connected to the current mirror circuit and an anode terminal connected to the bias voltage supply. In another embodiment the current mirror circuit is located between the photodiode and a ground connection, and wherein the photodiode has an anode terminal connected to the current mirror circuit and a cathode terminal connected to the bias voltage supply.

In another embodiment the current mirror circuit includes a pair of nMOS transistors, wherein the photodiode has a cathode terminal connected to a source terminal of one of the nMOS transistors and an anode terminal connected to a ground connection, and wherein the bias voltage supply is configured to apply a negative bias voltage to a body terminal of each of the pair of nMOS transistors.

In another embodiment the current mirror circuit is located between the power supply and the photodiode, and wherein the current mirror circuit includes a pair of nMOS transistors and a pair of pMOS transistors, wherein the photodiode has a cathode terminal connected to the a source terminal of one of the nMOS transistors and an anode terminal connected to a first bias voltage supply, and wherein the pMOS transistors each have a source connection that is connected to a second bias voltage supply.

According to another aspect of the present invention there is provided a pixel circuit comprising a photodiode having first and second terminals, a power supply that applies a reverse bias voltage to a first terminal of the photodiode so that the photodiode provides a photocurrent I _p in response to incident light, and a current mirror circuit having first and second parallel branches, wherein the first branch is connected between the power supply and the first terminal of the photodiode and the second branch is connected between the power supply and the second terminal of the photodiode, and wherein the nMOS current mirror circuit comprises a pair of FETs, each having a channel aspect ratio (W/L) of less than 1: 1.

In an embodiment the FETs each have a channel aspect ratio (W/L) of less than 1:2, more preferably less than 1 :4. The FETs may, for example, each have a channel aspect ratio (W/L) of about 1:6.

The low aspect ratio of the FETs results in a very low dark current, thereby increasing the sensitivity of the pixel at very low light levels.

The pixel circuit may include an output circuit connected to the first branch of the current mirror circuit, which may for example be a source-follower output circuit or a differential amplifier output circuit.

The pixel circuit may have a logarithmic output, providing a high dynamic range.

According to another embodiment of the invention there is provided an image sensor including an array of pixel circuits, wherein said array includes at least one pixel circuit according to any one of the preceding statements of invention.

In an embodiment the image sensor comprises a CMOS image sensor.

Various embodiments of the invention will now be described by way of example with reference to the accompanying drawings, wherein:

Figure 1 is a circuit diagram of a pixel circuit according to a first embodiment of the invention;

Figure 2 is a graph of output voltage against photocurrent showing the comparative responses of a pixel circuit according to the present invention and a typical conventional logarithmic pixel, and

Figure 3 is a graph of diode voltage against photocurrent showing the comparative responses of a pixel circuit according to the present invention that has an applied bias voltage and a similar pixel circuit that does not have an applied bias voltage; Figure 4 is a circuit diagram of a pixel circuit according to a second embodiment of the invention;

Figure 5 is a circuit diagram of a pixel circuit according to a third embodiment of the invention; Figure 6 is a circuit diagram of a pixel circuit according to a fourth embodiment of the invention; and

Figure 7 is a circuit diagram of a pixel circuit according to a fifth embodiment of the invention.

Figure 1 is a schematic circuit diagram of a pixel circuit 2. The pixel circuit 2 may comprise a standalone pixel for use in a single pixel device, or it may be part of an array of pixels in a CMOS image sensor. It should be noted that if the pixel is part of an array some components of the pixel may be shared with other pixels.

The pixel circuit shown in Fig. 1 includes a double current mirror circuit 4 comprising an nMOS current mirror 6 comprising two nMOS FET transistors Ml, M2, a pMOS current mirror 8 comprising two pMOS FET transistors M3, M4, a reverse-biased photodiode PD, and a source-follower output circuit 10 comprising nMOS transistors M5, M6.

The source terminals S of the pMOS transistors M3, M4 are connected to a fixed power supply 12, which provides a supply voltage V _DD A. The gate terminals of the pMOS transistors M3, M4 are connected to the drain terminal of the pMOS transistor M3. The drain terminals of the nMOS transistors Ml, M2 are connected respectively to the drain terminals of the pMOS FET transistors M3, M4. The gate terminals of the nMOS transistors Ml, M2 are connected to the drain terminal D of the nMOS transistor M2. The source terminal S of the nMOS transistor Ml is connected to the cathode 14 of the photodiode PD. The anode 16 of the photodiode PD and the source terminal S of the nMOS transistor M2 are connected to a bias voltage source 18, which supplies a bias voltage VBIAS-

The body terminals (not shown) of the nMOS transistors M1,M2 are connected to ground, and the body terminals (not shown) of the pMOS transistors M3,M4 are connected to the supply voltage V _DD A. The bias voltage source 18 therefore raises the potential at the anode 16 of the photodiode PD to a bias voltage V _BI AS above ground.

The gate terminal of the nMOS source follower transistor M5 is connected to the drain terminal D of the pMOS transistor M3. The drain terminal D of source follower transistor M5 is connected to the supply voltage V _DD A and the source terminal S is connected via a row selector transistor M6 to an output terminal 20. The gate terminal of the row selector transistor M6 is connected to a row select terminal 22 to receive a row select signal.

The transistors M5 and M6 form a readout circuit 10, providing an output stage for the pixel. The readout circuit 10 includes an output node 20 for an output signal V _ou t, which is connected to the source terminal S of the select transistor M6. The readout circuit 10 is designed to sense the voltage at the gate connection of the source-follower transistor M5 without drawing any current. The gate of the select transistor M6 is connected to receive a select signal Row_Sel at a row select terminal 22 to select which pixel in a row or column of pixels is connected to the output node 20. Alternatively, the pixel may include a differential output stage, or the output stage can be omitted and the output signal sensed directly.

In this circuit, the transistors Ml and M2 form an nMOS current mirror 6 while the transistors M3 and M4 form a pMOS current mirror 8. The nMOS current mirror 6 and the pMOS current mirror 8 thus form a double current mirror circuit 4 having first and second parallel branches 30, 32 wherein the first branch 30 comprising transistors Ml and M3 is connected between the power supply 12 and the cathode 14 of the photodiode PD, and the second branch 32 comprising transistors M2 and M4 is connected between the power supply 12 and the anode 16 of the photodiode PD. The double current mirror circuit 4 is designed to provide an equal current in both branches 30, 32 of the mirror circuit. The bias voltage source 18 is connected to the anode 16 of the photodiode PD and supplies a bias voltage VBIAS to the anode.

The photodiode PD generates a photocurrent I _PD when light falls on it. If the loop formed by the transistors Ml, M2 and the photodiode PD is considered, the voltage on the photodiode PD can be expressed as Vpd = Vgs2-Vgsl where Vpd is the photodiode voltage, Vgs2 is the gate-source voltage of transistor M2 and Vgsl is the gate-source voltage of transistor Ml. The photodiode voltage Vpd should be zero if the currents flowing in the nMOS transistors Ml, M2 are equal. However, a second order dependence of the MOS drain source potential, due to the Drain Induced Barrier Lowering effect, leads to non-zero potential Vpd across the photodiode PD. This potential can be reduced either by increasing the body effect of the transistors Ml, M2 or by increasing the channel length of the transistors, or by a combination of these modifications.

According to one aspect the present invention this higher order effect is removed by applying an external bias voltage, V _BI AS, to the anode of the photodiode PD, which reduces the potential Vpd across the photodiode PD close to zero and removes all higher order effects. The bias voltage V _BI AS is selected through an optimisation process so as to reduce the photodiode voltage Vpd as close to zero as possible. In practice, the photodiode voltage Vpd will generally be less than lOOmV and will typically be in the range 2-8mV or less. In this embodiment the bias voltage VBIAS is related to the supply voltage VDDA by the relationship VBIAS = X.VDDA, where the coefficient x is in the range 0-0.7, preferably in the range 0.2-0.5.

According to another aspect of the present invention the photodiode potential is reduced by increasing the channel length of the nMOS transistors M1,M2 and/or the pMOS transistors M3,M4. For example, the width/length (W/L) ratio (the aspect ratio) of the channel may be less than unity, and for a typical manufacturing process with a feature size of HOnm the aspect ratio is preferably approximately 1 :6. By comparison, in conventional FETs the aspect ratio is usually much greater than unity. In other words, the width of the channel is usually much greater than the length.

The pixel described above has been simulated using typical circuit simulation software. Figure 2 shows the response of the new pixel (upper curve) vis-a-vis a typical pixel (lower curve). It may be observed that the new pixel provides an order of magnitude better performance than the typical pixel at low photocurrents. This means that the new pixel will perform significantly better in low light conditions than a conventional pixel. It is worth noting that the graph has been plotted on a logarithmic scale as the pixel captures a wide dynamic range of intensities. To further confirm that the pixel circuit is actually providing approximately zero potential across the photodiode PD, a further figure 3 is attached, which shows the photodiode voltage at different photocurrents for a pixel circuit with an applied bias voltage VBIAS of IV (lower curve), and for a similar pixel circuit with no applied bias voltage (upper curve). In absence of the bias voltage VBIAS the photodiode voltage rises at low photocurrents to over 75mV, which leads to higher dark current in the photodiode. With an applied bias voltage VBIAS of IV, the photodiode voltage can be reduced to less than 5mV, thus producing a significantly lower dark current. Simulations suggests that in a typical pixel circuit configuration, the application of a bias voltage reduces the dark current approximately ten-fold.

The dependence of the photodiode voltage on the bias voltage and the bias potential may be explained as follows.

The double current mirror pixel circuit has been investigated to understand the cause of the higher than expected potential across the photodiode. Let us consider the expression of the threshold voltage VTH at the variation of the body effect:

where VFB is the flat-band voltage, N _A is the doping density in the substrate, C _OX is the gate oxide capacitance, est is the dielectric constant of the silicon, q is the electron charge and ψβ = (KT/q) log(N _a /n is the difference between the Fermi potential and the intrinsic potential in the substrate.

This equation shows that a change of the body-source voltage VBS will result in a variation of the threshold voltage. In addition, a change in the ψβ potential will do the same. In a first approximation when considering the drain source current the change of the threshold voltage VTH should not affect the behaviour of the current mirror. However, the following expression of the sub-threshold leakage current IDS, subth should also be considered: where Is is a factor which depends on the aspect ratio of the nMOS channel, VTHO is the zero bias threshold voltage, η is the Drain-Induced Barrier Lowering (DIBL) coefficient. For small values of V _B S, the body effect is linear and it is represented by the term γ' V s where γ' is the linearised body effect coefficient (Roy et al. "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits" Proc. of the IEEE, Feb 2003)

In this equation, the sub-threshold current IDS, subth is dependent on the VDS voltage. In the double current mirror circuit, transistors Ml and M2 have different drain- source voltages V _D S. This difference causes a mismatch between the two drain-source currents I _D S which in turn causes the gate-source voltage VGS of the current mirror pair to be different, thus increasing the voltage drop on the photodiode. However, increasing the body- source voltage V _B S increases the effect of the first term (VGS) in the exponential compared to the second term (VTHO) where the drain-source voltage VDS is present. If the body-source voltage VBS is sufficiently increased, the mismatch between the two currents will be reduced and, as a consequence, the photodiode voltage drop will be reduced as well.

Furthermore, the Drain-Induced Barrier Lowering (DIBL) coefficient is a short channel effect which can be reduced by increasing the length of the channel so that the aspect ratio W/L is less than unity and for a typical manufacturing process with a feature size of 1 lOnm the aspect ratio is preferably approximately 1:6. In fact, when the source and drain of a MOSFET are spatially close the barrier between them is lowered. This changes the ψβ potential and in turn the threshold voltage and the same explanation as for the body voltage applies again.

A pixel circuit according to a second embodiment of the invention is shown in Fig. 4. Except as indicated below, this circuit is similar to the first circuit shown in Fig. 1 and described above. The pixel circuit again includes a double current mirror circuit 4 comprising an nMOS current mirror circuit 6 and a pMOS current mirror circuit 8. The nMOS current mirror 6 comprises two nMOS FET transistors Ml, M2, and the pMOS current mirror 8 comprises two pMOS FET transistors M3, M4.

In this embodiment the reverse-biased photodiode PD is connected between the source terminal S of the pMOS transistor M4 and a bias voltage source 18, which supplies a bias voltage V _BI AS. The source terminal S of the second pMOS transistor M3 is also connected to the bias voltage source 18. The body terminals (not shown) of the pMOS transistors M3,M4 are connected to the supply voltage V _DD A via an N-well 26 that accommodates the pMOS transistors M3,M4. The bias voltage source 18 therefore raises the potential at the cathode of the photodiode above the supply voltage VDDA.

Alternatively, instead of a single N-well 26, separate N-wells may be provided to accommodate each of the pMOS transistors M3,M4. These N-wells may be supplied with the same bias voltage or they may alternatively be supplied with different bias voltages. Having two separate N-wells requires extra space but provides an extra degree of freedom for the Vbias potential.

Returning to Fig. 4, the source terminals S and the body terminals (not shown) of the nMOS transistors M1,M2 are connected to ground GND. The drain terminals D of the nMOS transistors M1,M2 are connected to the drain terminals D of the pMOS transistors M3,M4.

The gate terminals of the pMOS transistors M3, M4 are connected to the drain terminal D of the pMOS transistor M3. The gate terminals of the nMOS transistors Ml, M2 are connected to the drain terminal of the nMOS transistor M2, which is connected via output line 24 to a conventional source-follower output circuit (not shown).

The photodiode PD generates a photocurrent I _PD when light falls on it, which flows through the first branch 30 of the current mirror circuit 4 comprising transistors M2,M4. This photocurrent is matched in the second branch 32 of the current mirror circuit 4 comprising transistors M1,M3. The photodiode voltage Vpd should be zero if the currents flowing in the pMOS transistors M3, M4 are equal. However, a second order dependence of the MOS drain source potential, due to the Drain Induced Barrier Lowering effect, leads to non-zero potential Vpd across the photodiode PD. This potential is removed by applying an external bias voltage, VBIAS, to the cathode 14 of the photodiode PD, which reduces the potential Vpd across the photodiode PD close to zero and removes all higher order effects. Alternatively or in combination with this, the photodiode potential may be reduced by reducing the aspect ratio of the current mirrors (however this occupies more area and in certain circumstances may be less convenient). The bias voltage V _BI AS is selected through an optimisation process so as to reduce the photodiode voltage Vpd as close to zero as possible. In practice, the photodiode voltage Vpd will generally be less than lOOmV and will typically be in the range 2-8mV or less. In this embodiment the bias voltage VBIAS is related to the supply voltage VDDA by the relationship VBIAS = VDDA - X.VDDA, where the coefficient x is in the range 0-0.7, preferably in the range 0.2-0.5.

A pixel circuit according to a third embodiment of the invention is shown in Fig. 5. Except as indicated below, this circuit is similar to the second circuit shown in Fig. 2 and described above. The pixel circuit again includes a double current mirror circuit 4 comprising an nMOS current mirror circuit 6 and a pMOS current mirror circuit 8. The nMOS current mirror 6 comprises two nMOS FET transistors Ml, M2, and the pMOS current mirror 8 comprises two pMOS FET transistors M3, M4.

In this embodiment the reverse-biased photodiode PD is connected between the source terminal S of the pMOS transistor M4 and the power supply 12, which provides the supply voltage V _DD A. The source terminal S of the second pMOS transistor M3 is also connected to the power supply 12. The pMOS transistors M3,M4 are accommodated in an isolated N-well 34 and the body terminals B of the pMOS transistors M3,M4 are connected to a bias voltage source 18 that supplies a bias voltage V _BI AS. The bias voltage source 18 therefore raises the potential at the body terminals B of the pMOS transistors M3,M4 above the supply voltage V _DD A. Alternatively, separate N-wells may be provided to accommodate the two pMOS transistors M3,M4, which may be supplied with the same bias voltage or different bias voltages.

The source terminals S and the body terminals (not shown) of the nMOS transistors M1,M2 are connected to ground GND. The drain terminals D of the nMOS transistors M1,M2 are connected to the drain terminals D of the pMOS transistors M3,M4.

The gate terminals of the pMOS transistors M3, M4 are connected to the drain terminal D of the pMOS transistor M3. The gate terminals of the nMOS transistors Ml, M2 are connected to the drain terminal of the nMOS transistor M2, which is connected via output line 24 to a conventional source-follower output circuit (not shown). The photodiode PD generates a photocurrent I _PD when light falls on it, which flows through the first branch 30 of the current mirror circuit 4 comprising transistors M2,M4. This photocurrent is matched in the second branch 32 of the current mirror circuit 4 comprising transistors M1,M3. The photodiode voltage Vpd should be zero if the currents flowing in the pMOS transistors M3, M4 are equal. However, a second order dependence of the MOS drain source potential, due to the Drain Induced Barrier Lowering effect, leads to non-zero potential Vpd across the photodiode PD. This potential is removed either by applying an external bias voltage, V _BI AS, to the body terminals B of the pMOS transistors M3,M4, which reduces the potential Vpd across the photodiode PD close to zero and removes all higher order effects, or by reducing the aspect ratio of the current mirrors.

The bias voltage V _BI AS is selected through an optimisation process so as to reduce the photodiode voltage Vpd as close to zero as possible. In practice, the photodiode voltage Vpd will generally be less than lOOmV and will typically be in the range 2-8mV or less. In this embodiment the bias voltage VBIAS is related to the supply voltage VDDA by the relationship VBIAS > VDDA or more specifically VBIAS = VDDA + X.VDDA where the coefficient x is in the range 0-0.7, preferably in the range 0.2-0.5.

A pixel circuit according to a fourth embodiment of the invention is shown in Fig. 6. The pixel circuit again includes a double current mirror circuit 4 comprising an nMOS current mirror 6 and a pMOS current mirror 8. The nMOS current mirror 6 comprises two nMOS FET transistors Ml, M2, and the pMOS current mirror 8 comprises two pMOS FET transistors M3, M4.

In this embodiment the reverse-biased photodiode PD is connected between the source terminal of the nMOS transistor Ml and a ground connection GND. The source terminal of the second nMOS transistor M2 is also connected to ground GND. The body terminals B of the nMOS transistors M1,M2 are connected to a bias voltage source 18, which supplies a negative bias voltage V _BI AS to an isolated P-well 36 that accommodates the nMOS transistors M1,M2. Alternatively, separate P- wells may be provided to accommodate the two nMOS transistors M1,M2, which may be supplied with the same bias voltage or different bias voltages. The drain terminals of the nMOS transistors M1,M2 are connected to the drain terminals of the pMOS transistors M3,M4 and the source terminals of the pMOS transistors M3, M4 are connected to the source 12 of the supply voltage V _DD A.

The gate terminals of the pMOS transistors M3, M4 are connected to the drain terminal of the pMOS transistor M3, which is connected to a conventional source-follower output circuit 10 comprising source-follower transistor M5 and output node 20. The gate terminals of the nMOS transistors Ml, M2 are connected to the drain terminal of the nMOS transistor M2.

The photodiode PD generates a photocurrent I _PD when light falls on it, which flows through the first branch 30 of the current mirror circuit 8 comprising transistors M1,M3. This photocurrent is matched in the second branch 32 of the current mirror circuit comprising transistors M2,M4. The photodiode voltage Vpd should be zero if the currents flowing in the nMOS transistors Ml, M2 are equal. However, a second order dependence of the MOS drain source potential, due to the Drain Induced Barrier Lowering effect, leads to non-zero potential Vpd across the photodiode PD. This potential is removed by applying a negative bias voltage, V _BI AS, to the body terminals B of the nMOS transistors M1,M2. This reduces the potential Vpd across the photodiode PD close to zero and removes all higher order effects. The photodiode potential Vpd may also be reduced by reducing the aspect ratio of the current mirrors.

The bias voltage V _BI AS is selected through an optimisation process so as to reduce the photodiode voltage Vpd as close to zero as possible. In practice, the photodiode voltage Vpd will generally be less than lOOmV and will typically be in the range 2-8mV or less. In this embodiment the bias voltage V _BI AS is a negative voltage relative to ground, or more specifically VBIAS = 0 - X.VDDA where the coefficient x is in the range 0-0.7, preferably in the range 0.2-0.5.

A pixel circuit according to a fifth embodiment of the invention is shown in Fig. 7. The pixel circuit again includes a double current mirror circuit 4 comprising an nMOS current mirror 6 and a pMOS current mirror 8. The nMOS current mirror 6 comprises two nMOS FET transistors Ml, M2, and the pMOS current mirror 8 comprises two pMOS FET transistors M3, M4. The drain terminals D of the nMOS transistors M1,M2 are connected to the drain terminals D of the pMOS transistors M3,M4. In this embodiment the reverse-biased photodiode PD is connected between the source terminal S of the first nMOS transistor Ml and a first bias voltage supply 18 that supplies a first bias voltage V _BI AS. The source terminal S of the second nMOS transistor M2 is also connected to the first bias voltage supply 18. The source terminals S of the pMOS transistors M3,M4 are connected to a second bias voltage source 18', which supplies a second bias voltage V _BI ASI. The body terminals (not shown) of the pMOS transistors M3,M4 are connected to the supply voltage VDDA via an isolated N-well 38 that accommodates the pMOS transistors M3,M4. Alternatively, separate N- wells may be provided to accommodate the two pMOS transistors M3,M4, which may be supplied with the same bias voltage or different bias voltages.

The gate terminals of the pMOS transistors M3, M4 are connected to the drain terminal of the pMOS transistor M3, which is connected to a conventional source-follower output circuit 10 comprising source-follower transistor M5 and output node 20. The gate terminals of the nMOS transistors Ml, M2 are connected to the drain terminal of the nMOS transistor M2. The photodiode PD generates a photocurrent I _PD when light falls on it, which flows through the first branch 30 of the current mirror circuit comprising transistors M1,M3. This photocurrent is matched in the second branch 32 of the current mirror circuit comprising transistors M2,M4. The photodiode voltage Vpd should be zero if the currents flowing in the nMOS transistors Ml, M2 are equal. However, a second order dependence of the MOS drain source potential, due to the Drain Induced Barrier Lowering effect, leads to non-zero potential Vp across the photodiode PD. This potential is removed by applying a first bias voltage, VBIAS, to the anode of the photodiode PD, and a second bias voltage VBIASI to the source terminals of the pMOS transistors M3,M4. The first bias voltage V _BI AS reduces the need for an increase in channel length of the nMOS transistors M1,M2 and the second bias voltage V _BI ASI reduces the need for an increase in channel length of the pMOS transistors M3,M4 .

This reduces the potential Vpd across the photodiode PD close to zero and removes all higher order effects. The bias voltages VBIAS and VBIASI are selected through an optimisation process so as to reduce the photodiode voltage Vpd as close to zero as possible. In practice, the photodiode voltage Vpd will generally be less than lOOmV and will typically be in the range 2-8mV or less. In this embodiment the first bias voltage V _BI AS is related to the supply voltage VDDA by the relationship VBIAS = X.VDDA, and the second bias voltage VBIAS2 is related to the supply voltage VDDA by the relationship VBIAS2 = VDDA - X.VDDA, where the coefficient x is in the range 0-0.7, preferably in the range 0.2-0.5.

A pixel circuit according to a sixth embodiment of the invention is shown in Fig. 8. Except as indicated below, this circuit is similar to the second circuit shown in Fig. 5 and described above. The pixel circuit again includes a double current mirror circuit 4 comprising an nMOS current mirror circuit 6 and a pMOS current mirror circuit 8. The nMOS current mirror 6 comprises two nMOS FET transistors Ml, M2, and the pMOS current mirror 8 comprises two pMOS FET transistors M3, M4.

In this embodiment the reverse-biased photodiode PD is connected between the source terminal S of the pMOS transistor M4 and the power supply 12, which provides the supply voltage V _DD A. The source terminal S of the second pMOS transistor M3 is also connected to the power supply 12.

The pMOS transistors M3,M4 are accommodated in an isolated N-well 34 and the body terminals B of the pMOS transistors M3,M4 are connected to a first bias voltage source 18 that supplies a bias voltage V _BI AS. The first bias voltage source 18 raises the potential at the body terminals B of the pMOS transistors M3,M4 above the supply voltage V _DD A. The nMOS transistors M1,M2 are accommodated in an isolated P-well 36 and the body terminals B of the nMOS transistors M1,M2 are connected to a second bias voltage source 18' that supplies a second bias voltage V _BI ASL The second bias voltage source 18' raises the potential at the body terminals B of the nMOS transistors M1,M2 above the ground potential.

Alternatively, separate N- wells may be provided to accommodate the two pMOS transistors M3,M4, and separate P- wells may be provided to accommodate the two nMOS transistors M1,M2, and each pair of wells may be supplied with the same bias voltage or different bias voltages. The source terminals S and the body terminals (not shown) of the nMOS transistors M1,M2 are connected to a third bias voltage source 18" that supplies a third bias voltage V _BI AS3. The drain terminals D of the nMOS transistors M1,M2 are connected to the drain terminals D of the pMOS transistors M3,M4. The gate terminals of the pMOS transistors M3, M4 are connected to the drain terminal D of the pMOS transistor M3. The gate terminals of the nMOS transistors Ml, M2 are connected to the drain terminal of the nMOS transistor M2, which is connected via output line 24 to a conventional source-follower output circuit (not shown).

The photodiode PD generates a photocurrent I _PD when light falls on it, which flows through the first branch 30 of the current mirror circuit 4 comprising transistors M2,M4. This photocurrent is matched in the second branch 32 of the current mirror circuit 4 comprising transistors M1,M3. The photodiode voltage Vpd should be zero if the currents flowing in the pMOS transistors M3, M4 are equal. However, a second order dependence of the MOS drain source potential, due to the Drain Induced Barrier Lowering effect, leads to non-zero potential Vpd across the photodiode PD. This potential is removed by applying a first bias voltage, V _BI AS, to the body terminals B of the pMOS transistors M3,M4, a second bias voltage VBIASI to the body terminals of the nMOS transistors M1,M2, and a third bias voltage, VBIAS3, to the source terminals S of the nMOS transistors M1,M2. This reduces the potential Vpd across the photodiode PD close to zero and removes all higher order effects. Alternatively or in addition, the potential Vpd across the photodiode PD may be reduced by reducing the aspect ratio of the current mirrors.

The first, second and third bias voltages VBIAS, VBIASI and VBIAS3 are selected through an optimisation process so as to reduce the photodiode voltage Vpd as close to zero as possible. In practice, the photodiode voltage Vpd will generally be less than lOOmV and will typically be in the range 2-8mV or less. In this embodiment the first bias voltage V _BI AS is related to the supply voltage VDDA by the relationship VBIAS = VDDA + X.VDDA, the second bias voltage VBIASI is related to the supply voltage VDDA by the relationship VBIAS = 0 - X.VDDA, and the third bias voltage VBIAS3 is related to the supply voltage VDDA by the relationship VBIAS = X.V _DD A, where the coefficient x is in the range 0-0.7, preferably in the range 0.2-0.5. A pixel circuit according to a seventh embodiment of the invention is shown in Fig. 9. The pixel circuit again includes a double current mirror circuit 4 comprising an nMOS current mirror 6 and a pMOS current mirror 8. The nMOS current mirror 6 comprises two nMOS FET transistors Ml, M2, and the pMOS current mirror 8 comprises two pMOS FET transistors M3, M4. The drain terminals D of the nMOS transistors M1,M2 are connected to the drain terminals D of the pMOS transistors M3,M4.

In this embodiment the reverse-biased photodiode PD is connected between the source terminal S of the first nMOS transistor Ml and a ground connection GND. The source terminal S of the second nMOS transistor M2 is also connected to ground. The pMOS transistors M3,M4 are accommodated in an isolated N-well 38 and the body terminals B of the pMOS transistors M3,M4 are connected to a first bias voltage supply 18 that supplies a first bias voltage V _BI ASI. The source terminals S of the pMOS transistors M3,M4 are connected to a second bias voltage source 18', which supplies a second bias voltage VBIAS2. Alternatively, separate N- wells may be provided to accommodate the two pMOS transistors M3,M4, and separate P- wells may be provided to accommodate the two nMOS transistors M1,M2, and each pair of wells may be supplied with the same bias voltage or different bias voltages.

The body terminals B of the nMOS transistors M1,M2 are connected to a negative bias voltage source 18", which supplies a negative bias voltage V _BI AS to an isolated P-well 36 that accommodates the nMOS transistors M1,M2.

The gate terminals of the pMOS transistors M3, M4 are connected to the drain terminal D of the pMOS transistor M3, which is connected to a conventional source-follower output circuit 10 comprising source-follower transistor M5 and output node 20. The gate terminals of the nMOS transistors Ml, M2 are connected to the drain terminal of the nMOS transistor M2.

The photodiode PD generates a photocurrent I _PD when light falls on it, which flows through the first branch 30 of the current mirror circuit comprising transistors M1,M3. This photocurrent is matched in the second branch 32 of the current mirror circuit comprising transistors M2,M4. The photodiode voltage Vpd should be zero if the currents flowing in the nMOS transistors Ml, M2 are equal. However, a second order dependence of the MOS drain source potential, due to the Drain Induced Barrier Lowering effect, leads to non-zero potential Vp across the photodiode PD. This potential is removed by applying a first bias voltage, VBIASI, to the body terminals B of the pMOS transistors M3,M4, a second bias voltage V _BI ASI to the source terminals of the pMOS transistors M3,M4, and a negative bias voltage, V _BI AS, to the body terminals B of the nMOS transistors M1,M2. The first bias voltage V _BI ASI reduces the need for an increase in channel length of the nMOS transistors M1,M2, the second bias voltage V _BI ASI reduces the need for an increase in channel length of the pMOS transistors M3,M4 and the negative bias voltage, VBIAS reduces the potential Vpd across the photodiode PD close to zero and removes all higher order effects. The photodiode potential Vpd may also be reduced by reducing the aspect ratio of the current mirrors.

The bias voltages VBIAS, VBIASI and VBIASI are selected through an optimisation process so as to reduce the photodiode voltage Vpd as close to zero as possible. In practice, the photodiode voltage Vpd will generally be less than lOOmV and will typically be in the range 2-8mV or less. In this embodiment the first bias voltage VBIASI is related to the supply voltage VDDA by the relationship VBIASI = X.VDDA, the second bias voltage VBIAS2 is related to the supply voltage VDDA by the relationship VBIAS2 = VDDA - X.VDDA, and the negative bias voltage VBIAS is related to the supply voltage VDDA by the relationship VBIAS = 0 - X.VDDA where the coefficient x is in the range 0-0.7, preferably in the range 0.2-0.5.

In each of the embodiments described above, the bias voltage V _BI AS is used to regulate the body-source voltage V _B S of the transistor in the first branch 30 of the current mirror circuit to which the photodiode PD is connected. In the first, fourth and fifth circuits shown in Figs. 1, 6 and 7, the photodiode is connected to the first nMOS transistor Ml, while in the second and third circuits shown in Figs. 4 and 5 the photodiode is connected to the first pMOS transistor M4. The bias voltage V _BI AS is selected to regulate the body- source voltage V _B S in this first transistor, so that the body- source voltage V _B S is related to the supply voltage V _DD A by the relationship VBS = -X.VDDA where the coefficient x is in the range 0-0.7, preferably in the range 0.2-0.5. A typical value of the supply voltage V _DD A is 3.3 Volts so, for example, in the first embodiment shown in Fig. 1 where the bias voltage V _BI AS is applied to the source S of transistor Ml and the body terminal of transistor Ml is connected to ground, a bias voltage VBIAS of IV will provide a body-source voltage VBS of -0.3* VDDA.

The embodiments described above use a pair of current mirrors comprising an nMOS current mirror and a pMOS current mirror. Other current mirrors may also be used. For example, the pixel circuit could use Widlar current mirrors, Cascoded configurations, Wilson current mirrors or other types. These or other current mirror configurations may be used for either the nMOS current mirror configuration or the pMOS current mirror, or any combination of these possible configurations. In general, any technique that copies or forces the current to be the same in both branches of the circuit may be used.

The invention may be used in CMOS image sensors designed for use in digital cameras as well as a number of other imaging devices including, for example, radio-diagnosis detectors, satellite imagers and CCTVs. This pixel will also be particularly useful for various biomedical imaging techniques including fluoroscopy. The invention provides a pixel with a wide dynamic range of operation and a low number of transistors. Unlike most current solutions, which attempt to reduce the dark current by costly process modifications, the invention involves redesigning the pixel circuit so that it has a process-independent leakage current.

Embodiments of the invention use a different circuit to those used in typical image sensors. Typical pixels integrate charge on a diode. In embodiments of the invention the circuit uses a current mirror to mirror the diode current. In parallel, the circuit ensures that voltage across the photodiode is fixed to zero (or as close as possible to zero). This is achieved by ensuring that both ends of the diode are biased at a higher voltage than ground. This removes any low geometry effects and ensures that the pixel works when made in any manufacturing process. The undesired contribution of a leakage current flowing in the photodiode in absence of light is referred to as "dark current". This current limits the performance of the pixel when operating at low light levels. This dark current is dependent on the temperature as well as the voltage applied across the diode. For very low dark current applications, for example in astrophysics, a pixel is often cooled to very low temperature. However, at room temperature, this leakage current will be zero only if the voltage across the diode is zero volts. In embodiments of the invention this is achieved using a novel circuit configuration by pushing both ends of the photodiode to a higher but similar voltage. This provides a zero volt condition for very low leakage currents. This also ensures that the higher order effects, due to the substrate around the diode being at ground potential, do not affect the performance of the pixel circuit. In embodiments of the invention the circuit uses two current mirrors to keep the voltage of the photodiode close to zero, thus eliminating the dark current.

The circuit is suitable for imaging or light sensing in any low light conditions. Applications include communication systems, biomedical systems, microscopy applications, and security cameras, as well as low light detectors. The pixel circuit may be used either in a single pixel device, for example in a high precision light meter, or it may be part of an array of pixels for example in a CMOS image sensor.

Another important application of the pixel circuit is in x-ray imaging, for example in radiotherapy and in radio-diagnosis equipment, where a very low dark current and a wide dynamic range are required. The pixel can be integrated into a device for converting x-rays into visible light, known as a scintillator, to provide an x-ray detector with enhanced performance. Either a single pixel, or an array of pixels, or a set of pixel arrays can be used in this way.