PLANARIZATION OF EPITAXIAL HETEROSTRUCTURES INCLUDING THERMAL TREATMENT

FIELD OF THE INVENTION

The present invention relates to the field of epitaxial heterostructures including a relaxed buffer layer epitaxially grown on a substrate of a different material, as for instance graded silicon germanium (SiGe) layers deposited on a Si substrate.

BACKGROUND OF THE INVENTION

Relaxed graded SiGe buffers are commonly used notably as substrates for the achievement of high electron mobility structures.

However, it is known that in such relaxed graded buffers gradual lattice mismatch occurs, resulting in a disperse, three-dimensional misfit dislocation network (see for instance document PCT/EP2004/006186).

Due to the influence of these dislocation strain fields during growth, the surface of the SiGe buffer is considerably roughened, exhibiting cross- hatch patterns, thus requiring polishing to flatten the surface before subsequent growth or wafer bonding steps can be achieved. Moreover, the characteristic cross-hatch surface roughness and the underlying strain fields of the misfit array can overlap, blocking threading dislocation glide and leading to dislocation pile-ups. Such a metastable state can produce changes in the surface state when further steps of the process are performed, as induced by thermal activation. In view of this, many methods have been experimented in order to obtain smooth relaxed SiGe layers epitaxially grown on substrates of a different material such as Si.

According to a first approach, thermal processes are carried out during the epitaxially growth of relaxed Si(i _-X )Ge( _X ) buffer layers.

Document "Smooth.relaxed Sio.75Geo.25 layers on Si(OOl) via in situ rapid termal annealing", S. Hong, Y. L. Foo, K. A Bratland, T. Spila, and al, Applied Physics letters, VoI 83, N°21, november 2003, discloses that smooth strain-relaxed Sii- _x Ge _x alloy layers on Si(OOl) substrates can be obtained via a rapid thermal annealing (RTA) which is performed in situ (i.e. directly in the epitaxy equipment), at a temperature of 1000 ⁰ C and a duration of 10 seconds. Such conditions are a tradeoff between excessive surface topology with higher temperatures and unsufficient relaxation with lower temperatures. The main drawbacks of such a technique are the uncertainty of reproducibility because of the low throuput and the very high temperature needed to be effective during the very limited treatment time.

Document "Low thermal budget surface preparation of Si and SiGe", A. Abbadie, JM. Hartmann, P. Hollinger, M.N. Semeria, P. Besson, P. Gentile, Applied Surface Science, October 2003, discloses a process for surface preparation of Si and Sii- _x Ge _x layers comprising a thermal annealing during 2 min, under H ₂ atmosphere, at 800 ⁰ C, which is performed exsituanά in combination with a humid cleaning of the HF-Last type. However such a technique does not change the surface topology nor its roughness.

Another solution for removing the surface topology occurring on the SiGe heteroepitaxial layers is to use specific polishing techniques. Document PCT/EP2004/006186 describes a polishing method which permits to eliminate surface topology when observed with an atomic force microscope and to achieve a final post splitting polish to roughness values less than 0.2 nm RMS, over 1x1 μm ² and 10x10 μm ² area.

However, it appears that the scale range available when using atomic force microscopy (AFM) technique is not sufficient to ensure whether cross-hatch patterns are completely removed after polishing. Indeed, these surface changes imply low spatial frequencies (or relatively wide surfaces variations) so that they cannot be observed with the usual technique of AFM technique which involves small surface scans (e.g. 10x10 μm ² area). Thus, it has been noted that, after polishing, some structures no longer exhibit cross-hatch when they are observed with an

atomic force microscope whereas surface topology appears when examining them at a lower spatial frequency. Such a topology characterization can be performed with "the surface Haze" which allows measuring of the roughness on a large scale (i.e. on the whole wafer), the "Haze" corresponding to a measure of the light scattered by the surface irregularities that reflects the surface roughness.

Therefore, the prior art methods cannot provide a solution which ensures to obtain SiGe buffer layers without any surface topology, and this with a high rate of reproducibility. Even in the case of a chemical mechanical polishing (CMP), it can remain residual topology at the surface. Moreover, the cross-hatch may "reemerge" during subsequent thermal treatments.

OBJECT AND SUMMARY OF THE INVENTION

In view of such aspects, an object of the present invention is therefore to provide a technique which insures that the surface of an epitaxial heterostructure is planarized with a sufficient quality for subsequent growth or wafer bonding, and this without risks of reemergence of surface topology notably during subsequent heating of the heterostructure.

This object is attained with a method of planarization of an epitaxial heterostructure comprising at least a strain-relaxed buffer layer epitaxially grown on a substrate of a different material, the method comprising: a step of thermal annealing the epitaxial heterostructure at a temperature of at least 900 ⁰ C for a period of at least 2 hours, and a step of chemical-mechanical polishing the surface of the strain-relaxed buffer layer. The planarization method of the invention provides a specific thermal treatment which allows, by improving the relaxation of the strain- relaxed buffer layer, to obtain a better quality of the surface planarization and to insure a stable material for further processing.

Indeed, the thermal processing firstly brings an improvement to the polishing step for removing surface topology (e.g. cross-hatch) in that the

strained heteroepitaxial buffer layer is completely relaxed before the chemical-mechanical polishing step. In other words, the thermal annealing step structurally changes the surface of the layer in increasing the surface topology which, according to the method of the invention, is advantageous since the thermal annealing step is carried out before the polishing step.

The structural changes brought by the thermal annealing take place also inside the material of the layer which results in a stable equilibrium for the internal energy of the material with regard to subsequent heat treatments of the heterostructure. Reemergence of surface topology is thus prevented.

According to an aspect of the invention, the step of annealing the epitaxial heterostructure is carried out preferably in an atmosphere mainly composed of argon and that may contain about 2% of oxygen. This slightly oxidizing atmosphere allows an oxide layer of a thickness about 150 A to be formed on the epitaxial heterostructure.

The step of annealing the epitaxial heterostructure is carried out at temperatures ranging from 900 ⁰ C to 1000 ⁰ C and for a period lying between about 2 hours to 4 hours.

The epitaxial heterostructure may comprise a strain-relaxed buffer graded SiGe layer grown on a silicon substrate, the SiGe layer having cross-hatch patterns and localized irregularities at its surface.

The step of annealing the epitaxial heterostructure is carried out ex situ, namely outside the epitaxy reactor after the formation of the epitaxial heterostructure, to insure high production yield since several wafers can be processed together.

The step of chemical-mechanical polishing the surface of the strain- relaxed buffer layer is carried out with a polishing pad having a compressibility comprised between 2 and 15% and a slurry containing at least 20% of silica particles having a size comprised between 70 and 100 nm.

This polishing step allows to reach high polishing rates (ex. 40 A/sec) appropriated for eliminating surface defects or topology on heteroepitaxial layers, such as cross-hatch patterns, and to achieve, in the same time, a final polish roughness values less than 4 A RMS for a scan

area of 40*40 μm ² and 2 A RMS for a scan area of 10*10 μm ² , while preserving an industrial, cost effective process.

Indeed, the planarization and the smoothing being performed in one-step polishing process, the method of the invention brings cost reduction and production yield in comparison with the usual polishing process which calls for important material removal usually takes place in two steps: one step for planarization followed by a finishing step to get a specified roughness level, such as disclosed in the patent EP 1 016 129.

This method of planarization further brings industrial advantages such as good reproducibility and is easily transferable for production.

In case of removing cross-hatch pattern from the surface of the strain-relaxed layer, the parameters of the polishing tool can be adjusted so as to reach a stabilized polishing rate around 40 A/sec, which permits to carry out the step of chemical mechanical polishing for a period less than 200 seconds.

For instance, a stabilized polishing rate around 40 A/sec can be reached when the head velocity Vt and the platen velocity Vp of the polishing tool, such as that provided in Strasbaugh's 6DS-SP CMP Systems, are set such that Vt/Vp=46/30 rpm with a polishing pressure P of 6 psi. In the same way, in order to have a polishing rate comprised in the range 35 A/sec to 45 A/sec, the three above parameters can be adjusted according to the following possibilities:

- if Vt and Vp are constant (i.e. Vt=46 rpm and Vp=30 rpm) then 5<P<7 psi, - if P and Vp are constant (i.e. P=6 psi and Vp=30 rpm) then

40<Vt<55 rpm, and

- if P and Vt are constant (i.e. P=6 psi and Vt=46 rpm) then 25<Vp< 35 rpm.

Moreover, since the method of the invention allows to obtain a final polish roughness values less than 5 A RMS (4 A RMS for a scan area of

40*40 μm ² and 2 A RMS for a scan area of 10*10 μm ² ) that corresponds to the typical roughness value from which a molecular bonding can be performed, said method may further comprise a step of molecular bonding the epitaxial heterostructure to a receiving substrate such as a silicon substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention and its advantages will be better understood from the following description, given as non-limiting examples, of preferred embodiments with reference to the appended drawings, in which:

Figure 1 is a curve showing general aspect of a thermal cycle performed during the annealing step of the invention. - Figure 2 illustrates the influence of different annealing conditions on the surface planarity of SiGe buffer layers, either before chemical-mechanical polishing (CMP) or after, as measured with the surface Haze;

Figure 3 shows the effects of annealing on the surface roughness, as measured by AFM, and the difference between a small surface scan (10*10 μm ² ) and a larger surface scan (40*40 μm ² );

Figure 4 shows pictures which enhance this benefit of annealing on the surface roughness after CMP, as observed with AFM performed on 40*40 μm ² surface scans; - Figure 5 is a schematic of an apparatus for polishing according to an embodiment of the invention;

Figures 6A and 6B are curves showing polishing rate variation according to polishing time which are obtained with the method of the invention and with a conventional method.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

According to an embodiement, the invention implements an annealing step in the overall processing of planarization of graded SiGe substrates in order to better eliminate by polishing the cross-hatch pattern and to provide thermally stable substrates for further wafer processing.

This annealing process can be carried out with the following values of the parameters: - temperature range: 900 -1000 ⁰ C ;

- annealing time: 2-4 hours ;

- thermal cycle: as shown in figure 1;

- atmosphere: inert or slightly oxidizing, namely about 2% of oxygen ; Regarding the thermal cycle of the annealing process, as shown in figure 1, the temperature when the wafers are introduced in the oven (boat-in) at the beginning of the cycle and at the end of a cycle when they are taken out of the oven (boat-out) is between 300-600 ⁰ C and typically about 500 ⁰ C. The ramp rate, which is the period of time during the cycle when temperature is rising (i.e. ramp-up) or falling (i.e. ramp-down), is comprised in the range 5°C/min to 30 °C/min, typically of about 10 °C/min as indicated in figure 1. The period of time for the ramp-up or the ramp- down is about 40 min. Between the ramp-up and the ramp-down period, the wafer temperature is kept constant (i.e. steady-state) at a steady-state temperature ranging from 900 ⁰ C to 1000 ⁰ C and for a steady-state time duration from 2 hours to 4 hours.

The annealing process is performed at atmospheric pressure under an argon atmosphere which can include about 2% of oxygen allowing the formation of an oxide layer of a thickness about 150 A. The annealing is performed exsituQ.e, outside the epitaxy reactor) which allows several wafers to be processed at once and to introduce oxidizing compounds if needed. Moreover, for relatively long annealing time, as compared to previous known proposed annealing, it is believed that it results in more uniform relaxation if the SiGe layer. Such an annealing results in an increase of the cross-hatch pattern before polishing as seen by Haze measurement, but it leads to an improved quality of the surface planarity after polishing, in that it allows to remove entirely the cross-hatch pattern. Indeed, the chemical-mechanical step is performed on a layer which is completely relaxed thanks to the previous annealing step.

Moreover the substrates obtained according to this process exhibit a better thermal stability for the further steps of the whole process notably those implementing thermal treatments. More precisely, the annealing step also changes the whole material of the layer, which results in a stable equilibrium for the internal energy of the material and prevents

reemergence of surface topology at the time of subsequent heat treatments.

The benefits inferred from implementing this thermal processing in the planarization process of graded SiGe buffer layers will be better understood through the following comments hereafter.

Figure 2 illustrates the influence of different annealing conditions on the surface planarity of SiGe buffer layers, either before chemical- mechanical polishing (CMP) corresponding to ^w Haze after TUT (thermal treatment)" in the figure or after corresponding to "Haze after CMP" in the figure, as measured with the surface Haze.

Large portions of the surface (or equivalents low spatial frequencies) can be observed by this technique, as opposed to AFM for which only small portions (or equivalents high spatial frequencies) can be measured. Two important features are set in evidence by the graph of figure 1, which reports Haze measurements performed on Si(i- _X )Ge _x (x»20%) substrates with different annealing conditions:

- An increase of the Haze with the annealing energy, which reflects an increase in the surface irregularities. This is confirmed by roughness measurements which ranges from 2.3 ppm for no annealing to 2.55 ppm for an annealing of 2 hours at 1000 ⁰ C;

- A decrease of the Haze after CMP with the annealing energy, ranging from a ratio of 20 for no annealing to a ratio of 35 after annealing of 2 hours at 1000 ⁰ C. Figure 3 shows the effects of annealing on the surface roughness, as measured by AFM, and the difference between a small surface scan (10*10 μm ² ) and a larger surface scan (40*40 μm ² ). In the figure, A designates a starting Si(i- _X )Ge _x (x«20%) substrate material, THT designates annealing according to three different annealing conditions (THTl, THT2 and THT3), and CMP designates chemical-mechanical polishing.

As can be seen from figure 3, the former scan (10*10 μm ² ) leads to similar values of the roughness before and after CMP, whatever the thermal processing is, while only the latter scan (40*40 μm ² ) allows to

observe the increase of surface roughness after annealing but before CMP and the decrease of this roughness after CMP for annealed samples.

Figure 4 shows pictures which enhance this benefit of annealing on the surface roughness after CMP, as observed with AFM performed on 40*40 μm ² surface scans: the first four pictures (pictures 1 to 4) show the cross-hatch patterns before CMP, with (pictures 2 to 4) or without (picture 1) annealing, while the last two pictures (pictures 5 and 6) show the difference in surface roughness after CMP between an annealed sample (picture 5) and a non-annealed sample (picture 6), the latter showing that punctual defects (intense lines) are still present.

Thus, the annealing process which is one object of the invention allows to eliminate, after CMP, both the cross-hatch pattern and the punctual surface defects.

When comparing annealed and non annealed samples as for the dislocation rate, by measuring pile-up density and/or threading dislocation density with a physical-chemical analysis method like the Schimmel Etch for example (Journal of Electrochemistry Society (ECS), vol. 126 (1979), p. 479), it becomes apparent that, even at 1000 ⁰ C, the annealing step does not cause damages to the layer. In other words, the annealing step according to the invention does not lead to migration of dislocations to the surface of the layer.

Once the annealing step is terminated, the chemical-mechanical polishing step is carried out.

Figure 5 illustrates a system 10 according to an embodiment of the invention which can be used for implementing the method of the present invention. The system 10 comprises a polishing head 11 into which a structure 12 to be polished is inserted and a plate 13 covered with a polishing pad 14. A liquid abrasive or slurry is injected into the head, for example via a side conduit 15. A polishing pressure Fe and a movement represented by an arrow 16 are applied to the head 11 to carry out polishing.

The structure 12 is a heterostructure comprising at least a heteroepitaxial layer 121, as for example a SiGe layer, which has grown on a substrate 120 of another material such as silicon. The surface of the heteroepitaxial layer 121 is polished in order to eliminate cross-hatch

patterns occurred during growth from the dislocation strain fields and annealing step. The polishing step can also be used for smoothing the final surface disturbed after a transfer process using a substrate fracture method (ex. Smart Cut™) has been performed (after-cleaving residues). According to the present invention, chemical-mechanical polishing

(CMP) is carried out with an intermediate polishing pad, that is a pad having a compressibility rate less than that of a soft pad and more than a hard pad. More precisely, the polishing pad used in the invention has a compressibility rate included between 2% (hard pad) and 15% (soft pad), preferably around 6%.

The CMP is also performed by an "aggressive" slurry containing a colloidal solution, such as a NH ₄ OH solution, with high rate of silica, namely more than 20%, and silica particles in 70-100 nm range.

The combined use of the above-mentioned intermediate pad and aggressive slurry allows to perform CMP which are suitable to the polishing of heteroepitaxial layers, such as Si(i- _X )Ge( _X ) layers, permitting, on the one hand, to eliminate either the surface defects (Crosshatch patterns, after-cleaving residues), and, on the other hand, to achieve a final post bonding polish, while preserving an industrial, cost effective process. Alternatively, a slurry slightly less aggressive (e.g. diluted to 1/40 or containing smaller particles) may be selected in order to prevent local residual strains that may still be present from being selectively etched or polished.

The polishing pad used in the invention is primarily intended for smoothing the surface, while the slurry with a high rate of silica enhances the reactive and mechanical activity of the etching and hence allows to increase the polishing rate for Si(i- _X )Ge( _X ).

The advantages of the CMP step of the present invention become apparent when comparing the polishing rate obtained with typical processes used for silicon polishing, such as disclosed in document FR 2 842 755, with that obtained with the planarization method of the invention. Figure 6A shows the polishing rate according to polishing time which is obtained with a typical process (curve B) used for silicon polishing (soft pad of around 10% compressibility, "standard" slurry including a colloidal solution with a low rate of silica (less than 10%) and silica

particles of 130-210 nm in diameter), here applied to SiGe polishing, and with the planarization method of the invention (i.e. CMP with intermediate pad stiffness of 6 % compressibility, "aggressive" slurry including at least 20% of silica particles having a size comprised between 70 and 100 nm) (curve A). The results shown in figure 6A are obtained from SiGe samples which consist of Sio.βGeo.2 wafers.

Figure 6A clearly shows the advantages of the planarization method of the invention for the polishing rate on Si(i- _X )Ge( _X ) since it permits to reach a polishing rate of around 40 A/sec, versus 2 A/sec with the typical process.

As a result, the processing duration is very short, less than 200 seconds in order to eliminate a Crosshatch pattern of a thickness around 500 nm and prepare surface for bonding. In some instances, it has been found that as little as 200 nm of stock removal was sufficient to eliminate cross-hatch patterns in an approximate time of 100 sec.

Figure 6B which is an enlarged view of the curve A of figure 5A, indicates that the polishing rate decreases along with time and stabilizes from around 130 seconds to about 40 A/sec, a value well suitable for large material removal such as required by Crosshatch pattern removal. Such stabilization insures also good process reproducibility.

The stabilized polishing rate of 40 A/sec can be obtained by adjusting the parameters of the polishing tool. For instance, a stabilized polishing rate around 40 A/sec can be reached when the Vt, Vp parameters (Vt=head velocity and Vp=platen velocity) of the polishing tool, such as that provided in Strasbaugh's 6DS-SP CMP Systems, are set such that Vt/Vp=46/30 rpm with a polishing pressure P of 6 psi. In the same way, in order to have a polishing rate comprised in the range 35 A/sec to 45 A/sec, the three above parameters can be adjusted according to the following possibilities: - if Vt and Vp are constant (i.e. Vt=46 rpm and Vp=30 rpm) then

5<P<7 psi,

- if P and Vp are constant (i.e. P=6 psi and Vp=30 rpm) then 40<Vt<55 rpm, and

- if P and Vt are constant (i.e. P=6 psi and Vt=46 rpm) then 25<Vp< 35 rpm.

The ultra-smooth surfaces thus obtained are well fitted for applications such as strained Si epitaxy regrowth for forming strained silicon bulk material and/or molecular bonding in view of sSOI (strained silicon on insulator) or SGOI (Strained Silicon on Silicon Germanium on Insulator (SGOI) wafers manufacturing. Indeed, regarding the molecular bonding, the method of planarization of the present invention allows to obtain a final polish roughness values less than 5 A RMS (4 A RMS for a scan area of 40*40 μm ² and 2 A RMS for a scan area of 10*10 μm ² ) that corresponds to the typical roughness value from which a molecular bonding can be performed. Therefore, the planarization method of the invention can be used as a surface preparation step for strain-relaxed buffer layers such as SiGe layers that must be molecular bonded on receiving substrates such as Si substrates.

By using, for polishing heteroepitaxial layers as Si(i _-X )Ge _(X) layers, more appropriate both pad stiffness grade and silica colloidal solutions, the invention allows to get surface roughness values for as good as a usual final polishing processes, but in a much shorter time. A short time then insures to minimize major defects, such as scratches, which often occur for long polishing times. Consequently, the polishing process is better adapted for mass production.

Accordingly also, it is cost effective since the polishing is performed in a one-step process on a completely relaxed epitaxial material thanks to the previous annealing step described above.