Title:
PLASMA DISPLAY PANEL INTEGRATED CIRCUIT, ACCESS CONTROL METHOD AND PLASMA DISPLAY SYSTEM
Document Type and Number:
WIPO Patent Application WO/2012/001886
Kind Code:
A1
Abstract:
This invention provides a plasma display system wherein the peak data transfer amount in a case of using a shared memory can be suppressed. In the plasma display system, at timing when an SF reading unit (103) reads, from a shared memory (140), SF pixel data that is information indicating lighted-up cells in each of the subfields, a control unit (104) suppresses the access of a moving image decoder (101) to the shared memory (140). At timing when the SF reading unit (103) is not reading, from the shared memory (140), any SF pixel data, that is, during a sustain discharge interval, the control unit (104) permits the moving image decoder (101) to access the shared memory (140).
Inventors:
MAEDA MASAKI
OOTANI NAOKI
KIYOHARA TOKUZO
OOTANI NAOKI
KIYOHARA TOKUZO
Application Number:
PCT/JP2011/003281
Publication Date:
January 05, 2012
Filing Date:
June 09, 2011
Export Citation:
Assignee:
PANASONIC CORP (JP)
MAEDA MASAKI
OOTANI NAOKI
KIYOHARA TOKUZO
MAEDA MASAKI
OOTANI NAOKI
KIYOHARA TOKUZO
International Classes:
G06F12/00; G09G3/20; G09G3/28; G09G3/288; G09G3/298; H04N5/66
Foreign References:
| JP2005017725A | 2005-01-20 | |||
| JP2008197653A | 2008-08-28 | |||
| JP2005338123A | 2005-12-08 | |||
| JP2004309846A | 2004-11-04 | |||
| JPH11175024A | 1999-07-02 | |||
| JP2007079292A | 2007-03-29 | |||
| JPH0916142A | 1997-01-17 |
Attorney, Agent or Firm:
NAKAJIMA, Shiro et al. (JP)
Shiro Nakajima (JP)
Shiro Nakajima (JP)
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Claims: