Title:
PLL CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2008/044350
Kind Code:
A1
Abstract:
A PLL circuit includes a voltage-controlled oscillator (4), which has two voltage/current
converting circuits (40,41) and a selecting circuit (42) for selecting an output
of one of those voltage/current converting circuits (40,41). The output of the
voltage/current converting circuit selected by the selecting circuit (42)
is inputted to a current-controlled oscillator (45). The input side of the voltage/current
converting circuit (41) is connected to the output side of a loop filter (3), while
the input side of the other voltage/current converting circuit (40) is connected
to an input terminal (8) used for evaluating the oscillation characteristic
of the voltage-controlled oscillator (4). It is, therefore, achieved to effectively
suppress both the temporal variation in output frequency of the PLL circuit and
the temporal variation in voltage of the loop filter that would otherwise occur
due to an arrangement in which the input terminal used for evaluating the oscillation
characteristic of the voltage-controlled oscillator is connected to the loop
filter via a switch.
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Inventors:
SOGAWA KAZUAKI
KINOSHITA MASAYOSHI
YAMADA YUJI
NAKATSUKA JUNJI
KINOSHITA MASAYOSHI
YAMADA YUJI
NAKATSUKA JUNJI
Application Number:
PCT/JP2007/056817
Publication Date:
April 17, 2008
Filing Date:
March 29, 2007
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD (JP)
SOGAWA KAZUAKI
KINOSHITA MASAYOSHI
YAMADA YUJI
NAKATSUKA JUNJI
SOGAWA KAZUAKI
KINOSHITA MASAYOSHI
YAMADA YUJI
NAKATSUKA JUNJI
International Classes:
H03L7/099
Foreign References:
JP2001230667A | 2001-08-24 | |||
JPH0795069A | 1995-04-07 | |||
JP2005354317A | 2005-12-22 |
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (5-7 Hommachi 2-chome, Chuo-k, Osaka-shi Osaka, JP)
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