Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
PLL CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/008672
Kind Code:
A1
Abstract:
According to the present invention, a phase frequency comparator (4) compares a reference signal with an output signal of a variable frequency divider (3), and outputs a frequency UP signal and a frequency DOWN signal according to the comparison result. An AND circuit (9) performs a logical operation on the UP signal and the DOWN signal, and outputs an operation result as a retiming signal CLKretime. A flip-flop circuit (10) holds and outputs an output signal of a frequency control circuit (8) at a timing which is the same as the timing of an output signal of the AND circuit (9). A ΔΣ modulator (7) determines the frequency division ratio of the variable frequency divider (3) corresponding to the output of the flip-flop circuit (10).

Inventors:
TSUTSUMI, Koji (7-3 Marunouchi 2-chome, Chiyoda-k, Tokyo 10, 〒1008310, JP)
YANAGIHARA, Yuki (7-3 Marunouchi 2-chome, Chiyoda-k, Tokyo 10, 〒1008310, JP)
SHIMOZAWA, Mitsuhiro (7-3 Marunouchi 2-chome, Chiyoda-k, Tokyo 10, 〒1008310, JP)
Application Number:
JP2017/024498
Publication Date:
January 10, 2019
Filing Date:
July 04, 2017
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
MITSUBISHI ELECTRIC CORPORATION (7-3 Marunouchi 2-chome, Chiyoda-ku Tokyo, 10, 〒1008310, JP)
International Classes:
H03L7/197
Attorney, Agent or Firm:
TAZAWA, Hideaki et al. (Akasaka Sanno Center Bldg. 5F, 12-4 Nagata-cho 2-chome, Chiyoda-k, Tokyo 14, 〒1000014, JP)
Download PDF: