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Title:
POTENTIAL WELL BASED FDSOI MOSFET (PWFDSOI MOSFET)
Document Type and Number:
WIPO Patent Application WO/2020/212786
Kind Code:
A1
Abstract:
The present invention discloses a device which is a fully depleted silicon on insulator Metal Oxide Semiconductor Field Effect Transistor (FDSOI MOSFET) having transistor gate wherein the device comprises highly doped planar well regions (TS, TD) in the buried oxide (BOX) under source and drain regions giving rise to potential well in the source and drain. These potential wells decrease the OFF current of the device.

Inventors:
QURESHI SHAFI (IN)
MEHROTRA SHRUTI (IN)
Application Number:
PCT/IB2020/052974
Publication Date:
October 22, 2020
Filing Date:
March 28, 2020
Export Citation:
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Assignee:
INDIAN INSTITUTE OF TECH KANPUR (IN)
International Classes:
H01L29/786; H01L21/336; H01L29/40
Other References:
LOAN, SAJAD A. ET AL.: "A novel partial-ground-plane-based MOSFET on selective buried oxide: 2-D simulation study", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 57, no. 3, 1 March 2010 (2010-03-01), pages 671 - 680, XP011300639
RAHIMIAN, MORTEZA ET AL.: "A novel nanoscale MOSFET with modified buried layer for improving of AC performance and self-heating effect", MATERIALS SCIENCE IN SEMICONDUCTOR PROCESSING, vol. 15, no. 4, 1 August 2012 (2012-08-01), pages 445 - 454, XP028504250
Attorney, Agent or Firm:
MAJUMDAR, Subhatosh et al. (IN)
Download PDF:
Claims:
WE CLAIM:

1. A semiconductor device comprising:

a first silicon layer at the bottom of the device constituting a silicon-on-insulator (SOI) to define a substrate; whereby the insulator is a buried oxide (BOX); a ground plane over the first silicon layer (substrate)

wherein the device is fully depleted silicon on insulator Metal Oxide Semiconductor Field Effect Transistor (FDSOI MOSFET) having source region (S), drain region (D), transistor gate (G), CHARACTERIZED IN THAT,

the device further comprises highly doped planar well regions (Ts, TD) in BOX under source (S) and drain (D) regions of the device, adapted to decrease the OFF current of the device.

2. The semiconductor device as claimed in claim 1, comprising a buried oxide (BOX) based transistors, such that BOX is over the ground plane in the device.

3. The semiconductor device as claimed in claim 2, wherein the device comprises highly doped well regions (Ts, TD) placed under the source (S) and drain (D) regions in the buried oxide (BOX).

4. The semiconductor device as claimed in claim 3, wherein the size of the well regions (Ts, TD) is 5 nm depth and 5 nm width.

5. The semiconductor device as claimed in claim 1, optionally comprising on the buried oxide (BOX) a silicon layer along with source region and drain region forming a planar fully depleted silicon creating potential well in the source and drain regions thus improving the IoN-to-IoFF current ratio significantly.

6. The semiconductor device as claimed in claim 1, wherein one kind of doping of the potential well regions (Ts and TD) is 1 X lO20 cm 3.

7. The semiconductor device as claimed in claim 6, wherein the doping of the source region and the drain region is 1 x 1020 cm 3 of opposite type of the doping as of Silicon in the well (Ts and TD).

8. The semiconductor device as claimed in claim 6, wherein the doping for (Ts, TD) is p+ Silicon (for NMOS device).

9. The semiconductor device as claimed in claim 1, wherein the equivalent oxide thickness of the transistor gate (G) is 0.9 nm / 0.65 nm.

10. The semiconductor device as claimed in claim 1, wherein transistor gate (G) is above a layer of Si.

11. The semiconductor device as claimed in claim 10, wherein the layer of Si preferably has a thickness of 5 nm.

12. The semiconductor device as claimed in claim 1, wherein the transistor gate (G) comprises high K (one kind Si02-Hf02) metal gate, spacers in between the gate and the source (S) region and the drain region (D).

13. The semiconductor device as claimed in claim 1, wherein the length of the transistor gate (G) is 20 nm or lesser.

14. The semiconductor device as claimed in claim 1, wherein the gate-to-source and gate- to-drain overlap is 3 nm or lesser.

15. The semiconductor device as claimed in any one of the preceding claims wherein the buried oxide (BOX) is Germanium oxide (GeOx) with Germanium (Ge) channel and source/drain.

16. The semiconductor device as claimed in any one of the preceding claims having unstrained silicon channels.

17. The semiconductor device as claimed in any one of the preceding claims further comprising strained silicon channels.

Description:
TITLE: POTENTIAL WELL BASED FDSOI MOSFET (PWFDSOI MOSFET)

TECHNICAL FIELD OF THE INVENTION

The present subject matter described herein, relates to Silicon-on-Insulator (SOI) devices and particularly, it relates to Metal Oxide Silicon Field Effect Transistor or Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices.

BACKGROUND OF THE INVENTION

MOSFET device forms the backbone of the semiconductor industry around which most electronic products are built. It is known in the art that immense challenges are existent in scaling MOSFET device to 20/10 nm and smaller gate lengths to meet Moore’s law.

These challenges have been further met by scaling the MOSFET device. However, as the MOSFET device is scaled to extreme dimensions such as 20 nm or 10 nm or smaller gate lengths, the device OFF current increases significantly resulting in lowering of Io N -to- IOFF current ratio. This primarily happens due to the phenomenon called the drain induced barrier lowering (DIBL). The DIBL is caused by the lowering of the potential barrier between the source and drain in the channel by the drain voltage. Consequently the gate has lesser control on the current flowing between the source and drain. To meet this challenge at extremely scaled gate length, different devices have been explored having different device structures, one of them being 3D FinFET. The design and fabrication of 3D FinFET device based circuits is quite complex in comparison to planar device based circuits hence there is distinct advantage in having a planar device with comparable characteristics. However, as the conventional FDSOI MOSFET which is a planar device is scaled beyond 20 nm gate length, the ON current-to-OFF current ratio (i.e. Io N -to-Io FF current ratio) degrades significantly thus making it a poor transistor. Thus, it is seen that 3- D device technology poses considerable circuit design and process complexity over planar device technologies which have reached a limit in scaling to these dimensions. Reference is made to US6800910B2 that discloses a FinFET device which employs strained silicon to enhance carrier mobility. In one method, a FinFET body is patterned from a layer of silicon germanium (SiGe) that overlies a dielectric layer. Further, reference is made to US7465999B2 that discloses a fully-depleted (FD) Silicon-on- Insulator (SOI) MOSFET access transistor comprising a gate electrode of a conductivity type which is opposite the conductivity type of the source/drain regions. However, these prior art do not disclose planar device having smaller gate lengths and significantly lesser circuit design, and having lesser process complexity.

Therefore, there is a dire need to provide a planar device having comparable or even better characteristics (such as high ON current-to-OFF current ratio) as that of the 3 D devices at smaller gate lengths (such as 20 nm or 10 nm or even lesser) and also having significantly lesser circuit design and process complexity.

SUMMARY OF THE INVENTION

The following disclosure presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the present invention. It is not intended to identify the key/critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concept of the invention in a simplified form as a prelude to a more detailed description of the invention presented later.

An object of the present invention is to provide fully depleted silicon on insulator (SOI) MOSFET device (FDSOI MOSFET device) having comparable or potentially even better characteristics as that of the 3 D devices at smaller gate lengths.

Another object of the present invention is to provide planar fully depleted silicon on insulator (SOI) MOSFET device having significantly lesser circuit design and process complexity. Yet another object of the present invention is to a simple and economical solution of planar fully depleted silicon on insulator (SOI) MOSFET device having smaller gate length and high ON current- to-OFF current ratio.

Briefly, various aspects of the subject matter described herein are directed at a semiconductor device comprising a bottom silicon layer called substrate , a ground plane over the substrate followed by a buried oxide (BOX) layer on top of the ground plane having wells under the source and drain regions. The wells are filled with heavily doped silicon of opposite doping in comparison to source and drain doping to create potential wells in the source and drain regions. The next layer on the BOX is silicon layer along with source region and drain region forming a planar fully depleted silicon on insulator Metal Oxide Semiconductor Field Effect Transistor (FDSOI MOSFET) having Si0 2 -Hf0 2 gate stack. The potential wells thus created in the source and drain regions play important role in decreasing the OFF current of the device.

Other salient features and advantages of the invention will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, discloses exemplary embodiments of the invention.

BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

The above and other aspects, features, and advantages of certain exemplary embodiments of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings in which:

Figure 1(a) illustrates a conventional FDSOI MOSFET according to the prior art of the present invention.

Figure 1(b) illustrates the absence of potential wells in source region and drain region of a conventional FDSOI MOSFET according to the prior art of the present invention. Figure 2 (a) illustrates 20nm Potential Well based FDSOI MOSFET as per an embodiment of the present invention.

Figure 2 (b) illustrates the potential wells in source region and drain region in 20 nm Potential Well based FDSOI MOSFET as per an embodiment of the present invention.

Figure 2 (c) illustrates the potential wells in source region and drain region in 20 nm Potential Well based FDSOI MOSFET, when channel is inverted, as per an embodiment of the present invention.

Figure 3(a) illustrates 20 nm Potential Well based FDSOI MOSFET having region marked as‘Ts’ only as per an embodiment of the present invention.

Figure 3(b) illustrates the potential wells in 20 nm Potential Well based FDSOI MOSFET having region marked as ‘Ts’ only as per an embodiment of the present invention.

Figure 3(c) illustrates 20 nm Potential Well based FDSOI MOSFET having region marked as‘T D ’ only as per an embodiment of the present invention.

Figure 3(d) illustrates the potential wells in 20 nm Potential Well based FDSOI MOSFET having region marked as ‘T D ’ only as per an embodiment of the present invention.

Figure 3(e) illustrates the I D VS VGS for 20 nm Potential Well based FDSOI MOSFET under different conditions as per an embodiment of the present invention.

Figure 4 illustrates I D VS VGS of 20 nm Potential Well based FDSOI MOSFET as per an embodiment of the present invention and 20 nm reference device as per the prior art.

Figure 5(a) illustrates 12 nm Potential Well based FDSOI MOSFET as per an embodiment of the present invention. Figure 5 (b) illustrates the potential wells in source region and drain region in 12 nm Potential Well based FDSOI MOSFET as per an embodiment of the present invention.

Figure 5 (c) illustrates the potential wells in source region and drain region in 12 nm Potential Well based FDSOI MOSFET, when channel is inverted, as per an embodiment of the present invention.

Figure 6 illustrates I D VS VGS of 12 nm Potential Well based FDSOI MOSFET as per an embodiment of the present invention and 12 nm reference device as per the prior art.

Figure 7 (a) illustrates 10 nm Potential Well based FDSOI MOSFET as per an embodiment of the present invention.

Figure 7 (b) illustrates the potential wells in source region and drain region in 10 nm Potential Well based FDSOI MOSFET as per an embodiment of the present invention.

Figure 7 (c) illustrates the potential wells in source region and drain region in 10 nm Potential Well based FDSOI MOSFET, when channel is inverted, as per an embodiment of the present invention.

Figure 8 illustrates I D VS VGS of 10 nm Potential Well based FDSOI MOSFET as per an embodiment of the present invention and 10 nm reference device as per the prior art.

Figure 9 illustrates noise behavior of 10 nm Potential Well based FDSOI MOSFET as per an embodiment of the present invention and 10 nm reference device as per the prior art.

Persons skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and may have not been drawn to scale. For example, the dimensions of some of the elements in the figure may be exaggerated relative to other elements to help to improve understanding of various exemplary embodiments of the present disclosure. Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of exemplary embodiments of the invention. It includes various specific details to assist in that understanding but these are to be regarded as merely exemplary.

Accordingly, those skilled in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the invention. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness.

The terms and words used in the following description are not limited to the bibliographical meanings, but, are merely used by the inventor to enable a clear and consistent understanding of the invention. Accordingly, it should be apparent to those skilled in the art that the following description of exemplary embodiments of the present invention are provided for illustration purpose only and not for the purpose of limiting the invention as defined by their equivalents.

It is to be understood that the singular forms“a,”“an,” and“the” include plural referents unless the context clearly dictates otherwise.

By the term“substantially” wherever used or will be used later it is meant that the recited characteristic, parameter, or value need not be achieved exactly, but that deviations or variations, including for example, tolerances, measurement error, measurement accuracy limitations and other factors known to those of skill in the art, may occur in amounts that do not preclude the effect the characteristic was intended to provide. Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments and/or in combination with or instead of the features of the other embodiments.

It should be emphasized that the term“comprises/comprising” when used in this specification is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

A conventional fully depleted silicon on insulator Metal Oxide Semiconductor Field Effect Transistor (FDSOI MOSFET) with ground plane henceforth referred to as the reference device having no doped regions (Ts and TD ) is shown in Figure 1(a). Also, in Figure 1(b) is shown the potential well along the cutline Z-Z\ As can be seen from Figure 1(b), no potential well exists in the source and drain region.

In one embodiment, the present invention discloses a planar potential well based fully depleted silicon on insulator (FDSOI) MOSFET (acronym as PWFDSOI MOSFET) which has been realized by applying new device physics. The device disclosed in the present invention comprises potential wells (PW) in the source region and the drain region of the MOSFET. The device disclosed in the present invention comprises a novel planar PWFDSOI MOSFET device based on new device physics suitable for 20/10 nm and smaller gate lengths.

Figure 2(a) discloses FDSOI MOSFET device in accordance with an embodiment of the present invention. The device comprises well regions (Ts, TD) in the buried oxide (BOX) layer. It discloses a semiconductor device comprises silicon layer (substrate), a ground plane over substrate followed by the buried oxide (BOX) layer on top having wells Ts and TD. The well regions (Ts, TD) are placed in the buried oxide under the source /drain of the device as shown in Figure 2(a) and filled with highly doped silicon of opposite doping in comparison to source and drain region doping giving rise to formation of potential well in the source and drain regions of the device. The silicon layer (Si) is placed on top of the BOX layer along with source (S), drain (D) and the gate stack (Si02-Hf0 2 ) metal gate (G) to realize an FDSOI transistor. The creation of potential well in the source and drain regions resulting from doped regions (Ts, T D ) decreases the OFF current of the device significantly. The length of the transistor gate (L g ) as per this embodiment is 20 nm. The transistor gate may be composed of materials known in the prior art such S1O2, Hf0 2 . The device may have the thickness of the ground plane as 10 nm and the thickness of BOX layer as 10 nm. The Equivalent Oxide Thickness (EOT) of the transistor gate (G) may be 0.9 nm.

The transistor gate (G) is embedded in between the raised source (S) and the drain (D) regions. The device may comprise of spacers in between the gate stack and the source and the drain regions as seen in Figure 2(a). The source region and the drain region may be adapted to connect to ohmic contacts. Below the transistor gate is present a layer of Si, having a preferable thickness of 5 nm. This said layer of Si may be spaced a distance (preferably 6 nm) away from the wells Ts and T D .

The doped regions Ts and T D in the buried oxide give rise to potential well in the source and drain regions of the device in accordance with the basic device physics as is shown in Figure 2(b) and Figure 2(c) for different conditions when seen along the cutline Z-Z’ shown in Figure 2(a). On one side of the cutline Z-Z’ are the substrate, the ground plane, BOX including Ts and T D and the other side of the Z-Z’ are present the transistor gate (G), the raised source region, the raised drain region, the layer of Si below the transistor gate (G) and the spacers. The device of Figure 1(a) and the device of Figure 2(a) differ in the presence of the doped regions (Ts and T D ) under the source and drain regions.

For the 20 nm PWFDSOI MOSFET, the Ts and T D regions may be doped as 1 x 10 20 cm 3 . The source and drain regions may be doped with 1 x 10 20 cm 3 of opposite type. For instance the doping of Ts and T D may include p+ Silicon for negative channel metal oxide semiconductor (NMOS) device. The gate-to- source and gate-to-drain overlap may be 3 nm. Figure 2(b) shows the potential wells in the source region and drain region in 20 nm PWFDSOI MOSFET device and Figure 2(c) shows potential wells in source and drain regions in 20 nm PWFDSOI MOSFET when channel is inverted. The well regions Ts and T D of the device are preferably having size 5 nm depth x 5 nm width in the buried oxide (BOX) under the source and drain. By virtue of the basic semiconductor device physics, these doped regions result in the creation of potential well in the source and drain regions which are effective in reducing the OFF current of the device while the ON current of the device is marginally changed resulting in higher Io N -to-Io FF current ratio as the device is scaled to 20 nm and smaller gate lengths. A 10 nm gate length PWFDSOI MOSFET has Io N -to-Io FF current ratio of over 7 x 10 5 in comparison to about 250 for the conventional planar FDSOI MOSFET with ground plane for unstrained silicon channel. The PWFDSOI MOSFET device also has better Sub-threshold swing (SS) characteristics of 87 mV/decade in comparison to that of conventional planar FDSOI MOSFET which has SS of 144 mV/decade. This feature of potential well concept has also been applied to PMOS version of the device and the results are observed to be consistent.

The herein disclosed PWFDSOI MOSFET devices have been simulated using a simulation tool which confirmed the validity of the present invention that is directed at the formation of the potential wells in the source region and drain region. The observations have been reported here. The formation of the potential wells explains the lowering of the OFF current when a 20 nm gate length device is in OFF state for V GS =0 V, V DS =50 mV and V BS =0 V, where V GS is the gate to source voltage, V DS is the drain to source voltage and V BS is the source bias voltage. Also shown are the potential wells for V GS =0.9 V, V DS =50 mV and V BS =0 V when 20 nm device is in ON state. The gate stack used herein is a high-K metal gate.

The clear demonstration of the role of the potential wells in controlling the OFF state current can be observed when only one doped region Ts or T D is present. Figure 3(a) shows the cross sectional view of the PWFDSOI MOSFET when only Ts is present. Figure 3(b) shows the potential well for the device shown in Figure 3(a). Figure 3(c) is the cross sectional view of PWFDSOI MOSFET when only the doped region of drain (T D ) is present and Figure 3(d) shows the corresponding potential well diagram. The I D VS V GS plots of the PWFDSOI MOSFETs are shown in Figure 3(e) for V DS =0.9 V and V BS =0 V, where I D is the current in the drain. It can be seen that the OFF current at V GS =0 V is lower for the case when doped region of drain (T D ) is present and doped region of source (Ts) is absent than in the case when doped region of source (Ts) is present and doped region of drain (TD) is absent.

The above observation implies that most carriers generated in the device by thermal generation end up in the well created by doped region of drain (T D ) than in case when doped region of source (Ts) is present and most thermally generated carriers are collected by the drain contributing to higher leakage current.

The drain current ID VS VGS characteristics of PWFDSOI MOSFET of 20 nm gate length are shown in Figure 4. The ID VS VGS of existing 20 nm FDSOI MOSFET reference device (prior art) is also shown for comparison. Table 1 given below provides a comparison of the parameters of interest of PWFDSOI MOSFET with the reference device.

Table 1: LG = 20 nm (14 nm node), VDS = 0.9 V, VBS = -1.0 V

In another embodiment of the present invention, the gate length of PWFDSOI MOSFET is scaled to 12 nm as shown in Figure 5(a). The potential wells in this device are shown in Figure 5(b) and Figure 5(c), wherein Figure 5(c) is when channel is inverted.

A comparison of ID VS VGS characteristics of 12 nm gate length PWFDSOI MOSFET and FDSOI MOSFET reference device (prior art) is shown in Figure 6. The ION- to-Io FF current ratio of 9 x 10 5 is observed for PWFDSOI MOSFET device for EOT of 0.65 nm as shown in Table 2. The Io N -to-Io FF current ratio of approx. 4 x 10 3 is seen in case of FDSOI MOSFET reference device. Table 2: LG = 12 nm (8 nm node), YDS = 0.7 V, VBS = -1.0 V

Further, in another embodiment of the present invention is shown in Figure 7(a) having scaling of the PWFDSOI device to gate length of 10 nm. The potential wells in this are shown in Figures 7(b) and 7(c), where Figure 7(c) is when channel is inverted.

A comparison of ID VS VGS characteristics of 10 nm gate length PWFDSOI MOSFET and FDSOI MOSFET reference device is shown in Figure 8. The Io N -to-Io FF current ratio of approx. 7 x 10 5 is seen for PWFDSOI MOSFET. The Io N -to-Io FF current ratio of 10 nm gate length FDSOI MOSFET reference device is approximately 250.

The device parameters of 10 nm gate length PWFDSOI MOSFET are compared with 10 nm gate length FDSOI MOSFET reference device (prior art) in Table 3. Table 3 also shows device parameters of a 3 D FinFET of comparable technology node (7 nm) found in the literature. It is significant to note that the planar PWFDSOI MOSFET of the present invention is on the verge of competing with 7 nm node FinFET which is a 3 D device.

Table 3: LG = 10 nm (6 nm node), VDS = 0.7 V, VBS = -1.0 V

The high frequency noise of PWFDSOI MOSFET is marginally higher in comparison to FDSOI MOSFET reference device as shown in Figure 9.

Some of the noteworthy features of the present invention are mentioned below:

1) The invention discloses a novel planar device having comparable or better characteristics at 20/10 nm and smaller gate length and significantly lesser circuit design and process complexity when compared to 3D FinFET.

2) The present invention provides characteristics that can be comparable to 3D device namely FinFET.

3) The gate length can be scaled down to 20 nm or even less and attain the desired current and voltage characteristics.

4) The Io N -to-Io FF current ratio of the device as per the present invention shows significant improvement over conventional FDSOI MOSFET.

Some of the non-limiting advantages of the present invention over the prior art are mentioned below:

1) The present invention can be used for fabrication of processor chips, memory blocks etc. for computers, fabrication of chips for cell phones, fabrication of chips for electronic system and the like.

2) With the present invention aggressively scaled planar MOSFET is realizable. 3) It is simple in its construction and is economical as compared to the solution of the prior art at extremely scaled technology nodes.