Title:
POWER AMPLIFICATION CIRCUIT, HIGH-FREQUENCY CIRCUIT, AND COMMUNICATION DEVICE
Document Type and Number:
WIPO Patent Application WO/2021/157152
Kind Code:
A1
Abstract:
The objective of the present invention is to suppress gain. In a power amplification circuit (10), a first transistor (Q1) has a first input terminal (11), a first output terminal (12), and a first ground terminal (13). A second transistor (Q2) has a second input terminal (21), a second output terminal (22), and a second ground terminal (23). The second input terminal (21) is connected to the first input terminal (11). The second output terminal (22) is connected to the first output terminal (12). A first bias circuit (5) is connected to the first input terminal (11). A second bias circuit (6) is connected to the second input terminal (21). A first resistor (R1) is connected between the first ground terminal (13) and ground. A second resistor (R2) is connected between the second ground terminal (23) and ground. The resistance value of the second resistor (R2) is greater than the resistance value of the first resistor (R1).
Inventors:
TAHARA KENJI
SHIMAMOTO KENICHI
YAMADA TAKASHI
SHIMAMOTO KENICHI
YAMADA TAKASHI
Application Number:
PCT/JP2020/041763
Publication Date:
August 12, 2021
Filing Date:
November 09, 2020
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H03G3/10; H03F1/02; H03F1/56; H03F3/24; H03F3/68; H04B1/04
Domestic Patent References:
| WO2002056461A1 | 2002-07-18 |
Foreign References:
| CN103338009A | 2013-10-02 | |||
| US20070096823A1 | 2007-05-03 | |||
| US20180358933A1 | 2018-12-13 | |||
| CN104022741A | 2014-09-03 | |||
| JP2003046340A | 2003-02-14 |
Attorney, Agent or Firm:
HOKUTO PATENT ATTORNEYS OFFICE (JP)
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