Title:
POWER AMPLIFIER CIRCUIT FOR TIME DIVISION DUPLEX MODE
Document Type and Number:
WIPO Patent Application WO/2019/000426
Kind Code:
A1
Abstract:
A power amplifier circuit for a time division duplex mode. The power amplifier circuit comprises a power amplifier bias circuit (1) and a time division duplex switching circuit (2); the power amplifier bias circuit (1) is used for generating a constant quiescent current in a power amplifier; the power amplifier bias circuit (1) comprises a first field effect transistor and a second field effect transistor; moreover, the first field effect transistor and the second field effect transistor form a mirror current source; the time division duplex switching circuit (2) is used for switching the resistance of a gate circuit connected in series to the power amplifier bias circuit (1). The power amplifier circuit keeps the quiescent current constant in a radio frequency amplifier while meeting the requirements of fast time division duplex switching, is implemented by simple and low-cost components, and uses a chip that is easy to integrate into a power transmitter, and the cost is low.
Inventors:
LI FENG (CN)
Application Number:
PCT/CN2017/091244
Publication Date:
January 03, 2019
Filing Date:
June 30, 2017
Export Citation:
Assignee:
NOKIA SHANGHAI BELL CO LTD (CN)
International Classes:
H03F3/20
Foreign References:
| CN200959590Y | 2007-10-10 | |||
| CN1905356A | 2007-01-31 | |||
| CN101478293A | 2009-07-08 | |||
| US20060055447A1 | 2006-03-16 |
Attorney, Agent or Firm:
HANHOW INTELLECTUAL PROPERTY (CN)
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