POWER AMPLIFIER CIRCUIT

TECHNICAL FIELD

The present invention relates to power amplifier circuits. BACKGROUND

Power amplifiers in wireless communications consume a lot of power, which results in that high direct currents are drawn from the supply and that the metal wires in the circuit have to handle high direct current densities. One problem with high direct current (DC) density is that it causes damages in metal wires in the circuit due to electromigration.

To reduce the impact of electromigration the wires are generally made wide in order to reduce the effective current density, but at the cost of increased chip area and parasitic capacitances that degrade performance. In addition, on-chip inductors and transformers typically have a metal wire width limitation set by electromagnetic design considerations.

In more detail, for integrated radio frequency (RF) Complementary Metal Oxide

Semiconductor (CMOS) power amplifiers it is a challenge to get a large direct current from the higher metal layers down to the lowest metal layer, which connects to the drain and source junctions of the device. Moreover, in many application areas (such as e.g. safety technologies, medical equipment) reliability is critically important, wherefore electromigration effects must be considered when designing the circuits. This is especially important in applications where functionality for many years must be guaranteed. Conventionally, to ensure reliability, the metal wires are widened such that they can handle the direct current (DC) also at high temperatures. However, wider metal wires increase layout parasitic capacitance and increases the chip area, which becomes costly in modern CMOS processes. In some cases, silicon vendors even develop special transistor layouts for power amplifiers with wider source and drain to better handle the DC levels.

Further, another problem associated with widening of the metal wires is electromagnetic design considerations for e.g. inductors or transformers at the output of the power amplifier. At high output power and frequency, a very small inductance is required to resonate with the parasitic capacitances at the output. Thus, a small diameter on-chip inductance must be used, and that may be impossible with large wire widths.

Moreover, as operating frequency continues to increase, the effects of capacitive parasitics due to the metal wires also increase, and therefore it is desirable to reduce their width as much as possible. At mm-wave frequencies it is preferred that the smaller chip area also results in shorter wires and less inductive parasitics.

There is therefore a need for an improved circuit solution for reducing the adverse effects of electromigration in circuit components operating with high direct currents.

SUMMARY

It is therefore an object of the present invention to provide a power amplifier circuit, a transmitter/receiver circuit, a communication apparatus, and a method for controlling a power amplifier, which alleviate all or at least some of the above-discussed drawbacks of presently known systems.

This object is achieved by means of a power amplifier circuit, a transmitter circuit, a communication apparatus, and method as defined in the appended claims. The term exemplary is in the present context to be understood as serving as an instance, example or illustration.

The present invention is at least partly based on the realization that because damages due to electromigration are caused by the DC current that flows through power amplifiers, one can mitigate this effect by periodically reverting the bias current (DC current) direction (for example when the power amplifier is idle). The reversal of current direction may for example be realized by swapping/inverting the VDD/GND pins of the bias arrangement. The proposed solution is applicable to any amplifiers that do not require continuous operation. Moreover, the present inventors realized that the effective supply voltage during the "reversed mode" (referred to as the second mode in the following) can be reduced in order to reduce power consumption. Moreover, the gate bias points of the power amplifiers can be modified so that the time integral of the "reverse current" approximately matches the time integral of the "active current". An advantage of the proposed solution is that thinner and narrower metal wires can be used in power amplifier circuits. Also, the product life-time and performance can be increased and at a reduced cost as compared to conventional solutions. Furthermore, the use of thinner and narrower wires may in turn improve electrical performance, especially at higher operating frequencies by reducing parasitic capacitances. Moreover, the proposed solution addresses damages caused by electromigration in both active and passive devices.

According to a first aspect of the invention, there is provided a power amplifier circuit having a first mode and a second mode. The power amplifier circuit comprises a power amplifier connected to a first voltage supply rail and a second voltage supply rail, and a control circuit. The control circuit is configured to, in the first mode, apply a first DC voltage having a first polarity between the first voltage supply rail and the second voltage supply rail in order to obtain a first bias current through the power amplifier. The control circuit is further configured to, in the second mode, apply a second DC voltage having a second polarity between the first voltage supply rail and the second voltage supply rail in order to obtain a second bias current through the power amplifier, the second bias current having an opposite direction relative to the first bias current.

The terms first bias current and second bias current is in the present context to be understood as a first DC current and a second DC current, respectively.

The control unit can be realized as a software controlled processor. However, the control circuit may alternatively be realized wholly or partly in hardware. Moreover, the first mode can be construed as an "active mode", i.e. a mode in which the amplifier is to operate as intended by the application, while the second mode can be construed as a "healing mode", which serves to reverse or mitigate the effects of electromigration caused by the biasing in the "active mode". The power amplifier may be any type of suitable electronic power amplifier configured to increase the power available to a load, and where the application does not require the power amplifier to operate continuously but is allowed to be "off" during recurring time periods, so that the proposed solution can utilize the "off" time to reverse the bias current.

According to an exemplary embodiment, the power amplifier has at least one gate bias terminal, and each gate bias terminal is connected to a corresponding DC voltage supply. The control circuit is connected to each corresponding DC voltage supply in order to control the output voltage of each DC voltage supply. In more detail, the control circuit is configured to control each corresponding DC voltage supply such that a time integral of the second bias current during the second mode is within a range of 60 % to 140% of a time integral of the first bias current during the first mode. Preferably, the time integral of the second bias current during the second mode is within a range of 75% and 125% of the time integral of the first bias current during the first mode. More preferably, the time integral of the second bias current during the second mode is within a range of 80% and 120% of the time integral of the first bias current during the first mode.

By controlling the gate bias voltages of the power amplifier, one provides a simple and efficient means for ensuring that the time integrals of the first and the second bias currents in the first and second modes are approximately the same, and thereby optimizing the "healing effect" of the bias current reversal.

According to a second aspect of the present invention, there is provided a transmitter/receiver circuit comprising the power amplifier circuit according to the first aspect of the present invention. With this aspect of the invention, similar advantages and preferred features are present as in the previously discussed first aspect of the invention.

Further, according to a third aspect of the present invention, there is provided a communication apparatus comprising the transmitter/receiver circuit according to the second aspect of the invention. With this aspect of the invention, similar advantages and preferred features are present as in the previously discussed aspects of the invention. The communication apparatus may for example be a wireless terminal for a cellular communication system (e.g. mobile phone, tablet, or the like), or a radio base station for a cellular communication system.

According to a fourth aspect, there is provided a method for controlling a power amplifier. The method comprises applying a first bias current through the power amplifier in a first mode of operation, and applying a second bias current through the power amplifier in a second mode of operation, the second bias current having an opposite direction relative to the first bias current. With this aspect of the invention, similar advantages and preferred features are present as in the previously discussed aspects of the invention. The bias currents may for example be applied by applying a first DC voltage across the power amplifier in the first mode of operation, and a second DC voltage across the power amplifier in the second mode of operation. The first and second voltages having opposite polarities.

Moreover, in accordance with an exemplary embodiment of the present invention, the method further comprises applying and controlling a gate bias voltage of the power amplifier such that a time integral of the second bias current during the second mode is within a range of 60 % to 140% of a time integral of the first bias current during the first mode. Preferably, the time integral of the second bias current during the second mode is within a range of 75% and 125% of the time integral of the first bias current during the first mode. More preferably, the time integral of the second bias current during the second mode is within a range of 80% and 120% of the time integral of the first bias current during the first mode.

Further embodiments of the invention are defined in the dependent claims. It should be emphasized that the term "comprises/comprising" when used in this specification is taken to specify the presence of stated features, integers, steps, or components. It does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof.

These and other features and advantages of the present invention will in the following be further clarified with reference to the embodiments described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

Further objects, features and advantages of embodiments of the invention will appear from the following detailed description, reference being made to the accompanying drawings, in which:

Fig. 1 is a schematic illustration of a communication environment.

Fig. 2 is a schematic illustration of a transmitter circuit.

Figs. 3 -5 are schematic illustrations of embodiments of a power amplifier circuit.

Fig. 6a is a schematic illustration of the power amplifier circuit of Fig. 3 in a first mode. Fig. 6b is a schematic illustration of the power amplifier circuit of Fig. 3 in a second mode.

Figs. 7 - 9 are schematic illustrations of embodiments of a power amplifier.

Fig. 10 shows (a) a power consumption of the power amplifier in Figs. 3, 6a, and 6b in the two operating modes, (b) a bias current through the power amplifier in the two operating modes, and (c) the voltage levels of the voltage rails connected to the power amplifier in the two operating modes.

Fig. 11 is a flow chart representation of a method for controlling a power amplifier.

DETAILED DESCRIPTION

Fig. 1 illustrates a communication environment wherein embodiments of the present invention may be employed. A wireless terminal 20 of a cellular communication system is in wireless communication with a radio base station 21 of the cellular communication system. The wireless terminal 20 may be what is generally referred to a user equipment (UE). The wireless terminal 20 is depicted in Fig. 1 as a mobile phone, but may be any kind of device with cellular communication capabilities, such a tablet or laptop computer, machine-type communication, MTC, device, or similar. Furthermore, even though a cellular communication system is used as an example throughout this disclosure, embodiments of the present invention may be applicable in other types of systems as well, such as but not limited to Wi-Fi systems.

The radio base station 21 and wireless terminal 20 are examples of what in this disclosure is generically referred to as communication apparatuses. Embodiments as described in the following may suitably be used in such and other communication apparatuses. However, as mentioned, embodiments of the present invention are applicable in other electronic devices as well.

Fig. 2 schematically illustrates a transmitter circuit 30, which may for example be comprised in a communication apparatus such as the wireless terminal 20 or radio base station 21. The transmitter circuit 30 has a power amplifier circuit 1 having a power amplifier that is configured to feed a signal to be transmitted to a transmission antenna 8 of for example a communication apparatus. The power amplifier circuit 1 may be preceded by various different circuitry, well known in the art of radio transmitter design, and the present disclosure is not limited to any particular such circuitry, as indicated by the dotted line in Fig. 2.

Fig. 3 illustrates a power amplifier circuit 1 having a first mode and a second mode according to an example embodiment of the present invention. The power amplifier circuit 1 comprises a differential input power amplifier 2 connected to a first voltage supply rail 3 and to a second voltage supply rail 4. Each voltage supply rail 3, 4 may be connected to one or more DC voltage sources 11, 12 (as will be further exemplified in the embodiments to follow). The power amplifier circuit 1 further comprises a control circuit 10 configured to, in the first mode, apply a first DC voltage having a first polarity between the first voltage supply rail 3 and the second voltage supply rail 4 in order to obtain a first bias current (first DC current) through the power amplifier 2. The control circuit 10 is further configured to, in the second mode, apply a second DC voltage having a second polarity between the first voltage supply rail 3 and the second voltage supply rail 4 in order to obtain a second bias current (second DC current) through the power amplifier 2. However, the second bias current flows in an opposite direction as compared to the first bias current. In other words, the first and second DC voltages are of opposite polarity.

By periodically reversing the bias current through the power amplifier 2 it is possible to mitigate damages caused by electromigration, which in turn enables use of thinner and narrower metal wires in the power amplifier 2. An additional advantage is that the product life time can be increased. Moreover, the use of thinner and narrower metal wires will may in turn enable improved electrical performance, especially at higher operating frequencies.

Further, in some circuit applications with high operating frequencies and high output power, realization of coils that are capable of handling the tough reliability requirements for DC will be close to impossible in conventional amplifier circuits. However, by utilizing the proposed solution, with a second mode that applies a reversed bias current, i.e. a current that flows in the opposite direction as compared to an "active" mode, the metal wires in the coil can be optimized for highest electromagnetic performance without being constrained by

electromigration concerns. Moreover, by using a second DC voltage in the second mode, which is lower than the first DC voltage used in the first mode, the power consumption for running the amplifier circuits in the second mode according to the proposed invention, will be negligible or at least very limited.

The switching between the first mode and the second mode of the power amplifier circuit 1 as illustrated in Fig. 3 is effectively achieved by controlling the switches 13a, 13b which are used to connect and disconnect the second voltage rail 4 to ground or to a DC voltage source 12. In more detail, the amplifier circuit 1 has a first DC voltage source 11 connected to the first voltage supply rail 3. The first DC voltage source 11 is arranged to provide a first electric potential to the first voltage supply rail 3. The power amplifier circuit further has a second voltage source 12 connected to the second voltage supply rail via a first switch 13b. The second DC voltage source 12 is arranged to provide a second electric potential to the second voltage supply rail 4, where the second electric potential is higher than the first electric potential. However, as the skilled person readily understands, other circuit arrangements to realize the first mode and the reverse-biasing of the second mode are feasible, as will be elaborated upon in reference to the exemplary embodiments illustrated in Figs. 4 and 5.

Moving on, in Fig. 3, the second voltage rail is connected to ground via a second switch 13a. The control circuit 10 is connected to the first switch 13b and to the second switch 13a. The term connected, in reference to the control circuit 10, is in the present context to be interpreted broadly, and may be construed as "operatively connected", and encompasses direct, indirect, wired and wireless connections. The control circuit 10 is accordingly configured to (in the first mode) open the first switch 13b and close the second switch 13a in order to connect the second voltage rail 4 to ground. Moreover, the control circuit 10 is configured to (in the second mode) close the first switch 13b and open the second switch 13a in order to connect the second voltage rail 4 to the second DC voltage source 12. As the skilled reader realizes that the above does not specify a specific order of the switches 13a, 13b are operated. Naturally, the switches 13b, 13b are such they are not closed simultaneously since this would short circuit the second DC voltage source 12.

In an exemplary embodiment, the magnitude of the second voltage is lower than a magnitude of the first DC voltage. This is in order to reduce power consumption in the second mode, which may be referred to as a healing mode. In reference to the illustrated example of Fig. 3, the first DC voltage source 11 may be arranged to provide an output voltage of 4V. Accordingly, when the amplifier circuit 1 is in the first mode (second switch 13a is closed and first switch 13b is open), a voltage of +4V is applied between the first voltage supply rail 3 and the second voltage supply rail 4. The second DC voltage source 12 may in turn be arranged to provide 5V, such that when the amplifier circuit is in the second mode (second switch 13a is open and first switch 13b is closed), a voltage of -IV (4V - 5V = -IV) is applied between the first voltage supply rail 3 and the second voltage supply rail 4. Thus, the second voltage is here the difference between the output voltages of the first voltage source 11 and the second voltage source 12.

The first mode and the second mode of the amplifier circuit may be understood as an active mode and a healing mode, respectively, where the term "healing" refers to a mitigation of the negative effects of electromigration during the active mode. In an exemplary embodiment, when the amplifier circuit 1 is employed in a transmitter circuit (30 in Fig. 2), the control circuit 10 can be configured to operate the amplifier circuit 1 in the first mode while the transmitter circuit 30 is transmitting. Then, the control circuit 10 can be configured to operate the amplifier circuit 1 in the second mode while the transmitter circuit 30 is inactive. Thereby, the negative effects of electromigration in the power amplifier 2 can effectively be mitigated without affecting the use of the device, e.g. transmitter circuit that the amplifier circuit 1 is employed in.

Further, the power amplifier 2 has two input terminals 9a, 9b, where one input terminal is arranged to receive a negative component "inn" of the differential input voltage, and the other is arranged to receive a positive component "inp" of the differential input voltage. The power amplifier 2 has two gate bias terminals, each connected to a corresponding DC voltage supply 6, 7 in order to provide a gate bias voltage to the transistors (see e.g. Fig. 7) of the differential power amplifier 2. In the present description different terms are used for the DC voltage sources 11, 12 and the DC voltage supplies 6, 7 in order to increase readability and to differentiate between the bias voltage applied to the voltage rails 3, 4 and the gate bias voltage. The skilled reader however readily understands that these components are analogous in terms of function and structure.

Moving on, the control circuit 10 is connected to each DC voltage supply 6, 7 and may be configured to control each DC voltage supply 6, 7 such that a time integral of the second bias current during the second mode is within a range of 60% to 140% of a time integral of the first bias current during the first mode. In other words, the control circuit 10 may be configured to control the gate bias so that a total current of the two time periods representing the first and the second modes sums up to approximately zero. Preferably, the control circuit 10 is configured to control each DC voltage supply 6, 7 such that the time integral of the second bias current during the second mode is within a range of 75% to 125% of the time integral of the first bias current during the first mode. However, even more preferably, the control circuit 10 is configured to control each DC voltage supply 6, 7 such that the time integral of the second bias current during the second mode is within a range of 80% to 120% of the time integral of the first bias current during the first mode.

The closer to 100% (i.e. time integrals of the bias currents in the first and second modes being closer to equal), the better the negative effects of the electromigration can be mitigated. However, preferably the control circuit 10 is configured to control each corresponding DC voltage supply 6, 7 such that a magnitude of the second bias current is lower than a magnitude of the first bias current. In other words, the time integral of the second bias current should rather be in the lower half of the above-mentioned ranges than the upper halves in order to reduce power consumption.

The present invention is at least partly based on the realization that because damages due to electromigration are caused by the DC current that flows through power amplifiers, one can mitigate this effect by periodically reverting the bias current direction (for example when the power amplifier is idle). The proposed solution is applicable to any amplifiers that do not require continuous operation. Moreover, the present inventors realized that the effective supply voltage during the "reversed mode" (referred to as the second mode in the following) can be reduced in order to reduce power consumption. Moreover, the gate bias voltages of the power amplifiers can be modified so that the time integral of the "reverse current" approximately matches the time integral of the "active current".

Fig. 4 is a schematic illustration of a power amplifier circuit in accordance with another exemplary embodiment of the present invention. Many features and structural components are the same or similar to the ones disclosed in reference to Fig. 3, wherefore some details, for the sake of brevity, will be omitted. For example, the amplifier circuit 1 in Fig. 4 also comprises a power amplifier 2 connected to a load 8, where the power amplifier 2 has two inputs 9a, 9b to receive the positive and negative components of a differential input voltage. Instead, the discussion in reference to Fig. 4 will focus on the differing features, i.e. the features related to the switching between the first mode and the second mode.

Accordingly, the power amplifier circuit 1 has a DC voltage source 11 connected to the first voltage rail 3 via a first switch 14a and to the second voltage rail 4 via a second switch 14b. Moreover, the first voltage rail 3 is connected to ground via a third switch 14c, and the second voltage rail 4 is connected to ground via a fourth switch 14b. The control circuit 10 is accordingly connected to each of the first, second, third, and fourth switch 14a-d. The term connected, in reference to the control circuit 10, is in the present context to be interpreted broadly, and may be construed as "operatively connected", and encompasses direct, indirect, wired and wireless connections.

The control circuit 10 is configured to (in the first mode) close the first switch 14a, close the fourth switch 14d, open the second switch 14b and open the third switch 14c. Thereby, the first voltage rail 3 is connected to DC voltage source 11, and the second voltage rail 4 is connected to ground in the first mode. Moreover, the control circuit 10 is configured to (in the second mode) to open the first switch 14a, open the fourth switch 14d, close second switch 14b, and close the third switch 14c. Thereby, the first voltage rail 3 is connected to ground and the second voltage rail 4 is connected to the DC voltage source 11. In other words, the DC voltage between the first voltage rail 3 and the second voltage rail 4 is reversed in the first and the second mode and the bias current hence flows in opposite directions in the two modes. The DC voltage source 11 may be a variable voltage source, such that a magnitude of the DC bias voltage between the first and second voltage rails 3, 4 is lower in the second mode as compared to the first mode. As the skilled person realizes, the control circuit 10 may be configured to control the gate bias levels of the power amplifier 2 in order to ensure that the bias currents through the amplifier are at approximately the same level in the two modes as discussed in the foregoing. As mentioned in reference to Fig. 3, the skilled reader realizes that the switches 14a-d are operated so to avoid short circuiting of any DC voltage sources.

Fig. 5 is a schematic illustration of a power amplifier circuit in accordance with another exemplary embodiment of the present invention. In particular, Fig. 5 serves to illustrate another alternative realization to provide the switching between the first and second modes of the power amplifier circuit 1. Thus, repetition of features shared with the previous exemplary embodiments discussed in reference to Figs. 3 and 4 will for the sake of brevity be omitted.

Moving on, in Fig. 5, the power amplifier circuit 1 comprises a first DC voltage source 15 connected to the first voltage rail 3 via a first switch 17a. The first DC voltage source 15 is arranged to provide a first electric potential to the first voltage supply rail 3. The amplifier circuit 1 further comprises a second DC voltage source 16 connected to the first voltage rail 3 via a second switch 17b. The second DC voltage source 16 is arranged to provide a second electric potential to the first voltage supply rail. The second electric potential has an opposite polarity in reference to the first electric potential. For example, if the first electric potential, provided by the first DC voltage source 15, is 5V, then the second electric potential, provided by the second DC voltage source 16 can be -2V, -3V, -5V, and so forth. The second voltage rail 4 is grounded (i.e. connected to ground).

The control circuit 10 is connected to the first switch 17a and to the second switch 17b. The term connected, in reference to the control circuit 10, is in the present context to be interpreted broadly, and may be construed as "operatively connected", and encompasses direct, indirect, wired and wireless connections. In other words, the control circuit 10 is arranged to control the operation (open or closed) of the switches 17a, 17b. Moreover, the control circuit 10 is configured to (in the first mode) close the first switch 17a and to open the second switch 17b in order to connect the first DC voltage source to the first voltage rail 3. However, in the second mode, the control circuit 10 is configured to open the first switch 17a and to close the second switch 17b in order to connect the second DC voltage source to the first voltage rail. Thereby, the bias current through the power amplifier 2 is effectively reversed in the second mode as compared to the first mode, and the negative effects of electromigration occurring during the first mode may, at least partly, be reversed in the second mode.

Figs. 6A and 6B are schematic illustrations showing the effective bias points VI and V2 in the first mode and second mode of the power amplifier circuit in Fig. 3. As shown in Fig. 6a, when the power amplifier circuit 1 is operating in the first mode, the first voltage rail 3 is supplied with a voltage VI provided by the first DC voltage source 11, and the second voltage rail 4 is grounded. In Fig. 6B, the power amplifier circuit is operating in the second mode and the second voltage rail is supplied with a voltage V2 provided by the second voltage source 12. By selecting the voltage sources 11, 12 such that V2 > VI, the bias current will flow in the opposite direction in the second mode as compared to the bias current in the first mode.

In an exemplary embodiment, the control circuit is configured to operate the power amplifier circuit in the second mode for a total time of less than 0.5 seconds. Preferably, the control circuit is configured to operate the power amplifier in the second mode for a total time of less than 0.5 ms. Assuming that the total time of operation in both the first mode and the second mode is 1 ms, which would correspond to the time period 1/f, where f is the frequency. Also, assuming that the currents are balanced, it would correspond to an alternating current, AC, having a frequency of approximately 1 kHz flowing through the power amplifier. Balanced is in the present context to be understood as that the time integral of the second bias current (i.e. bias current in the second mode) is approximately equal to the time integral of the first bias current (i.e. bias current in the first mode).

Fig. 7 shows a schematic circuit realization of a power amplifier (e.g. ref 2 in Figs. 3 - 6b). Here, the power amplifier is in the form of a differential cascode amplifier, which is connected to a load 8 (e.g. an antenna) via a transformer 5. In more detail, the differential cascode amplifier comprises two metal-oxide-semiconductor, MOS, cascode stages, where each cascode stage has a pair of transistors 70a-d. Each cascode stage has an "input transistor" (common source transistor) 70c, 70d, whose drain terminal is connected to a source terminal of a "cascode transistor" (common base transistor) 70a, 70b. The drain terminals of the cascode transistors 70a, 70b are in turn connected to a transformer 5. The transistors are preferably in the form of field-effect transistors (FETs) and may for example be laterally diffused metal oxide

semiconductor, LDMOS, transistors, thin-film transistors, n-channel metal-oxide- semiconductor, NMOS , field-effect transistors, p-channel metal-oxide-semiconductor, PMOS field-effect transistors, and so forth, as known in the art.

In other words, the differential power amplifier comprises four field-effect transistors 70a,

70b, 70c, 70d, where the "bottom" two transistors 70c, 70d receive the differential input voltages "inp" and "inn". Bottom, top, left, right, is here in reference to the illustrated schematic arrangement in order to increase readability and not to be construed as limiting to the invention. Further, the gate terminal 9a of a first input field-effect transistor 70c is connected to a positive input "inp" to receive a positive component of the differential input voltage. The gate terminal 9b of a second field-effect transistor 70d is connected to a negative input "inn" to receive a negative component of the differential input voltage. Further, Fig. 7 also shows the gate bias inputs 6a, 6b, 7a, 7b that can be controlled by the control circuit by means of corresponding DC voltage supplies (ref. 6 and 7 in Figs. 3 - 5).

In high-frequency, high-power applications, the inductance of the output coils connected to the drain terminals of the cascode transistors (top transistors) 70a, 70b, is preferably selected so to resonate with the drain capacitances of the cascode transistors 70a, 70b. In these high- frequencies applications, a relatively small inductance is required, which translates into small diameter on-chip inductances, which is not compatible with large wire widths.

Fig. 8 shows another schematic power amplifier 2 applicable to be used in a power amplifier circuit in accordance with another exemplary embodiment of the present invention. The power amplifier 2 is a single-ended power amplifier and comprises a single field-effect transistor 70.

Fig. 9 shows yet another schematic power amplifier applicable to be used in a power amplifier circuit in accordance with another exemplary embodiment of the present invention. The power amplifier 2 is a differential power amplifier comprising two field-effect transistors 70a, 70b. The gate terminal of the field-effect transistor 70a is connected to a positive input "inp" to receive a positive component of the differential input voltage. Similarly, in Fig. 9, the gate terminal of the field-effect transistor 70b is connected to a negative input "inn" to receive a negative component of the differential input voltage. The source nodes of the field-effect transistors 70a, 70b are grounded and the drain nodes of the field-effect transistors are connected via a transformer 5 to a load, here in the form of an antenna 8. However, as already exemplified, other configurations are possible and within the scope of the present disclosure.

The control circuit 10 as discussed in the foregoing may comprise any number of hardware components for conducting data or signal processing for executing computer code stored in a memory. The control circuit 10 can comprise any number of modules for performing different operations. The control circuit 10 can for example include at least one computer readable storage medium or memory (not shown), and the memory can be one or more devices for storing data and/or computer code for completing or facilitating the methods described in the present description. The memory can include volatile memory or non-volatile memory. The control circuit may comprise a processor (not shown), such as for example a microprocessor, digital signal processor, graphical processing unit (GPU), embedded processor, field

programmable gate array (FPGA), or an Application specific integrated circuit (ASIC).

Fig. 10 shows three different plots (a), (b), (c) illustrating the power consumption, bias current, and voltage levels of the power amplifier in the power amplifier circuit illustrated in Fig. 3 and Figs. 6a, 6b during operation in the first mode 31 and second mode 32. The bottom plot, plot (c), illustrates the voltage level 3a at the first voltage rail (e.g. ref. 3 in Fig. 3) and the voltage level at the second voltage rail (e.g. ref. 4 in Fig. 3) during the first mode 31 and second mode 32. During the first mode 31, here being approximately 200 ps, only the first voltage rail is biased as indicated by the dashed line 3a that represents the electric potential of the first voltage rail. The second voltage rail is connected to ground during the first mode as indicated by line 3b. In the second mode 32, here being approximately 200 ps, the electric potential of the second voltage rail is slightly higher than that of the first voltage rail as indicated in the figure by AV.

The middle plot of Fig. 10, i.e. plot (b) shows the bias current through the amplifier, where the current through the amplifier is li during the first mode 31 and -li during the second mode 32. Since the magnitude of the bias voltage (may also be referred to as the supply voltage) is significantly higher during the first mode 31, the current magnitude is instead controlled by applying suitable gate bias levels as discussed in the foregoing. However, an effect of having a significantly lower magnitude of the bias voltage during the second mode, the power consumption 42 during the second mode 32 is significantly lower as compared to the power consumption 41 during the first mode.

Further, Fig. 11 shows a flow-chart representation of a method 100 for controlling a power amplifier in accordance with an exemplary embodiment of the present invention. The method 100 comprises determining 101 which mode operation the power amplifier is to be operated in, here two modes of operation. If it is the first mode of operation, a first bias current is applied 102 through the power amplifier. If it is the second mode of operation, a second bias current is applied 103 through the power amplifier, where the second bias current flows in the opposite direction as compared to the first bias current. The step of applying 102 the first bias current through the power amplifier may comprise applying a first DC voltage across the power amplifier (i.e. applying a first DC voltage between the first and second voltage rails connected to the power amplifier). Analogously, the step of applying 103 the second bias current may comprise applying a second DC voltage across the power amplifier (i.e. applying a second DC voltage between the first and second voltage rails connected to the power amplifier). However, the second DC voltage should have an opposite polarity as compared to the first DC voltage so to reverse the bias current in the second mode in reference to the first mode.

Moreover, the steps of applying 102, 103 the first and second bias currents may further comprise applying and controlling one or more gate bias voltages to the power amplifier. The gate bias voltage(s) are controlled such that a time integral of the second bias current during the second mode is within a range of 60 % to 140% of a time integral of the first bias current during the first mode.

The present disclosure has been presented above with reference to specific embodiments. However, other embodiments than the above described are possible and within the scope of the disclosure. Different method steps than those described above, performing the method by hardware or software, may be provided within the scope of the disclosure. Thus, according to an exemplary embodiment of the present invention, there is provided a non-transitory computer-readable storage medium storing one or more programs configured to be executed by one or more processors of a power amplifier control circuit, the one or more programs comprising instructions for performing the method according to any one of the above- discussed embodiments. The different features and steps of the embodiments may be combined in other combinations than those described.