Title:
POWER AMPLIFYING SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/189037
Kind Code:
A1
Abstract:
A power amplifying semiconductor device (100) operates at a frequency of 3 GHz or more and includes: a substrate (101); a semiconductor layer (102) provided on the surface of the substrate (101) and including a plurality of unit HEMTs; a connection layer (L1) provided on the semiconductor layer (102) and including source electrodes (301), drain electrodes (302) and gate electrodes (303) of the unit HEMTs; a terminal layer (L2) provided on the connection layer (L1) and including source pads (701a), drain pads (702a) and gate pads (703a); a backside electrode (103) provided on the backside of the substrate (101) and set to a source potential; and substrate vias (901) penetrating through the substrate (101) and having a shield wiring layer (503) on the inner wall thereof, the power amplifying semiconductor device including a drain aggregated portion (702) and a gate aggregated portion (703), the drain aggregated portion (702) and/or the gate aggregated portion (703) being surrounded by the substrate vias (901) in plan view.
Inventors:
NISHIO AKIHIKO
KAWASHIMA KATSUHIKO
KANDA YUSUKE
YUI TAKASHI
KAWASHIMA KATSUHIKO
KANDA YUSUKE
YUI TAKASHI
Application Number:
PCT/JP2023/006448
Publication Date:
October 05, 2023
Filing Date:
February 22, 2023
Export Citation:
Assignee:
NUVOTON TECH CORPORATION JAPAN (JP)
International Classes:
H01L21/338; H01L29/812; H01L29/778
Domestic Patent References:
| WO2009101870A1 | 2009-08-20 | |||
| WO2017029822A1 | 2017-02-23 |
Foreign References:
| JP2008182158A | 2008-08-07 | |||
| JP2009239115A | 2009-10-15 | |||
| JP2011139018A | 2011-07-14 |
Attorney, Agent or Firm:
NII, Hiromori et al. (JP)
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