TRANSMITTER

FIELD OF THE INVENTION

The invention relates to a transmitter.

The transmitter may form part of, for example, a multistandard communication apparatus, which is capable of operating in accordance with various different communication standards, such as, for example, communication standards known under the acronyms GSM, WiFi, Bluetooth, GPS, and CDMA. Other aspects of the invention relate to a communication apparatus, a method of controlling a transmitter, and a computer program product for a transmitter that comprises programmable processor.

BACKGROUND OF THE INVENTION A transmitter typically comprises an output amplifier that provides a transmission signal at an appropriate power level. To that end, the output amplifier needs to draw a given amount power from a power source. The lesser the amount power the output amplifier draws from the power source, the more power efficient the output amplifier is. Power efficiency is an important item if, for example, the power source is in the form of a battery. Many communication apparatuses are battery-powered. Cellular phones are an example.

An output amplifier can operate in a relatively power efficient manner by applying the following measures. The output amplifier receives a pulse-like input signal, that is, an input signal that substantially comprises pulses. Respective pulses preferably have the same magnitude. The output amplifier operates in a saturation mode or in a close- to-saturation mode during a pulse. That is, an input pulse drives the output amplifier to a voltage limit and to a current limit, or close to these limits. A power supply voltage typically constitutes the voltage limit.

A so-called 1 decibel (dB) compression point characterizes a close-to-the- limit mode of operation. At relatively small signal levels, there is a linear relationship between input power and output power: an X dB increase of input power causes an X dB increase of output power, X being an arbitrary real number. This relationship corresponds

with a straight 45° line in a graph of output power versus input power. As the input power increases, the output power will no longer follow, as it were, an increase of input power. The IdB compression point is the point where the output power is IdB below the straight 45° line. An amplifier generally operates in a power efficient manner at this point. Achieving power efficiency in a multistandard communication apparatus requires particular attention. This is because different communication standards may require different transmission signal power levels. For example, one communication standard may require a transmission signal with a relatively high power level, whereas a transmission signal with a relatively low power level is sufficient for another communication standard. A standard output amplifier may be designed to operate power efficiently when providing the relatively high power level. For example, the standard power amplifier can be arranged so that this amplifier is relatively close to the IdB compression point when providing the relatively high power level. However, this amplifier will be less power efficient when providing the relatively low power level. This is because the amplifier will be relatively far from the IdB compression point when providing the relatively low power level.

In principal, it is possible to design an output amplifier so that the output amplifier can operate power efficiently for different transmission signal power levels. For example, the output amplifier may be composed of a plurality of amplifier circuits, which can individually be switched on and off. All amplifier circuits are switched on when the relatively high power level is required. One or more amplifier circuits are switched off when a lower power level is sufficient. The amplifier circuits that are active operate relatively close to the IdB compression point. However, such an output amplifier has a relatively complicated structure and is, therefore, relatively expensive. Another option is to adjust a supply voltage or a supply current, which an output amplifier receives. For example, a transmitter may comprise a so-called DC-to-DC converter that generates an increased supply voltage for an output amplifier. The DC-to- DC converter may be arranged so that the increased supply voltage is adjustable. In manner of speaking, a voltage limit is adjusted so that the output amplifier operates relatively close to the voltage limit for different power levels. However, such a solution is also relatively expensive. Moreover, adjusting the supply voltage or the supply current may be accompanied with a certain loss in efficiency. For example, a DC-to-DC converter may

have an efficiency that varies as a function of the increased supply voltage that the DC-to- DC converter provides.

US patent application published under number 2004/0219891 describes a polar modulation transmitter, which includes a saturated driver amplifier, a saturated power amplifier circuit, a power controller, and a power amplifier controller. The saturated driver amplifier comprises transistor pairs, which operate as fully-switched transistor stages. The saturated power amplifier circuit comprises staged amplifiers in a series chain. These staged amplifiers are configured for saturated mode operation, although operating bias points might be adjusted separately. The power controller generates scaled versions of an input envelope-modulation information signal based on a desired transmit power. The power amplifier controller may operate as a supply voltage modulator or as a supply current modulator, or some combination thereof. In any case, the power amplifier controller provides a modulated supply signal, which is a function of an amplitude modulation output of a baseband processor.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a transmitter that can provide different levels of output power in a power-efficient manner and that can be implemented at moderate cost. The independent claims define various aspects of the invention. The dependent claims define additional features for implementing the invention to advantage.

In accordance with the invention, a transmitter comprises a pulse shaper that replaces a portion of a pulse in a basic signal by a neutral value. Accordingly, the pulse shaper provides a pulse-shaped signal that comprises a thinned version of the pulse and, adjacent thereto, the neutral value. An output amplifier, which amplifies the pulse-shaped signal, is in a quiescent state when the pulse-shaped signal has the neutral value.

A transmission signal power level can be decreased by thinning a pulse by means of the pulse shaper. The output amplifier can operate in a saturation mode or in a close-to-saturation mode during a pulse. The pulse may have a relatively long duration or a relatively short duration depending on whether a relatively high power level or a relatively low power level is required, respectively. A transmitter in accordance with the invention does therefore not necessarily require a specific amplifier structure or an adjustable supply power supply circuit in order to achieve power efficient operation for various different power levels. Consequently, the output amplifier in a transmitter in accordance with the

invention can be implemented at moderate cost. What is more, the pulse shaper can be implemented with relatively few circuit elements that are inexpensive. For those reasons, the invention allows power efficiency for different transmission signal power levels at moderate cost. Another advantage of the invention relates to the following aspects. It may be desired that an output amplifier of a transmitter has a so-called class AB operation although the output amplifier receives a pulse-like input signal. For example, a class AB operation may be desired if a transmission signal has a relatively high frequency at which transistors in the output amplifier cannot alternately be switched on and off completely. A class AB operation allows the output power amplifier to achieve a sufficient switching speed. A class AB operation generally requires a particular biasing current for a given power level. This biasing current varies as a square function with the power level. For example, reducing the power level by a factor of 10, while maintaining a class AB operation, requires reducing the biasing current by a factor of 100. Reducing the biasing current so as to maintain class AB operation may prove to be difficult, or even practically impossible, in an application that requires significantly different power levels. The invention allows maintaining a class AB operation over a relatively wide range of different power levels while keeping the biasing current constant. Thinning a pulse decreases the power level but does not substantially affect the class AB operation. Accordingly, the invention allows a satisfactory performance over a relatively wide range of transmission signal power levels.

An implementation of the invention advantageously comprises one or more of following additional features, which are described in separate paragraphs that correspond with different dependent claims. Each additional feature contributes to power efficiency or cost efficiency, or both.

The pulse shaper preferably comprises a multiplexer circuit that causes the pulse-shaped signal to correspond with the basic signal or with the neutral value in dependence on a multiplexer control signal.

The pulse shaper preferably further comprises a delay circuit, which provides a delayed version of the basic signal, and an exclusive -or circuit for applying an exclusive -or function to the basic signal and the delayed version thereof. The multiplexer control signal results from the exclusive-or function.

The pulse shaper preferably further comprises a differential pair, which provides the pulse-shaped signal in the form of a differential current. The differential pair is coupled to a tail current control circuit. The tail current control circuit causes a tail current to flow through the differential pair, or prevents any tail current from flowing through the differential pair, in dependence on the multiplexer control signal.

The output amplifier is preferably in the form of a current amplifier with a pair of input transistors in a common base configuration. These input transistors receive the differential current that constitutes the pulse-shaped signal.

The pulse shaper can preferably adjust the portion of the pulse that is replaced by the neutral value in dependence on a pulse shape control signal.

The output amplifier comprises a pair of output transistors and a biasing circuit, which causes a biasing current to flow through the pair of output transistors. The biasing circuit can adjust the biasing current in dependence on a biasing control signal.

The transmitter preferably comprises a controller that generates the pulse shape control signal and the biasing control signal on the basis of a particular signal power, which the output amplifier should provide.

A detailed description with reference to drawings illustrates the invention summarized hereinbefore, as well as the additional features.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig.l is a block diagram that illustrates a communication apparatus. Fig.2 is a circuit diagram that illustrates an implementation of a phase modulator, which forms part of the communication apparatus.

Fig.3 is a functional diagram that illustrates a phase shaper, which forms part of the communication apparatus.

Fig.4 is a composite signal diagram that illustrates various signals in the pulse shaper.

Fig.5 is a circuit diagram that illustrates an implementation of the pulse shaper. Fig.6 is a circuit diagram that illustrates an implementation of a power amplifier, which forms part of the communication apparatus.

DETAILS OF THE INVENTION

Fig.l illustrates a communication apparatus CAP, which may be in the form of, for example, a cellular phone. The communication apparatus CAP comprises human interface devices HID, which may include a microphone and a numerical keyboard. The communication apparatus CAP further comprises various functional entities that constitute a transmitter, which is coupled between the human interface devices HID and an antenna ANT. These functional entities include a baseband processor BBP, a phase modulator PHM, a pulse shaper PSH, a power amplifier PWA, and an antenna coupler ACC. The communication apparatus CAP further comprises a controller CTRL, which is typically in the form of a suitably programmed processor.

The aforementioned functional entities may be implemented, for example, as a single integrated circuit, which may also include the controller CTRL. As another example of implementation, there may be various different integrated circuits, each of which comprises one or more functional entities. It should be noted that the communication apparatus CAP may comprise various other functional entities, some of which may constitute, for example, a receiver. Fig.l does not illustrate these functional entities for reasons of simplicity.

The communication apparatus CAP basically operates as follows. The human interface devices HID provide a human interface output signal HIO, which may comprise, for example, a voice signal. The baseband processor BBP generates a quadrature phase modulation signal IQP and an amplitude modulation signal AM on the basis of the human interface output signal HIO. The quadrature phase modulation signal IQP and the amplitude modulation signal AM represent the human interface output signal HIO.

The phase modulator PHM generates a phase-modulated radiofrequency signal RFP on the basis of the quadrature phase modulation signal IQP and frequency control data FC from the controller CTRL. The phase-modulated radiofrequency signal RFP has a carrier frequency that depends on the frequency control data FC. The phase- modulated radiofrequency signal RFP comprises positive pulses and negative pulses, which alternately occur. The pulse shaper PSH, which receives the phase-modulated radiofrequency signal RFP, introduces a neutral value between two consecutive pulses for a given interval of time. The given interval of time depends on shape control data SH from the controller

CTRL. Accordingly, the pulse shaper PSH provides a pulse-shaped phase-modulated radio frequency signal RFS.

The power amplifier PWA amplifies the pulse-shaped phase-modulated radiofrequency signal RFS and introduces an amplitude modulation so as to obtain a radiofrequency output signal RFO, which is phase modulated and amplitude modulated. The amplitude modulation signal AM, which the power amplifier PWA receives from the baseband processor BBP, defines the amplitude modulation of the radiofrequency output signal RFO.

The power amplifier PWA has a given class of operation, which depends on class control data CL from the controller CTRL. The given class of operation may be, for example, one of the following: A, AB, C or D depending on linearity, efficiency, and speed requirements. The antenna coupler ACC filters and transforms the radiofrequency output signal RFO that the power amplifier PWA provides so as to obtain a suitable antenna signal. The power amplifier PWA is in a quiescent state when the pulse-shaped phase-modulated radiofrequency signal RFS has the neutral value. The radiofrequency output signal RFO has a power level that depends on a percentage of time for which the power amplifier PWA is in the quiescent state. Accordingly, the controller CTRL can adjust the power level by means of the shape control data SH. The controller determines the shape control data SH on the basis of a desired power level, which the radio frequency output signal RFO should have. The controller may further determine respective gain settings and the class control data CL for the power amplifier PWA.

Fig.2 illustrates an implementation of the phase modulator PHM, which will be referred to hereinafter as phase modulator circuit. The phase modulator circuit comprises various transistors Q11-Q16 and Q21-Q26, various tail current sources TI l,

T12 and T21, T22, two digital-to-analog converters DACl and DAC2, and a fractional synthesizer FNS, which is coupled to a crystal element XTL. Transistors Q11-Q16, tail current sources TI l, T 12, and digital-to-analog converter DACl constitute an in-phase carrier modulation branch. Transistors Q21-Q26, tail current sources T21, T22, and analog to digital converter DAC2 constitute a quadrature modulation branch. The phase modulator circuit receives a main supply voltage VCC from a power supply source within the communication apparatus CAP illustrated in Fig.l.

The phase modulator circuit basically operates as follows. The fractional synthesizer FNS generates an in-phase carrier signal IC and a quadrature carrier signal QC on the basis of the frequency control data FC from the controller CTRL illustrated in Fig.l and a reference frequency Fref, which the crystal element XTL defines. The in-phase carrier signal IC and the quadrature carrier signal QC have an identical frequency that is equal to the reference frequency Fref multiplied by a rational number. The frequency control data FC defines the rational number.

Transistors QI l, Q12, Q15, Q16 and tail current source T 12 constitute a signal scaling circuit that provides a scaled version of the in-phase carrier signal IC. Transistors Q 13, Q 14 constitute a differential pair, which receives this scaled version of the in-phase carrier signal IC as a differential input signal voltage. Similarly, transistors Q21, Q22, Q25, Q26 and tail current source T22 constitute a signal scaling circuit that provides a scaled version of the quadrature carrier signal QC. Transistors Q23, Q24 constitute a differential pair that receives this scaled version of the quadrature carrier signal QC as a differential input signal voltage.

The phase modulator circuit receives the quadrature phase modulation signal IQP from the baseband processor BBP illustrated in Fig.l. The quadrature phase modulation signal IQP comprises an in-phase component IP and a quadrature component QP. Each of these components is in the form of a stream of digital values. The in-phase component IP of the quadrature phase modulation signal IQP corresponds with a desired phase modulation to which a sine function has been applied. The quadrature component QP corresponds with the desired phase modulation to which a cosine function has been applied. This can mathematically be expressed as follows: IP=A ₀ -sin[φ(t)] QP=A ₀ -cos[φ(t)] wherein φ(t) represents the desired phase modulation and A ₀ an envelope-magnitude constant.

Digital-to-analog converter DACl provides an in-phase modulation current IMI, which is an analog representation of the in-phase component IP. The in-phase modulation current IMI is added to a fixed tail current ITl, which tail current source TI l provides. The differential pair, which transistors Q 13, Q 14 form, receives a modulated tail current, which is a sum of the in-phase modulation current IMI and the fixed tail current ITl from tail current source TI l. As explained hereinbefore, this differential pair Q 13,

Q 14 further receives a scaled version of the in-phase carrier signal IC as a differential input signal voltage. Accordingly, transistors Q 13, Q 14 provide a differential current signal I _RF i, which is an amplitude modulated version of the in-phase carrier signal IC that the fractional synthesizer FNS provides. This differential current signal I _RFI has an amplitude modulation component that corresponds with the in-phase component IP.

In a similar fashion, transistors Q23, Q24 provide a differential current signal I _RFQ , which is an amplitude modulated version of the quadrature carrier signal QC that the fractional synthesizer FNS provides. This differential current signal I _RFQ has an amplitude modulation component that corresponds with the quadrature component QP, which the phase modulator PHM receives from the baseband processor BBP illustrated in Fig.l. More specifically, digital-to-analog converter DAC2 provides a quadrature modulation current IMQ, which is an analog representation of the quadrature component QP of the quadrature phase modulation signal IQP. The quadrature modulation current IMQ is added to a fixed tail current IT2, which tail current source T21 provides. The differential pair, which transistors Q23, Q24 form, receives a modulated tail current, which is the sum of the quadrature modulation current IMQ and the fixed tail current IT2 from tail current source T21. This differential pair Q23, Q24 further receives a scaled version of the quadrature carrier signal QC as a differential input signal voltage.

The phase modulator circuit provides a differential output signal current I _RFP , which corresponds with the phase-modulated radiofrequency signal RFP in Fig.l. This differential output signal current I _RFP is a sum of the differential signal currents I _RFI and I _RFQ , which the in-phase modulation branch and the quadrature modulation branch, respectively, provide. The differential output signal current I _RFP does not comprise any substantial amplitude modulation component. This is due to the fact that the in-phase component IP of the quadrature phase modulation signal IQP is a sine function of the desired phase modulation and that the quadrature component QP is a cosine function of the desired phase modulation. The differential output signal current I _RFP has a phase modulation component that substantially corresponds with the desired phase modulation component, which the quadrature phase modulation signal IQP defines.

Fig.3 illustrates the pulse shaper PSH in the form of a functional diagram. The pulse shaper PSH comprises the following functions: a signal delay function DEL, an exclusive-or function XOR, and a multiplexing function MUX. An implementation of the

pulse shaper PSH may comprise a circuit that carries out more than one function. An example will be given hereinafter.

The pulse shaper PSH basically operates as follows. The delay function is applied to the phase-modulated radio frequency signal RFP. Accordingly, a delayed version RFPD of the phase-modulated radio frequency signal is obtained, which has a given delay δ with respect to the phase-modulated radio frequency signal RFP. The shape control data SH from the controller CTRL illustrated in Fig.l determines the given delay δ between the aforementioned signals. The exclusive-or function XOR is applied to the phase-modulated radiofrequency signal RFP and the delayed version RFPD thereof. In response, the exclusive-or function XOR provides a neutral-value forcing signal NF.

The multiplexing function MUX is applied to the phase-modulated radiofrequency signal RFP and a neutral value "0". The neutral-value forcing signal NF, which the exclusive-or function XOR provides, controls the multiplexing function MUX. The neutral value 0 may correspond with a center value of the phase-modulated radiofrequency signal RFP. The multiplexing function MUX provides the pulse-shaped phase-modulated radiofrequency signal RFS, which the power amplifier PWA illustrated in Fig.1 receives. The power amplifier PWA is in a quiescent state when the pulse-shaped phase-modulated radiofrequency signal RFS has the neutral value 0. This will be explained in greater detail hereinafter.

Fig.4 illustrates various signals that are present in the pulse shaper PSH. Fig.4 is a composite graph having a common horizontal axis, which represents time T, and various signal diagrams disposed as horizontal bars, each of which represents a particular signal: the phase-modulated radiofrequency signal RFP, the delayed version RFPD of the phase-modulated radiofrequency signal, the neutral-value forcing signal NF, and the pulse- shaped phase-modulated radiofrequency signal RFS. Fig.4 indicates the given delay δ between the phase-modulated radiofrequency signal RFP and the delayed version RFPD thereof.

Fig.4 illustrates that the phase-modulated radiofrequency signal RFP is a square wave like signal, which switches between a positive normalized value +1 and a negative normalized value -1. The same applies to the delayed version RFPD of the phase- modulated radiofrequency signal. The positive normalized value +1 and the negative normalized value -1 may be associated with a current flowing in one direction and in an

opposite direction, respectively. For example, Fig.2 illustrates that the differential output current signal I _RF p of the phase modulator circuit flows in a particular direction. This may correspond with the positive normalized value +1. The negative normalized value -1 applies when the differential output current signal I _RFP flows in an opposite direction. The neutral-value forcing signal NF has a low value L when the phase- modulated radio frequency signal RFP and the delayed version RFPD thereof have identical values. Conversely, the neutral-value forcing signal NF has a high value H when the phase- modulated radio frequency signal RFP and the delayed version RFPD thereof have opposite values. The neutral-value forcing signal NF controls the multiplexing function MUX so as to obtain the pulse-shaped phase-modulated radio frequency signal RFS. The multiplexing function MUX causes the latter signal to have a value that corresponds with that of the phase-modulated radiofrequency signal RFP when the neutral-value forcing signal NF has the low value L. The multiplexing function MUX causes the pulse-shaped phase- modulated radiofrequency signal RFS to have the neutral value 0 when the neutral-value forcing signal NF has the high value H.

Fig.4 illustrates that the pulse shaper PSH effectively narrows pulses in the phase-modulated radiofrequency signal RFP by introduction of the neutral value 0. The pulses are narrowed to an extent that depends on the given delay δ, which the signal delay function DEL provides. More precisely, the pulse shaper PSH effectively replaces a front portion of a pulse in the phase-modulated radiofrequency signal RFP with the neutral value 0. The front portion, which is replaced by the neutral value 0, has a length that corresponds with the given delay δ. The controller CTRL illustrated in Fig.l can adjust this delay δ by means of the shape control data SH, which the controller CTRL applies to the pulse shaper PSH. The pulse-shaped phase-modulated radiofrequency signal RFS has a phase modulation component that substantially corresponds with that of the phase-modulated radiofrequency signal RFP, which the phase modulator PHM illustrated in Fig.2 provides. That is, the pulse shaper PSH does not substantially affect the phase modulation component. This can be understood as follows. Each respective pulse in the phase- modulated radiofrequency signal RFP can be considered to have a center of gravity, which corresponds with a particular point on the horizontal axis. Similarly, each respective narrowed pulse in the pulse-shaped phase-modulated radiofrequency signal RFS can be considered to have a center of gravity. The center of gravity of a narrowed pulse is shifted

by a fixed amount with respect to the center of gravity of a corresponding pulse in the phase-modulated radio frequency signal RFP. This shifting by a fixed amount preserves the phase modulation component.

Fig.5 illustrates an implementation of the pulse shaper PSH, which will be referred to as pulse shaper circuit hereinafter. The pulse shaper circuit comprises various transistors Q31-Q35 and Q41-Q46, various resistors R31, R32, various tail current sources T3, T41, T42, and a delaying amplifier circuit DAMP. In Fig.5, some resistors have no reference sign. These resistors have a biasing function. Transistors Q31, Q32 have respective base terminals, which receive a controlled bias voltage VBC via these resistors. The controlled bias voltage VBC originates from the power amplifier PWA. This will be described in greater detail hereinafter. The pulse shaper circuit receives the main supply voltage VCC.

The pulse shaper circuit operates as follows. The pulse shaper circuit receives the differential output signal current I _RFP of the phase modulator circuit illustrated in Fig.2. The pulse shaper circuit further receives a common mode current that is a sum of tail currents ITl and IT2 in the phase modulator circuit.

The differential output signal current I _RF p of the phase modulator circuit flows through transistors Q31, Q32, which produces a differential input signal voltage V _RFP . This differential input signal voltage V _RFP varies with the differential output signal current I _RFP in accordance with an inverse hyperbolic tangent function. Transistors Q31, Q32 have respective emitter base junctions that define the inverse hyperbolic tangent function. The aforementioned common mode current, which is the sum of tail currents ITl and IT2 in Fig.2, also defines the inverse hyperbolic tangent function. Transistors Q33, Q34 form a differential pair that is coupled to tail current source T3, which provides a tail current IT3. This differential pair Q33, Q34 receives the differential input signal voltage V _RFP and provides, in response, a differential output signal current I _RFS . The differential output signal current I _RFS depends on a neutral-value forcing voltage V _NF , which transistor Q35 receives. It will be shown that the differential output signal current I _RF s corresponds with the pulse-shaped phase-modulated radio frequency signal RFS illustrated in Fig.1.

Let it be assumed that the neutral-value forcing voltage V _NF is significantly greater than the controlled bias voltage VBC, which transistors Q31, Q32 receive. In that

case, the tail current IT3 will substantially flow through transistor Q35. Transistors Q33, Q34 will not receive any biasing current. The differential pair, which these transistors Q33, Q34 constitute, is inactive. As a result, the differential output signal current I _RFS will be zero. Transistors Q33, Q34 will not provide any common mode output current either. This case corresponds with the pulse-shaped phase-modulated radiofrequency signal RFS having the neutral value 0, which has been described hereinbefore with reference to Fig.4.

Let it now be assumed the neutral-value forcing voltage V _NF is significantly smaller than the controlled bias voltage VBC. In that case, the tail current IT3 entirely flows through transistors Q33, Q34. The differential pair, which these transistors Q33, Q34 constitute, is active. As a result, the differential output signal current I _RF s varies with the differential input signal voltage V _RFP in accordance with a hyperbolic tangent function. Transistors Q33, Q34 have respective emitter base junctions that define the hyperbolic tangent function. The tail current IT3 also defines the hyperbolic tangent function.

The following applies when the neutral-value forcing voltage V _NF is significantly smaller than the controlled bias voltage VBC. The differential output signal current I _RFS of the pulse shaper circuit is a scaled version of the differential output signal current I _RFP of the phase modulator PHM. That is, the differential output signal current I _RFS corresponds with the differential output signal current I _RF p multiplied by a current amplification factor. The current amplification factor depends on the respective emitter base junction areas of transistors Q31, Q32 and Q33, Q34, the tail current IT3, and tail currents ITl, IT2 in Fig.2, which constitute the common mode current that the pulse shaper circuit receives.

Transistor Q35 participates in the multiplexing function MUX, which is illustrated in Fig.3. The neutral-value forcing voltage V _NF corresponds with the neutral- value forcing signal NF in Fig.3. In the pulse shaper circuit, which Fig.5 illustrates, the multiplexing function MUX is comprised in a current amplifier circuit of which transistors Q31-Q34 and tail current source T3 form part. This current amplifier circuit is of the translinear type.

Transistors Q41-Q46, resistors R31, R32, and tail current sources T41, T42 constitute an exclusive -or circuit, which provides the exclusive-or function XOR illustrated in Fig.3. Tail current sources T41, T42 provide tail currents IT41, IT42, respectively, which have substantially similar magnitude. Transistors Q43, Q44 receive a fixed bias voltage VB.

The exclusive-or circuit receives two differential signal voltages from the delaying amplifier circuit DAMP: an amplified differential input signal voltage V _RFPA and a delayed and amplified differential input signal voltage V _RFPD - The delaying amplifier circuit DAMP provides these two differential signal voltages on the basis of the shape control data SH from the controller CTRL illustrated in Fig.l and the differential signal voltage V _RFP , which transistors Q31, Q32 produce in response to the differential output signal current I _RFP of the phase modulator circuit. The amplified differential input signal voltage V _RFPA and the delayed and amplified differential input signal voltage V _RFPD are each superposed on a common mode voltage that substantially corresponds with the fixed bias voltage VB. The amplified differential input signal voltage V _RFPA can be associated with the phase-modulated radio frequency signal RFP illustrated in Fig.4. The delayed and amplified differential input signal voltage V _RFPD can be associated with the delayed version RFPD of the phase-modulated radiofrequency signal illustrated in Fig.4.

Let it be assumed that the amplified differential input signal voltage V _RFPA and the delayed and amplified differential input signal voltage V _RFPD both have the same value, which may be either the positive normalized value +1 or the negative normalized value -1 illustrated in Fig.4. In that case, tail current IT41 flows through transistor Q41 or transistor Q42 and tail current IT42 flows through transistor Q45 or transistor Q46, depending on whether the two differential signal voltages V _RFPA , V _RFPD that the exclusive- or circuit receives have the positive normalized value +1 or the negative normalized value -1, respectively. In either case, a sum of tail currents IT41, IT42 will flow through resistor R31. As a result, the neutral-value forcing voltage V _NF will be significantly lower than the controlled bias voltage VBC. As explained hereinbefore, in that case, the differential output signal current I _RFS corresponds with the differential output signal current I _RFP multiplied by the current amplification factor.

Let it now be assumed that the amplified differential input signal voltage V _RFPA has the positive normalized value +1 and that the delayed and amplified differential input signal voltage V _RFPD has the negative normalized value -1. In that case, a portion of tail current IT41 will flow through transistor Q41 and another portion of tail current IT41 will flow through transistor Q42. Tail current IT42 will substantially flow through transistor Q44; substantially no current flows through transistors Q45, Q46. Only tail current IT41 will flow through resistor R31; tail current IT42 will flow through resistor R32. As a result, the neutral-value forcing voltage V _NF will be significantly higher than the

controlled bias voltage VBC. As explained hereinbefore, in that case the tail current IT3 will substantially flow through transistor Q35, which causes the differential output signal current I _RFS to have the neutral value 0.

The same applies when the amplified differential input signal voltage V _RFPA has the negative normalized value -1 and the delayed and amplified differential input signal voltage V _RFPD has the positive normalized value +1. In that case, tail current IT41 will substantially flow through transistor Q43; substantially no current flows through transistors Q41, Q42. A portion of tail current IT42 will flow through transistor Q45 and another portion of tail current IT42 will flow through transistor Q46. Only tail current IT42 will flow through resistor R31 ; tail current IT41 will flow through resistor R32. As a result, the neutral-value forcing voltage V _NF will be significantly higher than the controlled bias voltage VBC.

Fig.6 illustrates an implementation of the power amplifier PWA, which will be referred to hereinafter as power amplifier circuit. The power amplifier circuit comprises a various transistors Q51-Q58 and Q61-Q64, a controllable current source CS5, a digital- to-analog converter DAC5, a DC-to-DC converter DDC, two load inductances L61, L62, and a stray inductance LS6. A bonding wire may form the stray inductance LS6 in an integrated circuit implementation. The power amplifier circuit further comprises various resistors for biasing purposes. In Fig.6, these resistors have no reference signs. The power amplifier circuit receives the main supply voltage VCC.

The power amplifier circuit operates as follows. The power amplifier circuit receives the differential output signal current I _RFS of the pulse shaper circuit illustrated in Fig.5. The power amplifier circuit further receives a common mode input current that corresponds with tail current IT3 in the pulse shaper circuit illustrated in Fig.5. The differential output signal current I _RF s of the pulse shaper circuit flows through transistors Q51, Q52, which produces a differential input signal voltage V _RFS - The differential input signal voltage V _RFS varies with the differential output signal current I _RFS in accordance with an inverse hyperbolic tangent function. Transistors Q51, Q52 have respective emitter base junctions that define the inverse hyperbolic tangent function. The aforementioned common mode input current, which corresponds with tail current IT3 in Fig.5, also defines the inverse hyperbolic tangent function.

Transistors Q61, Q62 form a differential pair, which will be referred to as differential output pair Q61, Q62 hereinafter. The differential output pair Q61, Q62 receives the differential input signal voltage V _RFS via transistors Q53, Q54. Transistors

Q53, Q54 are arranged in an emitter follower configuration and constitute a differential signal voltage amplifier with substantially unity gain.

The differential output pair Q61, Q62 converts the differential input signal voltage V _RFS into a differential output signal current I _RFO - Transistors Q63, Q64 transfer the differential output signal current I _RFO to the two load inductances L61, L62. Transistors Q63, Q64 are arranged in a common base configuration, which is also frequently referred to as cascode configuration. Transistors Q63, Q64 constitute a differential signal current amplifier with substantially unity gain.

The differential output signal current I _RFO , which flows through the two load inductances L61, L62, produces a differential output signal voltage V _FRO - The differential output signal voltage V _FRO corresponds with the radiofrequency output signal RFO illustrated in Fig.l. A circuit corresponding with the antenna coupler ACC illustrated in Fig.1 may filter and transform the differential output signal voltage V _FRO SO as to obtain a single-ended antenna signal with desired spectral characteristics.

The DC-to-DC converter DDC generates an increased supply voltage VCX from the main supply voltage VCC and applies the increased supply voltage VCX to the load inductances L61, L62. The differential output signal voltage V _RFO can vary in a relatively wide voltage range, which is comprised between signal ground and the increased supply voltage VCX, which the DC-to-DC converter DDC generates.

The differential output signal current I _RFO varies with the differential input signal voltage V _RFS in accordance with a specific function, which will be referred to as output transconductance function hereinafter. The output transconductance function depends on a common mode current ICM, which flows through the differential output pair

Q61. Q62.

The power amplifier circuit comprises a common mode control loop that defines the common mode current ICM that flows through the differential output pair Q61, Q62. The common mode control loop comprises transistors Q55, Q56, the controlled current source, and digital-to-analog converter DAC5. Transistors Q55, Q56 are effectively coupled in parallel with transistors Q61, Q62, respectively. Consequently, transistors Q55, Q56 each provide a scaled copy of a main current that flows through transistors Q61, Q62,

respectively. Since transistors Q55, Q56 have collectors that are coupled to each other, the respective current copies are summed, which produces a common collector current ICR. The common collector current ICR is thus a scaled copy of the common mode current ICM that flows through the differential output pair Q61, Q62. The common collector current ICR flows to a current comparison node XN.

Two other currents flow to the current comparison node XN: a bias reference current IB, which the controllable current source CS5 provides, and an amplitude modulation current IAM, which the digital-to-analog converter DAC5 provides. The bias reference current IB has a magnitude that depends on the class control data CL, which the power amplifier circuit receives from the controller CTRL as illustrated in Fig.l. The amplitude modulation current IAM is an analog representation of the amplitude modulation signal AM, which the power amplifier circuit receives from the baseband processor BBP. The amplitude modulation signal AM is in the form of a stream of digital values, which the digital-to- analog converter converts into the amplitude modulation current IAM. A difference current ID flows from the current comparison node XN to respective base terminals of transistors Q51, Q52. The difference current ID is a sum of the bias reference current IB and the amplitude modulation current IAM minus the common collector current ICR from transistors Q55, Q56. An increase of the difference current ID will cause an increase of the common collector current ICR, which counteracts the aforementioned increase of the difference current ID. Likewise, a decrease of the difference current ID will cause a decrease of the common collector current ICR, which counteracts the aforementioned decrease of the difference current ID.

The common mode control loop strives to achieve a steady-state condition in which the difference current ID from the current comparison node XN is substantially equal to zero. That is, in the steady-state condition the common collector current ICR is equal to the sum of the bias reference current IB and the amplitude modulation current IAM. It has been explained hereinbefore that the common collector current ICR, which transistors Q55, Q56 provide is a scaled copy of the common mode current ICM that flows through the differential output pair. Consequently, the common mode control loop strives to make the common mode current ICM equal to the sum of the bias reference current IB and the amplitude modulation current IAM multiplied by a scaling factor. Transistors Q55, Q56 and Q61, Q62 define this scaling factor, which is a function of various transistor parameters such as, for example, transistor size.

The controlled bias voltage VBC occurs at the current comparison node XN. Transistors Q51, Q52 and transistors Q53, Q54 level shift the controlled bias voltage VBC so as to produce a level-shifted version of the controlled bias voltage VBC at respective base terminals of transistors Q61, Q62. In the steady-state condition, this level-shifted version of the controlled bias voltage VBC is so that the common mode current ICM, which flows through the output differential pair Q61, Q62, causes the common collector current ICR to be equal to the sum of the bias reference current IB and the amplitude modulation current IAM. In the steady-state condition, the controlled bias voltage VBC is approximately equal to the average of two voltage sums: a sum of respective emitter base junction voltages of transistors Q51 and Q53, and a sum of respective emitter base junction voltages of transistors Q52 and Q54. As mentioned hereinbefore, the pulse shaper circuit illustrated in Fig.5 receives the controlled bias voltage VBC.

The class control data CL, which the controller CTRL illustrated in Fig.l provides, determines the class of operation of the power amplifier circuit by setting a magnitude of the bias reference current IB within the common mode control loop. The power amplifier circuit has a class A operation when the bias reference current IB is relatively large. A class AB operation can be obtained by lowering the magnitude of the bias reference current IB. A class B operation can be obtained by further lowering the magnitude of the bias reference current IB. Further lowering of the magnitude of the bias reference current IB allows achieving class C operation and subsequently class D operation.

A particular magnitude of the bias reference current IB can be associated with each class of operation. These respective particular magnitudes depend on a small signal current gain, which the power amplifier circuit provides. The small signal current gain corresponds with the magnitude ratio between the differential output signal current I _RFO of the power amplifier circuit and the differential output signal current I _RF s of the pulse shaper circuit, when the latter signal current is infinitely small. There are various parameters that determine the small signal current gain of the power amplifier circuit: tail current IT3 in the pulse shaper circuit, which forms the common mode input current that the power amplifier circuit receives, the respective emitter-base junctions of transistors Q51, Q52 and those of transistors Q61, Q62, and the bias reference current IB.

Let it be assumed that the bias reference current IB has a magnitude so that the common mode input current ICM that flows through the differential output pair Q61,

Q62 is greater than tail current IT3 multiplied by the small signal current gain. In that case, both transistors Q61, Q62 will continuously be conductive to a greater or lesser extent for any given magnitude of the differential output signal current I _RFS of the pulse shaper circuit. The power amplifier circuit has a class A operation. Let it now be assumed that the bias reference current IB has a magnitude so that the common mode input current ICM that flows through the differential output pair Q61, Q62 is significantly smaller than tail current IT3 multiplied by the small signal current gain. In that case, either transistor Q61 or transistor Q62 will be conductive depending on whether the differential output signal current I _RFS of the pulse shaper circuit has a positive sign or a negative sign. The power amplifier circuit has a class D operation.

The common mode current ICM of the differential output pair Q61, Q62 reproduces the amplitude modulation current IAM, which the digital-to-analog converter DAC5 effectively injects into the common mode control loop. That is, the common mode current ICM has a magnitude that varies with the amplitude modulation signal AM from the baseband processor BBP. As a result, the differential output signal current I _RFO comprises an amplitude modulation component that corresponds with the amplitude modulation signal AM. The differential output signal voltage V _RFO will comprises the same amplitude modulation component.

The power amplifier circuit allows a broadband amplitude modulation. This is because the common mode control loop, via which amplitude modulation is introduced, has a relatively large bandwidth. Several factors account for this. First of all, time constants within the common mode control loop are relatively small. Transistors Q61, Q62, define a dominant time constant within the common mode control loop because these transistors are relatively large and, therefore, have relatively large capacitances. Transistors Q51, Q52 which are typically relatively small compared with transistors Q61, Q62, define a somewhat less dominant time constant.

Advantageously, the stray inductance LS6 allows the common mode control loop to have a high degree of stability. The stray inductance LS6 introduces a positive phase shift, which has a stabilizing effect. The stray inductance LS6 does not substantially affect conversion of the differential input signal voltage into the differential output signal current. That is, the stray inductance LS6 has a common mode effect only, not a differential mode effect.

It should be noted that the DC-to-DC converter DDC does not actively participate in an amplitude modulation process. Such participation would require the DC- to-DC converter DDC to provide a signal modulated increased output voltage. The DC-to- DC converter DDC would need to have sufficient bandwidth so that the signal modulated increased output voltage represents the amplitude modulation component with sufficient precision. This is difficult to achieve, or may even be impossible, if the amplitude modulation component has a relatively large bandwidth. In the power amplifier circuit, which Fig.6 illustrates, the increased supply voltage VCX that the DC-to-DC converter DDC provides is fixed. Consequently, the DC-to-DC converter DDC need not be designed for a specific dynamic behavior.

Transistors Q57, Q58 contribute to a relatively fast and symmetrical transient response of the differential output pair Q61, Q62. This is because transistors Q57, Q58 assist in charging and discharging relatively large junction capacitances, which are present in transistors Q61, Q62. Let it be assumed, for example, that there is a voltage decrease at a base terminal of transistor Q61 and, conversely that there is a voltage increase at a base terminal of transistor Q62. In that case, transistor Q57 provides a sink current that discharges junction capacitances within transistor Q61 so as to render this transistor less conductive. Conversely, transistor Q58 provides a source current that charges junction capacitances within transistor Q62 so as to render this transistor more conductive. In a manner of speaking, transistor Q58 pushes and transistor Q57 pulls, or vice versa, so that the differential output signal current I _RFO quickly responds to a variation in the differential input signal voltage V _RFS -

The differential output signal current I _RFS of the pulse shaper circuit illustrated in Fig.5, which the power amplifier circuit receives as an input signal, may temporarily be zero as explained hereinbefore. In addition, the common mode input current, which the power amplifier circuit receives, will temporarily be zero too. This corresponds with forcing the neutral value 0 upon the pulse-shaped phase-modulated radiofrequency signal RFS as illustrated in Fig.4. The power amplifier circuit is in a quiescent state when this occurs: the differential output signal voltage V _RFO is substantially equal to zero. That is, the power amplifier circuit does not provide any substantial radiofrequency power in the quiescent state.

On average, the power amplifier circuit is in the quiescent state for a percentage of time that depends on the delay δ within the pulse shaper PSH illustrated in

Fig.3. The longer the delay δ is, the greater the percentage of time during which the power amplifier circuit is in a quiescent state. Consequently, the power amplifier circuit provides an amount of radiofrequency power, which can be adjusted by varying the delay δ within the pulse shaper PSH. The delay δ does not substantially affect the class of operation of the power amplifier circuit.

The controller CTRL illustrated in Fig.l defines the delay δ in the pulse shaper PSH by means of the shape control data SH. To that end, the CTRL may comprise, for example, a delay locked loop for a precise control of the delay δ. The controller CTRL can thus maintain a desired class of operation, with a given degree of efficiency, throughout a range of different radiofrequency power levels.

A class D operation allows high efficiency. Transistors Q61 and Q62 are alternately switched on and off in this class of operation. This may prove to be difficult or even impossible at relatively high frequency due to relatively large time constants within these transistors. Transistors Q61 and Q62 are too slow, as it were, to follow relatively high-speed signal transitions. In that case, a class AB operation may be more appropriate. The controller CTRL illustrated in Fig.1 may adjust the amount of radiofrequency power, while maintaining class AB operation, by varying the delay δ in the pulse shaper PSH by means of the shape control data SH..

It should be noted that adjusting tail currents, either individually or in combination, allows a precise gain control. For example, the pulse shaper circuit illustrated in Fig.3 provides a power gain that depends on the ratio of tail current IT3 and the sum of tail currents ITl and IT2 from the phase modulator circuit illustrated in Fig.2. The power gain varies with substantially proportionally with tail current IT3 and substantially inversely proportionally with the sum of tail currents ITl and IT2. The power amplifier circuit illustrated in Fig.6 provides a power gain that depends on tail current IT3 from the pulse shaper circuit illustrated in Fig.5.

The controller CTRL illustrated in Fig.l may be programmed to provide a suitable gain control by varying the aforementioned tail currents. In this respect, it should be mentioned that the bias reference current IB is preferably adjusted when the power gain of the pulse shaper circuit or the amplifier circuit is adjusted. Such an adjustment allows the power amplifier circuit to maintain a similar class of operation. For example, a class AB operation can be maintained if the bias reference current IB varies with the power gain in a substantially exponential fashion.

It should be noted that the power gain that the pulse shaper circuit provides is substantially insensitive to temperature variations and production spread. This is because the power gain substantially depends on a current ratio, as mentioned hereinbefore, and that the respective tail currents vary with temperature in a substantially similar fashion and are similarly affected by any production spread. The power gain that the power amplifier circuit provides is also substantially insensitive to temperature variations and production spread for similar reasons. The power gain of the power amplifier circuit substantially depends on a transistor dimension ratio. Transistors Q51, Q52 and transistors Q61, Q62 define this transistor dimension ratio and, therefore, the power gain of the power amplifier circuit.

The detailed description hereinbefore with reference to the drawings is merely an illustration of the invention and the additional features, which are defined in the appended claims. The invention can be implemented in numerous different manners. In order to illustrate this, some alternatives are briefly indicated.

The invention may be applied to advantage in any type of product or method that involves transmission of a signal. The communication apparatus CAP illustrated in Fig.l is merely an example. The radiofrequency output signal RFO that this communication apparatus CAP provides is phase modulated and amplitude modulated. The invention may equally be applied in, for example, a communication apparatus that provides a radiofrequency output signal of constant envelope, which is exclusively phase modulated. Such a communication apparatus need not comprise a power amplifier that introduces amplitude modulation. For example, referring to Fig.6, digital-to-analog converter DAC5 may be omitted.

There are numerous different manners to implement a pulse shaper. The pulse shaper illustrated in Fig.4 is merely an example, which involves an exclusive -or function and a multiplexing function. A pulse shaper may involve other logic functions, such as, for example, an "and" function. A pulse-like input signal and a delayed version thereof may be applied to an "and" gate. Inverted versions of these signals may be applied to another "and" gate. A binary zero at the respective outputs of these "and" gates corresponds with the neutral value. A binary one at the output of the one and the other gate

corresponds with a positive pulse and a negative pulse, respectively. There is no need for any multiplexing function in this alternative implementation.

What is more, a pulse shaper need not necessarily involve a logic function. For example, a pulse-like input signal may be applied to an integrator circuit, which has an integration coefficient. The integrator circuit transforms a rectangular pulse into a triangular pulse, which has a magnitude that depends on the integration coefficient. The triangular pulse may be applied to a multilevel comparator circuit, which has a positive and a negative threshold. The multilevel comparator circuit provides the neutral level for a portion of the triangular pulse that is comprised between the positive and the negative threshold. The multilevel comparator circuit provides a positive output pulse or a negative output pulse for a portion of the triangular pulse that is above the positive threshold or below the negative threshold, respectively, whichever applies. These respective output pulses have a width that can be adjusted by varying the integration coefficient. This mechanism equally applies if the pulse-like input signal comprises pulses other than rectangular pulses, which have been mentioned here for reasons of ease of explanation.

There are numerous ways of implementing functions by means of items of hardware or software, or both. In this respect, the drawings are very diagrammatic, each representing only one possible embodiment of the invention. Thus, although a drawing shows different functions as different blocks, this by no means excludes that a single item of hardware or software carries out several functions. Nor does it exclude that an assembly of items of hardware or software or both carry out a function.

The remarks made herein before demonstrate that the detailed description with reference to the drawings, illustrate rather than limit the invention. There are numerous alternatives, which fall within the scope of the appended claims. Any reference sign in a claim should not be construed as limiting the claim. The word "comprising" does not exclude the presence of other elements or steps than those listed in a claim. The word "a" or "an" preceding an element or step does not exclude the presence of a plurality of such elements or steps.