Technical Field

Embodiments described herein generally relate to the field of power limit setting and, more particularly, to power limit setting of processing units of a data processing platform. Some embodiments relate to power limit setting of processing units of an integrated circuit device, such as a system-on-chip (SOC).

Background

System-on-chip (SOC) designs for computer processing platforms may incorporate a number of discrete processing units, such as a central processing unit (CPU), a graphics processing unit (GPU) and an image processing unit (IPU), into a single integrated circuit device. Some SOCs may have balancers which set individual frequency limits for the discrete processing units depending on a SOC power limit. When required, the frequency of a processing unit may be reactively increased, but when increased processing unit frequencies cause current or thermal limits of the system to be breached, frequency limits may be reactively imposed until the system operates within the appropriate current and thermal limits. This approach can result in sub-optimal operation of the individual processing units and may be difficult to scale at least because, due to system power constraints, the maximum frequency limit which can be allocated to each processing unit may be to some extent dependent on the activity of the other processing units. The balancer therefore may take into account the activity of all of the processing units of the SOC when setting frequency limits and, as frequency is not additive, this may increase balancer complexity. Different processing units can also have different thermal power designs, which may also be accounted for by the balancer when setting frequency limits.

Brief Description of the Drawings

Embodiments of will now be described by way of example only, with reference to the accompanying figures, in which:

Figure 1 is a conceptual block diagram of a computer processing platform having system level power balancing circuitry;

Figure 2 is a schematic block diagram of the system level power balancing circuitry of Figure 1 together with control circuitry;

Figure 3 is a more detailed schematic block diagram of the system level power balancing circuitry and control circuitry of Figure 2;

Figure 4 is a table illustrating power limits for different processing units of the computer processing platform of Figure 1 changing over time depending on utilisations of the processing units;

Figure 5 is an illustrative plot of processing unit utilisation versus frequency for a plurality of different constant power levels;

Figure 6 is a schematic diagram similar to that of Figure 2 but wherein the control of power limits is extended to platform components outside of a system-on-chip;

Figure 7 is a schematic diagram of system power level balancing circuitry similar to that shown in Figure 3, but including some optional plugins; and

Figure 8 is a flow chart illustrating a method of setting power limits for processing units of a computer processing platform.

Detailed Description of Embodiments

Illustrative embodiments of the present disclosure include, but are not limited to, methods, systems, circuitry, apparatuses and machine-readable instructions for setting power limits for processing units of a data processing platform, which may include a plurality of processing units, such as a plurality of processing units of an integrated circuit device such as a system-on-chip (SOC).

Figure 1 is a conceptual block diagram of a data processing platform 100 having system level power balancing circuitry 101 (acting as power control circuitry) in communication with a system on chip integrated circuit device (SOC) 102 and a plurality of platform components 103-107 provided off the SOC 102. In the example of Figure 1, the plurality of platform components 103-107 may include any two or more of a display 103, camera 104, connectivity module (CNV) 105 (which may comprise a radio antenna and/or circuitry such as WiFi, Bluetooth, Global Positioning System (GPS) or near field communications antenna and/or circuitry), modem 106, memory 107. The system level power balancing circuitry 101 may be in communication with the SOC 102 and the platform components 103-107 by way of a system bus 108. The SOC 102 may have a plurality of processing units. In the example of Figure 1, the SOC 102 has: at least one central processing unit (CPU) 110, such as a general purpose CPU for general purpose processing, having at least one physical core; at least one graphics processing unit (GPU) 111, such as a GPU for graphics processing, having at least one physical core; and an image processing unit (IPU) 112, such as an IPU for processing images, such as images captured by the camera 104 of the processing platform 100, having at least one physical core. However, the SOC 102 may have fewer or additional processing units, and one or more or each of the processing units may have more than one physical core. For example, the SOC 102 may have a vision processing unit for running machine vision algorithms, the vision processing unit having at least one physical core.

The processing platform 100, and thus the SOC 102 and the platform components 103- 107, receives power from one or more power sources 115. The one or more power source(s) 115 may be coupled to the processing platform 100 by one or more voltage regulators 116. The voltage regulator(s) 116 may be separate components from the power source(s) 115, or one or more of the voltage regulator(s) 116 may be integrated into the power source(s) 115. The power source(s) 115 may be alternating current (AC) power source(s) or the power source(s) 115 may be direct current (DC) power sources. For example, the power source(s) 115 may comprise (AC) mains power, or the power source(s) 115 may comprise one or more (DC) battery units, or the power source(s) 115 may comprise mains power and battery power from one or more battery units.

The system level power balancing circuitry 101 may comprise general purpose processing circuitry or special purpose circuitry. It may be that the system power balancing circuitry 101 operates by the general purpose processing circuitry or special purpose circuitry executing computer program instructions stored in and retrieved from a memory to thereby perform the functions described herein. It may be that the system power balancing circuitry 101 is provided by dedicated system level power balancing circuitry. The system level power balancing circuitry 101 may be provided by a power management unit (PMU) controller of the processing platform 100. Alternatively, it may be that the system power balancing circuitry is provided by an embedded controller. Alternatively, it may be that the system power balancing is provided by a processor of the processing platform 100 running an operating system of the processing platform 100.

The system level power balancing circuitry 101 may receive power from the power source(s) 115 by way of the voltage regulator(s) 116. The system level power balancing circuitry 101 may apportion power from the power source(s) 115 between the SOC 102 and the platform components 103-107 outside the SOC 102. The system level power balancing circuitry 101 may receive an input R 207 indicative of a system power limit for the processing platform, Psys. Psys may be the power the processing platform 100 needs in order to operate at a particular time, taking into account thermal and current conditions of the processing platform 100. It may be that the system power limit Psys is determined by control circuitry 200 or it may be that the system power limit Psys is determined by the system level power balancing circuitry 101. It may be that the system level power balancing circuitry 101 receives data indicative of the system power limit Psys from the control circuitry 200 or it may be that the system level power balancing circuitry 101 receives data indicative of the system power limit Psys from a memory. Thus the system level power balancing circuitry 101 may obtain system power limit data relating to the system power limit Psys. The system power limit data may comprise the system power limit Psys or data from which the system power limit Psys can be determined. The system level power balancing circuitry 101 may allocate respective portions (Psoc and Ppiatform components) of the system power limit Psys to the SOC 102 and the platform components 103-107. The system level power balancing circuitry 101 may apportion the part Psoc of the system power limit Psys allocated to the SOC 102 between the processing units 110-112 of the SOC 102. Alternatively, it may be that the system level power balancing circuitry 101 apportions the system level power limit Psys directly between the processing units 110-112 (and optionally the ring interconnect - see below) of the SOC 102 and one or more of the platform components 103-107 outside the SOC 102 without making a distinction between whether they are on the SOC 102 or off the SOC 102. In either case, the system level power balancing circuitry 101 may allocate a respective portion of the system power limit Psys to each of processing units 110-112 of the SOC 102 and to each of one or more of the platform components 103-107 off the SOC 102. It may be that the system level power balancing circuitry 101 may apportion the system power limit Psys between a subset (rather than all) of the processing units 110-112 of the SOC 102 and a subset (rather than all) of the platform components 103-107 off the SOC 102 if for example one or more of the processing units 110-112 or one or more of the platform components 103-107 are powered down.

In more detail, the system level power balancing circuitry 101 may receive a control input, R 207, from control circuitry 200 indicative of the system power limit Psys. As also shown in Figure 2, the control input, R 207, may be determined by control circuitry 200 depending on system parameter limits. In the illustrated example, the system parameter limits comprise: predetermined system power limits 201 (PL1, PL2) and 202 (PL3); a predetermined run-away thermal limit (RATL) 203; and a voltage regulator thermal design current (VR TDC) 204. The power limits PL1, PL2, PL3 may include a first power limit PL1 relating to a threshold for which power could be sustained for up to for example around 100 seconds, and a second, higher, power limit PL2 relating to a threshold for which power could peak for up to, for example, 100 milliseconds. The power limits may also include a third, yet higher, power limit PL3 relating to a threshold above which system power may be reduced as rapidly as possible. The power limits may also include a fourth, yet higher, power limit PL4 relating to a threshold above which system power should not exceed. The control circuitry 200 may receive feedback, for example by way of the bus 108, from sensors 205 regarding one or more parameters of the SOC 102 relevant to the power or thermal management of the SOC 102. For example, the sensors 205 may provide measurements of, for example, for each or at least a subset of the individual processing units 110-112 of the SOC 102 or for the SOC 102 as a whole: temperature, operating voltage, operating current, operating power, inter-core communication activity, operating frequency or any other parameter relevant to the power or thermal management of the SOC 102. The control circuitry 200 may determine the control input, R 207, and thus the system power limit Psys, depending on feedback from the sensors. As shown in Figure 3, the inputs to the control circuitry 200 may be processed by a filter 247 of the control circuitry 200 in order to determine the system power limit Psys.

In order to assist the system level power balancing circuitry 101 to set power limits for the processing units 110-112 of the SOC 102, the system level power balancing circuitry 101 may receive guidance data 225 relating to initial weightings to be allocated to the processing units 110-112 of the SOC 102 by way of a weight matrix 226 (see Figure 3). The initial weightings are indicative of the relative quantities of power which are expected to be used by the processing units 110-112. The guidance data 225 may contain the initial weightings or the system level power balancing circuitry 101 may determine the initial weightings from the guidance data 225. The initial weightings may be derived from package information and power bias register and user policy. Each package may have a certain maximum power associated with it. For example, if two processing units have a maximum package power of X and Y (Watts) respectively, the proportions x:(x+y) and y:(x+y) could be used to define the respective initial weights. These system defined weights may be overridden based on user’s preferences. For example, in a gaming scenario, a user preference for performance may give extra bias to graphics sub-system over the system bias. Different initial weightings may be associated with the different processing units 110-112. As will be explained below, the initial weightings provided in or determined from the guidance data 225 may be used by the system level power balancing circuitry 101 to apportion part Psoc of the system level power limit Psys between the individual processing units 110-112 of the SOC 102.

The system level power balancing circuitry 101 may further receive a user-specified Energy Performance Preference (EPP) 208 from the operating system. It may be that the EPP 208 specifies a user preference for power saving or for high performance. In the event that the user specifies a preference for power saving in the EPP 208, the system level power balancing circuitry 101 may responsively reduce the initial weightings provided in or determined from the guidance data 225. In the event that the user specifies a preference for performance in the EPP 208, the system level power balancing circuitry 101 may responsively increase the initial weightings provided in or determined from the guidance data 225.

The system level power balancing circuitry 101 may set power limits for the individual processing units 110-112 of the SOC 102 depending on their relative utilisations. The “utilisation” of a respective processing unit may refer to a proportion of the number cycles of the respective processing unit per unit time which are active cycles. The utilisation of each processing unit 110-112 may be measured in different ways for each of the processing units 110-112, and it may be that hardware (e.g. counters specific to the respective processing units) and software mechanisms are used to acquire and monitor this data.

The system level power balancing circuitry 101 may further receive inputs from the sensors 205 regarding the SOC 102, for example by way of the system bus 108. In the illustrated example of Figure 1, the system level power balancing circuitry 101 receives measurements relating to the temperature of the SOC 102 and the power usages of the processing units 110-112 of the SOC 102. As explained above, the control circuitry 200 may determine the system power limit Psys depending on inputs received from the sensors 205. The system level power balancing circuitry 101 may set power limits for the individual processing units 110-112 of the SOC 102 depending on one or more inputs received from the sensors 205. In particular, the system level power balancing circuitry 101 may set power limits for the individual processing units 110-112 of the SOC 102 depending on power usages of the processing units 110-112 which may be determined at least in part from measurements received from the sensors 205.

In more detail, the system level power balancing circuitry 101 may receive the system power limit Psys from the control circuitry 200 by way of control input R 207, and it may allocate respective portions (Psoc and Ppiatfom_components) of the system power limit Psys to the SOC 102 and the platform components 103-107 outside the SOC 102. The system level power balancing circuitry 101 may also apportion the part Psoc of the system power limit Psys allocated to the SOC 102 between the processing units 110-112 of the SOC 102. In order to allocate respective portions of the system power limit Psys to the SOC 102 and the platform components 103-107, it may be that fixed proportions of the system power limit Psys are allocated to the platform components 103-107 (Ppiatform_¥mponents) and to the SOC 102 (Psoc). The system level power balancing circuitry 101 may apportion Psoc between the processing units 110-112 by using the following equation, which may be implemented by a power limit calculator 227 of the system level power balancing circuitry 101 (see Figure 3), to determine individual power limits for each of the processing units 110-112:

Pk = Psoc * EPP * Uk * Wik / (åAxk) where: åAxk = åUkWik

Psoc is the power limit allocated to the SOC 102;

EPPWik is the weighting Wik of processing unit k scaled in accordance with respective user specified energy performance preference EPP 208; and

Uk is the utilisation of the processing unit k. such that Psoc == åPk for k = 1 to k=n, n being the number of processing units of the SOC 102 (n=3 in the illustrated example of Figure 1).

The system level power balancing circuitry 101 therefore receives utilisation data relating to utilisations of each of the processing units 110-112 (typically the utilisation data identifies the relative utilisations of each of the processing units 110-112, which may be different from each other) and sets power limits for the processing units 110-112 by apportioning the part, Psoc, of the system power limit Psys allocated to the SOC 102 between the processing units 110-112 depending on the utilisation data, by allocating a respective portion of Psoc to each of the processing units 110-112 depending on the utilisation data. Thus, the power limits of the individual processing units 110-112 of the SOC 102 may be set depending on their utilisations.

The power limits of the processing units 110-112 may be dynamically updated over time. For example, the power limits may be updated periodically (e.g. with a period of l5ms). Additionally or alternatively the power limits may be updated in response to one or more triggers. As described above, and as shown most clearly in the more detailed diagram of Figure 3, the utilisations 209 of the individual processing units 110-112 are fed back to the system level power balancing circuitry 101 which calculates the power limits of the individual processing units 110-112 depending on their utilisations 209 using the above equation. That is, when the relative utilisations 209 of the individual processing units 110- 112 change, the power limits allocated to the individual processing units 110-112 by the system level power balancing circuitry 101 are changed depending on their relative utilisations 209. It may be that, when the power limits of the processing units 110-112 are dynamically updated, a ratio of the power limit set for one of the processing units 110-112 to the power limit set for another of the processing units 110-112 changes. Additionally or alternatively it may be that, when the power limits of the processing units 110-112 are dynamically updated, a ratio of the power limit set for one of the processing units 110-112 to the system power limit Psys (or a ratio of the power limit set for one of the processing units 110-112 to the part of the system power limit allocated to the SOC 102, Psoc) changes.

As mentioned above, it may be that the power usages of the processing units 110-112 are determined at least in part from measurements provided by the sensors 205. For example, measurements of the operating frequencies of the processing units 110-112 may be obtained from the sensors 205 and the combinations of the operating frequencies and the utilisations of the processing units 110-112 may be compared to pre-characterised power models which relate frequency and utilisation to power consumption in order to determine the power usages of the processing units. The utilisations 209 of the processing units 110- 112 may be determined in a way which is specific to each processing unit 110-112. For example, for the CPU 110 or GPU 111, utilisation may be derived from internal counters of the CPU 110 or GPU 111 respectively.

The sensor and utilisation measurements may be obtained in respect of discrete periodic sample time periods (e.g. of l5ms) corresponding to the time period between periodic updates of the power limits. It may be that, in response to a relatively high utilisation and high power usage of a first processing unit of the SOC 102 during a particular sample time period, that first processing unit is allocated a higher power limit for the next sample time period. Similarly, in response to a relatively low utilisation and low power usage of a second processing unit of the SOC 102 during the same particular sample time period, that second processing unit is allocated a lower power limit for the next sample time period, part of the power limit of the second processing unit from the earlier sample time period being allocated to the first processing unit for the later sample time period.

The utilisations 209 of the processing units may be taken into account by way of the above equation. It may be that the initial weightings Wik associated with the processing units 110-112 are adjusted for later sample time periods depending on the power usages of the processing units 110-112 during the earlier sample time period. It may be that the weighting Wik associated with a given processing unit for a given sample time period is adjusted depending on a comparison between the power limit associated with that processing unit during the previous sample time period and its actual power usage during the previous sample time period. For example, if the power limit is significantly larger than the actual power usage in a given sample period, it may be that the power limit for that processing unit is reduced for the next sample time period. Conversely, if the actual power usage of the processing unit for a given sample time period is close to the power limit, it may be that the power limit for that processing unit is increased for the next sample time period.

Example pseudo code for updating the power limits of the processing units 110-112 by dynamically apportioning Psoc between them depending on their relative utilisations 209 is as follows:

0:

Initialise weightings for each processing unit 110-112 from received package information and power bias register and user policy

1:

a. At each sample, for each processing unit 110-112 of the SOC 102, receive utilisation data relating to the utilisation of that processing unit 110-112 ;

b. Adjust the weighting for that processing unit depending on its utilisation (e.g. multiply the weighting by the utilisation);

c. Calculate the power limit for each processing unit by apportioning Psoc between them depending on their relative utilisations;

d. Set power limit for each processing unit 110-112 of the SOC 102, for example by outputting the respective calculated power limits to the respective one of the processing units 110-112 to which they apply;

2:

a. On next sample evaluate the actual power consumed by each processing unit 110- 112 of the SOC 102 versus the power limit of that processing unit;

b. Re-adjust the weighting for each processing unit depending on the actual power consumed by each processing unit 110-112 of the SOC 102 versus the power limit of that processing unit; and

c. Revert to lb

In 2b, the actual power consumed by each processing unit 110-112 in a sample period may be determined as described above by comparing the utilisation and frequency of each processing unit 110-112 in that sample period to a pre-characterised power model which relates utilisation and frequency to power consumption for that processing unit. This actual power consumption may be used to revise the weightings. The weighting associated with a processing unit may be increased (for example) if the actual power consumption of that processing unit is close to the power limit allocated to that processing unit, while the weighting for that processing unit may be decreased (for example) if the actual power consumption of that processing unit is significantly below the power limit allocated to that processing unit. In the next repetition of la-lc, the power limit for that processing unit for the next sample period is derived using the accordingly using the revised weighting.

An example implementation of the dynamic apportioning of Psoc between the processing units 110-112 of the SOC 102 is illustrated in the exemplary table of Figure 4. In the example of Figure 4, the thermal design power (TDP) of the SOC 102, and Psoc, is assumed to 10W, but it will be understood that this is not necessarily the case; Psoc may be greater than or less than 10W and indeed may change over time. It will be assumed that EPP 208 is equal to 1 such that the initial weightings and the weightings scaled for EPP 208 are equal to each other. It will also be assumed that the weightings associated with the processing units 110-112 are not adjusted depending on actual power usage in this example.

On the first row of the table, the initial weighting for the CPU 110 is 50, the initial weight of the GPU 111 is 40 and the initial weighting of the IPU 112 is 10. The utilisations 209 of the CPU 110, GPU 111 and IPU 112 are 100%. The products of the utilisations 209 and the initial weightings for the CPU 110, GPU 111 and IPU 112 are thus 50, 40 and 10. These products define how the system level power balancing circuitry 101 apportions Psoc between CPU 110, GPU 111 and IPU 112 using the above equation. In this case, the individual power limits of the CPU 110, GPU 111 and IPU 112 are 5W, 4W and 1W.

In the second row, the utilisations 209 of each of the CPU 110, GPU 111 and IPU 112 drop from 100% to 50%. This causes the products of the initial weightings and the utilisations 209 to drop to 25, 20 and 5 respectively, but because the utilisations 209 do not change relative to each other, by the above equation, the power limits of the CPU 110, GPU 111 and IPU 112 remain at 5W, 4W and 1W respectively. Similarly in the third row of the table of Figure 4, the utilisations 209 of each of the CPU 110, GPU 111 and IPU 112 drop to 10%. This causes the products of the initial weightings and the utilisations 209 to drop to 5, 4 and 1 but again because the utilisations 209 do not change relative to each other, by the above equation, the power limits of the CPU 110, GPU 111 and IPU 112 remain at 5W, 4W and 1 W.

In the fourth row of the table, the utilisations 209 of the CPU 110, GPU 111 and IPU 112 are 50%, 100%, 100% respectively. Accordingly, the products of the initial weightings and the utilisations 209 become 25, 40, 10. Because the relative utilisations 209 of the processing units 110-112 have changed, the power limits allocated to the CPU 110, GPU 111 and IPU 112 also change. By the above equation, the power limits allocated to the CPU 110, GPU 111 and IPU 112 are 3.3W, 5.3W, 1.3W respectively. Thus, as a result of the ratio of the utilisation of the GPU 111 or IPU 112 to the utilisation of the CPU 110 becoming greater than it was previously, the revised power limit set for the CPU 110 is less than the previous power limit set for the CPU 110, and the revised power limits set for the GPU 111 and IPU 112 are greater than their previous power limits. In addition, the ratio of the revised power limits of the GPU 111 or IPU 112 to the revised power limit of the CPU 110 (5.3/3.3 or 1.3/3.3 respectively) is greater than the corresponding ratio of the previous power limit of the GPU 111 or IPU 112 to the previous power limit of the CPU 110 (5/4 or 1/4 respectively). In addition, the ratio of the revised power limit of the CPU 110 to Psoc (3.3/10) is less than the ratio of the previous power limit of the CPU 110 to Psoc (5/10).

In the next row, the utilisations 209 of the CPU 110, GPU 111 and IPU 112 change to 50%, 100%, 50% respectively, causing, by the above equation, the power limits of the CPU 110, GPU 111 and IPU 112 to change to 3.6W, 5.7W and 0.7W respectively. Again, the ratios of the power limits to each other and to Psoc have changed compared to the previous row in the table.

In the next row, the utilisations 209 of the CPU 110, GPU 111 and IPU 112 change to 25%, 25%, 50% respectively, causing, by the above equation, the power limits of the CPU 110, GPU 111 and IPU 112 to change to 4.5W, 3.6W, 1.8W respectively. Again, the ratios of the power limits to each other and Psoc have changed compared to the previous row in the table.

In the next row, the utilisations 209 of the CPU 110, GPU 111 and IPU 112 change to 50%, 25%, 50% respectively, causing, by the above equation, the power limits of the CPU 110, GPU 111 and IPU 112 to change to 5.6W, 2.2W, 2.2W respectively. Again, the ratios of the power limits to each other and Psoc have changed compared to the previous row in the table.

In the next row, the utilisations 209 of the CPU 110, GPU 111 and IPU 112 change to 100%, 25%, 25% respectively, causing, by the above equation, the power limits of the CPU 110, GPU 111 and IPU 112 to change to 8W, 1.6W, 0.4W respectively. Again, the ratios of the power limits to each other and Psoc have changed compared to the previous row in the table.

In the next row, the utilisations 209 of the CPU 110, GPU 111 and IPU 112 change to 50%, 50%, 60% respectively, causing, by the above equation, the power limits of the CPU 110, GPU 111 and IPU 112 to change to 4.9W, 3.9W, 1.2W respectively. Again, the ratios of the power limits to each other and Psoc have changed compared to the previous row in the table.

In the next row, the utilisations 209 of the CPU 110, GPU 111 and IPU 112 change to 50%, 100%, 100% respectively, causing, by the above equation, the power limits of the CPU 110, GPU 111 and IPU 112 to change to 3.3W, 5.3W, 1.3W respectively, which is the same as it was in row 4 as described above. Again, the ratios of the power limits to each other and Psoc have changed compared to the previous row in the table.

Finally, the utilisations 209 of the CPU 110, GPU 111 and IPU 112 change to 10%, 10%, 10% respectively, causing, by the above equation, the power limits of the CPU 110, GPU 111 and IPU 112 to change to 5W, 4W, 1W respectively. Again, the ratios of the power limits to each other and Psoc have changed compared to the previous row in the table.

Thus, if the utilisations 209 of one or more processing units 110-112 increase while the utilisations 209 of one or more other processing units 110-112 decrease, additional power budget by way of a higher power limit is dynamically allocated to the processor 110-112 having the higher utilisation and less power budget by way of a lower power limit is dynamically allocated to the processing unit 110-112 with having lower utilisation. In this way, power is dynamically shared between processing units 110-112 to where it is most needed, improving the energy efficiency, the performance, or both the energy efficiency and performance of the processing platform 100 as a whole.

It will be understood that, although the above description of Figure 4 assumes that Psoc remains constant, Psoc may alternatively be variable. In this case, the power limits allocated to the processing units 110-112 would of course be scaled in accordance with revised values for Psoc.

Referring back to Figure 1, the power limits for the CPU 110, GPU 111 and IPU 112 are output from the system level power balancing circuitry 101 to the SOC 102, and SOC power balancing circuitry 230 may output the individual power limits to the respective processing units CPU 110, GPU 111 and IPU 112. It will be understood that the SOC power balancing circuitry 230 may comprise processing circuitry executing computer program instructions to perform the functions described herein. The processing circuitry of the SOC balancing circuitry may be general purpose or special purpose processing circuitry. The processing circuitry of the SOC power balancing circuitry 230 may comprise processing circuitry dedicated to perform the functions of the SOC power balancing circuitry 230 described herein, or the processing circuitry of the SOC power balancing circuitry 230 may comprise processing circuitry which also performs additional functions. It may be that the SOC balancing circuitry 230 is provided on the SOC 102; alternatively, the SOC balancing circuitry 230 may be provided off the SOC 102.

Providing a respective individual power limit to each of the processing units 110-112 allows the individual processing units 110-112 to decide how best, for example for energy efficiency or for high performance, to use the respective power budgets allocated to them by the system level power balancing circuitry 101. Each of the respective processing units 110-112 may receive their respective power limits and select a performance state, for example including a performance operating frequency and utilisation, depending on their respective power limits. Figure 5 shows a plurality of plots 241-244 of utilisation versus frequency for a given processing unit, which may be for example CPU 110, GPU 111 or IPU 112, each of the plots being an isometric power line, that is a line defining combinations of utilisation and frequency of the processing unit which consume the same quantity of power. Each of the processing units 110-112 may select a performance state which best suits the needs of that processing unit 110-112 and which lies on an isometric power line associated with a power which is less than the power limit allocated to that processing unit.

Although the above description focuses on the system level power balancing circuitry 101 dynamically allocating power limits for the processing units 110-112 of the SOC 102, it will be understood that this could be extended to other components of the processing platform 100 including other components of the SOC 102 and platform components 103- 107 outside of the SOC 102. This can be readily done because power is additive, unlike frequency for example. For example, the SOC 102 may comprise a ring interconnect (not shown) for bringing the processing units 110-112 of the SOC 102 into communication with each other, and it may be that the system level power balancing circuitry 101 apportions Psoc between not only the processing units 110-112 of the SOC 102 but between the individual processing units 110-112 and the ring interconnect. In this case, it may be that the system level power balancing circuitry 101 allocates a fixed power limit 240 (see Figure 2) to the ring interconnect and dynamically apportions the remainder of Psoc (i.e. Psoc - P ring_interconnect, where Prmgjnterconnect is the fixed power limit 240 allocated to the ring interconnect) between the processing units 110-112 depending on their initial weightings and their utilisations and optionally their power usages. Alternatively, it may be that the system level power balancing circuitry 101 allocates a weighting to the ring interconnect and dynamically apportions Psoc between the ring interconnect and the individual processing units 110-112 over time depending on their weightings and on the utilisations 209 of the processing units 110-112. It may be that the system level power balancing circuitry 101 takes into account a monitored usage parameter relating to the usage of the ring interconnect and dynamically allocates a respective portion of Psoc to the ring interconnect depending on the monitored usage parameter, and typically also depending on the utilisations of the processing units 110-112 (and optionally on usage parameters of one or more components 103-107 off the SOC 102 as described below). The monitored usage parameter may relate to the power consumption of the ring interconnect in one or more previous sample time periods (for example) or may be derived from workload data relating to a type of workload being performed or expected to be performed by the SOC 102. The workload data may be received from the operating system, for example. In any event, it may be that the portion of the Psoc allocated to the ring interconnect should be kept above a threshold level (if necessary by overriding the power limit apportioned to the ring interconnect in dependence on the utilisations of the processing units 110-112 and on the usage parameter of the ring interconnect) to maintain an acceptable speed of communication between processing units 110-112.

Similarly, as shown in Figure 6, the system level power balancing circuitry 101 may dynamically apportion the system level power limit P _sys or part of the system level power limit Psys between the processing units 110-112, and optionally the ring interconnect, of the SOC 102 and between one or more of the platform components 103-107 outside of the SOC 102 such as the display 103 or modem 106, rather than simply allocating a fixed portion of Psys to one or more of the platform components 103-107 outside of the SOC 102 as described above. Figure 6 also shows that power may be fed to the SOC 102 and the platform components 103-107 by different voltage regulators 245, 246. Although the display 103 and modem 106 are shown in Figure 6, it will be understood that the system level power balancing circuitry 101 may dynamically apportion the system level power limit Psys between the processing units 110-112 and optionally the ring interconnect of the SOC 102 and any one or more of the platform components 103-107 outside of the SOC 102. In this case, the system level power balancing circuitry 101 may receive guidance data 250 (see Figures 1 and 6) comprising initial weightings, or from which initial weightings can be determined, for each of the platform components 103-107 outside of the SOC 102 for which power limits are to be dynamically apportioned from Psys. For example the guidance data 250 (which may for example be received from the operating system) may provide system level power data associated with the power consumption of each of the platform components 103-107, and respective weightings for each of the platform components 103-107 may be derived depending on the system level power data. As above, these weightings may be overridden depending on user preferences.

The respective portions of Psys allocated to the platform components 103-107 may be dynamically updated depending on the initial weightings and respective monitored usage parameters relating to usages of the platform components 103-107, and optionally depending on the utilisations of the processing units 110-112 and optionally on the monitored usage parameter of the ring interconnect. The monitored usage parameters may relate to the power consumption of the respective platform components 103-107 in one or more previous sample time periods (for example) or may be derived from workload data relating to a type of workload being performed or expected to be performed by the processing platform. The workload data may be received from the operating system, for example.

A similar equation to that described above for the SOC 102 may be applied for the processing platform 100 to apportion Psys or a portion of Psys between the processing units 110-112, the ring interconnect and one or more of the platform components 103-107 outside of the SOC 102. Power budget can thereby be dynamically distributed between them based on their weightings and monitored usage parameters (which may be the utilisations 209 in the case of the processing units 110-112) to where it is most needed. It may be that the weightings associated with the platform components 103-107 or the ring interconnect are updated depending on their power usages in one or more previous sample time periods.

As illustrated in Figure 7, the system level power balancing circuitry 101 may further receive from the operating system workload data 260 relating to a type of workload being performed or expected, for example scheduled, to be performed by the SOC 102. The type of workload may be specified in terms of a type of application or a type of task to be performed by an application to be executed by the SOC 102, such as a word processing task or application or image processing task or application. The type of workload may be indicative of likely future utilisations of the respective processing units 110-112 which may have different current or future utilisations from each other depending on the type of workload to be performed, and the system level power balancing circuitry 101 may take this into account when determining the individual power limits for the processing units 110-112 of the SOC 102. For example, the workload data may be taken into account by way of a workload multiplier to the relevant weightings, the said multiplier in some cases being different for one or more or each of the processing units 110-112 from the others. In one example, the workload data specifies that the SOC 102 is to process images captured by the camera 104. In this case, the workload multiplier associated with the IMU 112 may be increased, while the workload multiplier associated with the GPU 111 may be decreased and the workload multiplier associated with the CPU 110 may be kept constant.

As also shown in Figure 7, the system level power balancing circuitry 101 may also receive performance state prediction data 270 relating to probable subsequent performance states of the processing units 110-112. The performance state prediction data 270 may be based on historical performance state data relating to historical performance states, the performance state typically being a combination of a utilisation and an operating frequency, of the processing units 110-112. For example, the performance state prediction data 270 may be determined from a statistical analysis, or mathematical model, of logged historical performance states of the processing units 110-112. For example, a hidden Markov Model may be generated by applying one or more machine learning algorithms (e.g. the Baum-Welch algorithm) to respective historical performance states of the processing units 110-112. The most probable next performance states of the processing units 110-112 may be determined from the mathematical model depending on the current performance states of the processing units 110-112. The performance state prediction data 270 may be provided to the system level power balancing circuitry 101 together with the workload data 260 as shown in Figure 7 or it may be provided separately from the workload data 260. The performance state prediction data 270 may be taken into account by the system level power balancing circuitry 101 to determine the power limits of the processing units 110-112, optionally by way of an performance state prediction multiplier applied to the weightings associated with the respective processing units 110-112. The performance state prediction multiplier for each processing unit 110-112 may be selected depending on the probable next performance state of that processing unit from the performance state prediction data 270. For example, if the probable next performance state of a processing unit is a high utilisation, high frequency state, a higher multiplier may be selected and applied for that processing unit; conversely if the probable next performance state of a processing unit is a low utilisation, low frequency state, a lower multiplier may be selected and applied for that processing unit. It may be that any workload data 260 provided is prioritised over the performance state prediction data 270 or vice versa or they may be both taken into account together with equal weighting.

As also shown in Figure 7, the system level power balancing circuitry 101 may also determine or receive power usage strategy data 280 relating to a power usage strategy to be implemented by the system level power balancing circuitry 101. For example, the system level power balancing circuitry 101 may determine a power usage strategy depending on one or more system parameters. For example, the system level power balancing circuitry 101 may select a power usage strategy from a plurality of candidate power usage strategies depending on any one or more of: received system event data 220 (see Figure 1); fuel gauge data 210 (see Figure 1); utilisations 209 of one or more of the processing units 110-112; historical power consumptions of one or more of the processing units 110-112 (see Figure 1); estimated cost of available power usage strategies, which may be determined depending on power source availability. For example, the candidate power usage strategies may comprise a (lower power) power saving power usage strategy and a (higher power) high performance power usage strategy.

The received system event data 220 may, for example, provide information as to whether mains power is available to the processing platform 100 or whether it is reliant solely on battery power. For example, the system event data 220 may provide information as to whether the device comprising the processing platform 100 is docked or undocked. If the processing platform 100 is docked, it may be inferred that the processing platform 100 has access to mains power; if the processing platform 100 is undocked it may be inferred that the processing platform is reliant on battery power. If mains power is available, the system level power balancing circuitry 101 may tend towards selecting a high performance power usage strategy from the plurality of candidate power usage strategies; conversely, if the device is reliant solely on battery power the system level power balancing circuitry 101 may tend towards selecting a power saving power usage strategy from the plurality of candidate power usage strategies.

It may be that the system power level balancing circuitry 101 determines the power usage strategy depending on fuel gauge data 210 (see Figure 1) which may comprise a maximum available battery power PMAX BAT from the battery. If the fuel gauge data 210 indicates that PMAX BAT is relatively low, it may tend towards selecting the power saving power usage strategy; if the fuel gauge data 210 indicates that PMAX BAT is relatively high, it may tend towards selecting the high performance power usage strategy. Similarly, if utilisations 209 of the processing units 110-112 are high, the system level power balancing circuitry 101 may tend towards selecting the high performance power usage strategy; conversely, if utilisations 209 of the processing units 110-112 are low, the system level power balancing circuitry 101 may tend towards selecting the power saving power usage strategy. If historical power consumption of the processing units 110-112 is high, the system level power balancing circuitry 101 may tend towards selecting the high performance power usage strategy; conversely, if historical power consumption of the processing units 110- 112 is low, the system level power balancing circuitry 101 may tend towards selecting the power saving power usage strategy. The cost of a power usage strategy may be determined on the basis of rewards or penalties, such as reward scores or penalty scores, which may be associated with particular strategies. The rewards or penalties may depend on power source availability data, which may be inferred from system event data 220 for example. For example, the rewards or penalties may depend on whether mains power is available, or if mains power is not available, whether a battery charge level is below a threshold. If mains power is available, and optionally if battery charge level is above a threshold, a reward may be allocated if the high-performance strategy is selected and a lesser reward or a penalty may be allocated if the power saving power usage strategy is selected. If mains power is not available, or optionally if battery charge level is below a threshold, a reward may be allocated if the power saving strategy is selected and a lesser reward or a penalty may be allocated if the high-performance power usage strategy is selected.

It will be understood that, instead of the system level power balancing circuitry 101 selecting the power usage strategy from the plurality of candidate power strategies, it may be that one or more of the individual processing units 110-112 each select a power usage strategy from a plurality of predetermined candidate power usage strategies. For example, each processing unit 110-112 may select a power usage strategy from a plurality of predetermined candidate power usage strategies depending on any one or more of: received system event data 220; fuel gauge data 210; its utilisation; its historical power consumption; estimated cost of available power usage strategies, which may be determined depending on power source availability. In this case, the processing units 110- 112 may each provide respective power usage strategy data to the system level power balancing circuitry 101 which may set power limits depending thereon.

It may be that the same power usage strategy is selected for each of the processing units 110-112. Alternatively in some cases it may be that different power usage strategies are selected for different processing units. In either case, the system level power balancing circuitry 101 may set power limits of the individual processing units 110-112 depending on the power usage strategy data 280. For example, the power usage strategy, or the power usage strategy for a particular processing unit 110-112, may be taken into account in the above power limit equation by way of a power usage strategy multiplier applied to the relevant weightings. Figure 8 is a flow-chart illustrating a method of setting power limits for processing units of the processing platform 100. The method may comprise at 301 receiving a system power limit Psys for the processing platform 100. The method may further comprise determining a power limit Psoc for the SOC 102 from Psys. Alternatively it may be that no intermediate power limit for the SOC 102 is determined, and the system power limit Psys or a portion of the system power limit Psys may be apportioned directly between the processing units 110-112 of the SOC 102 and one or more of the platform components 103-107 outside of the SOC 102 and optionally the ring interconnect of the SOC 102, without making a distinction between whether they are on the SOC 102 or off the SOC 102. At 302, the method may comprise, for a respective sample time period, receiving utilisation data relating to utilisations 209 of each of the processing units 110-112 of the processing platform 100. At 302, the method may further comprise receiving power usage data relating to the power usages of each of the processing units 110-112 during the respective sample time period or more typically this may be taken into account in revised weightings used at 303. At 303, the method may comprise setting power limits for the processing units 110-112 by apportioning part, Psoc, of the system power limit Psys allocated to the SOC 102 between at least the processing units 110-112 (e.g. between the processing units 110-112 or between the processing units 110-112 and the ring interconnect of the SOC 102) depending on the utilisation data/usage parameters and the (revised) weightings for the respective sample time period. Alternatively at 303 the method may comprise apportioning Psys or a portion of Psys directly between the processing units 110-112 of the SOC 102 and one or more platform components 103-107 outside of the SOC 102, and optionally to the ring interconnect of the SOC 102, without making a distinction as to whether they are on the SOC 102 or off the SOC 102. The method may comprise between 301 and 302 allocating respective portions of the system power limit Psys to the SOC 102 and the platform components 103-107 outside the SOC 102, thereby determining Psoc. At 303, the method may comprise calculating the power limits of the processing units 110-112 depending on the utilisation data and outputting the respective power limits to the respective processing units 110-112 to thereby set the power limits for the processing units 110-112.

From 303, the method reverts to 301 and repeats 301-303 to thereby dynamically update the power limits of the processing units 110-112 depending on their utilisations 209 for each successive sample time period. As explained above, it may be that for a given sample time period, the weightings associated with the individual processing units 110-112 may be adjusted depending on their power usages in an immediately previous sample time period. It may be that the weighting associated with a given processing unit for a given sample time period is adjusted depending on a comparison between the power limit associated with that processing unit during the previous sample time period and its actual power usage during the previous sample time period. For example, if the power limit is significantly larger than the actual power usage, it may be that the power limit for that processing unit is reduced for the given sample time period. Conversely, if the actual power usage of the processing unit for the previous sample time period is close to the power limit, it may be that the power limit for that processing unit is increased for the given sample time period.

It will be understood that, particularly but not exclusively in examples in which the system level power balancing circuitry 101 allocates a fixed portion of Psys to the platform components 103-107 outside the SOC 102, it may be that some or all of the functionality of the system level power balancing circuitry 101 relating to dynamically apportioning Psoc between the processing units 110-112 is instead performed by the power balancing circuitry 230 of the SOC 102 (in which case the power balancing circuitry 230 of the SOC 102 may act as power control circuitry, and Psoc may be a received system power limit for the SOC 102).

It will also be understood that, although the SOC 102 illustrated in the figures and described above has three processing units 110-112, there may alternatively be more than three or fewer than three processing units 110-112.

It may be that one or more or each of the processing units of the SOC 102 have more than one physical core, and in this case it may be that the system level power balancing circuitry 101, or the SOC power balancing circuitry 230 as the case may be, apportions Psoc between at least each of the physical cores of the processing units individually. That is, each of the physical cores may be treated as a separate processing unit in the sehing of their power limits. Alternatively it may be that Psys or part of Psys is apportioned between one or more of the platform components 103-107 and the individual cores of the processing units 110-112 directly without a distinction being made as to whether they are on or off the SOC 102. It will also be understood that Psoc may be fixed or variable, which may depend on whether the power budget allocated to the platform components 103-107 outside of the SOC 102 is fixed or variable. In this case, utilisation data relating to the utilisations 209, and optionally power usage data relating to power usages, of each of the physical cores may be fed back to the system level power balancing circuitry 101 or the SOC power balancing circuitry 230 as the case may be to allow the apportioning of power budget to be performed depending on the utilisations 209 of the cores.

While the above examples describe Psoc being apportioned between processing units 110- 112 of a SOC 102, it will be understood that in alternative examples it may be that at least part of a system power limit Psys of a processing platform is apportioned between processing units which are not part of a SOC 102 depending on their utilisations 209. It may be that at least part of a system power limit Psys is apportioned between processing units of an alternative integrated circuit device depending on their utilisations 209. For example, at least part of a system power limit Psys may be apportioned between discrete nodes within the hierarchy of a multi-core central or graphics processing unit depending on their utilisations.

While the above examples describe the system power limit Psys provided by the control circuitry 200 as being a power limit associated with the processing platform, it may be that the power limit Psys output by the control circuitry 200 is alternatively a power limit for the SOC 102. That is, in some examples, the power limit output Psys by the control circuitry 200 is the power limit for the SOC 102, Psoc (which in this case may be a received system power limit for the SOC 102).

Although Figures 2 and 6 show only two inputs (guidance data 225, 250 and EPP 208) to the system level power balancing circuitry 101, it will be understood that the system level power balancing circuitry 101 may contain any or all of inputs to the system level power balancing circuitry 101 described herein.

In this specification, the phrase“at least one of A or B” and the phrase“at least one of A and B” and should be interpreted to mean any one or more of the plurality of listed items A, B etc., taken jointly and severally in any and all permutations. Where functional units have been described as circuitry, the circuitry may be general purpose processor circuitry configured by program code to perform specified processing functions. The circuitry may also be configured by modification to the processing hardware. Configuration of the circuitry to perform a specified function may be entirely in hardware, entirely in software or using a combination of hardware modification and software execution. Program instructions may be used to configure logic gates of general purpose or special-purpose processor circuitry to perform a processing function.

Circuitry may be implemented, for example, as a hardware circuit comprising processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application specific integrated circuits (ASIC), programmable logic devices (PLD), digital signal processors (DSP), field programmable gate arrays (FPGAs), logic gates, registers, semiconductor devices, chips, microchips, chip sets, and the like.

The processors may comprise a general purpose processor, a network processor that processes data communicated over a computer network, or other types of processor including a reduced instruction set computer RISC or a complex instruction set computer CISC. The processor may have a single or multiple core design. Multiple core processors may integrate different processor core types on the same integrated circuit die.

Machine readable program instructions may be provided on a transitory medium such as a transmission medium or on a non-transitory medium such as a storage medium. Such machine readable instructions (computer program code) may be implemented in a high level procedural or object oriented programming language. However, the program(s) may be implemented in assembly or machine language, if desired. In any case, the language may be a compiled or interpreted language, and combined with hardware implementations.

Embodiments are applicable for use with all types of semiconductor integrated circuit (“IC”) chips. Examples of these IC chips include but are not limited to processors, controllers, chipset components, programmable logic arrays (PLAs), memory chips, network chips, and the like. In some embodiments, one or more of the components described herein may be embodied as a System On Chip (SOC) device. A SOC may include, for example, one or more Central Processing Unit (CPU) cores, one or more Graphics Processing Unit (GPU) cores, on or more Image Processing Unit (IPU) cores, a ring interconnect, an Input/Output interface and a memory controller. In some embodiments a SOC and its components may be provided on one or more integrated circuit die, for example, packaged into a single semiconductor device.

Examples

The following examples pertain to further embodiments. 1. Power control circuitry comprising processing circuitry to:

obtain system power limit data relating to a system power limit for a data processing platform comprising a plurality of processing units;

obtain utilisation data relating to utilisations of the plurality of processing units; and

set power limits for the plurality of processing units by apportioning at least part of the system power limit between at least the plurality of processing units depending on the utilisation data.

2. Power control circuitry according to example 1 wherein the processing circuitry is to determine power usages of the plurality of processing units and to set the power limits of the plurality of processing units depending on the utilisation data and on the determined power usages of the plurality of processing units.

3. Power control circuitry according to example 1 or example 2 wherein the processing circuitry is to adjust the power limits of each of one or more of the plurality of processing units for a later time period depending on a comparison between a power limit set for that processing unit for an earlier time period and a determined power usage of that processing unit during that earlier time period.

4. Power control circuitry according to any preceding example wherein the processing circuitry is further to:

associate a respective weighting with each of the plurality of processing units; and

set the said power limits for the plurality of processing units depending on the utilisation data and on the respective weightings associated with the plurality of processing units.

5. Power control circuitry according to any preceding example wherein the processing circuitry is further to:

set the power limits for the plurality of processing units depending on the utilisation data and on a user specified energy performance preference.

6. Power control circuitry according to any preceding example wherein the processing circuitry is further to:

obtain workload data relating to future utilisations of the plurality of processing units; and

set the said power limits for the plurality of processing units depending on the utilisation data and on the workload data.

7. Power control circuitry according to example 6 wherein the obtained workload data comprises data indicative of one or more types of application to be run by the data processing platform. 8. Power control circuitry according to any preceding example wherein the processing circuitry is further to: dynamically update the power limits set for the plurality of processing units by apportioning at least part of the system power limit between at least the plurality of processing units depending on subsequent utilisation data relating to subsequent utilisations of the plurality of processing units.

9. Power control circuitry according to any preceding example wherein the processing circuitry is further to: obtain subsequent system power limit data relating to a subsequent system power limit for the data processing platform; and to dynamically update the power limits set for the plurality of processing units by apportioning at least part of the subsequent system power limit between at least the plurality of processing units depending on subsequent utilisation data relating to subsequent utilisations of the plurality of processing units. 10. Power control circuitry according to any preceding example wherein the processing circuitry is to dynamically update the power limits set for first and second processing units of the plurality of processing units in response to a change in the relative utilisations of the plurality of processing units, thereby changing a ratio of the power limit set for the first processing unit to the power limit set for the second processing unit.

11. Power control circuitry according to any preceding example wherein the processing circuitry is to dynamically update the power limit set for a first processing unit of the plurality of processing units in response to a change in the relative utilisations of the processing units, thereby changing a ratio of the power limit set for the first processing unit to the system power limit.

12. Power control circuitry according to any preceding example wherein the plurality of processing units are provided in the same integrated circuit.

13. Power control circuitry according to any of examples 1 to 11 wherein the plurality of processing units are not provided in the same integrated circuit.

14. Power control circuitry according to any preceding example wherein the plurality of processing units comprises any two or more of: a central processing unit; a graphics processing unit; an image processing unit; a vision processing unit; a first physical core of a multi-core processing unit; a second physical core of a multi core processing unit; a first physical core of a multi-core central processing unit or multi-core graphics processing unit or multi-core image processing unit or multi core vision processing unit; a second physical core of the multi-core central processing unit or multi-core graphics processing unit or multi-core image processing unit or multi-core vision processing unit.

15. Power control circuitry according to any preceding example wherein the processing circuitry is further to:

obtain power usage strategy data relating to power usage strategies for the plurality of processing units; and

set the power limits for the plurality of processing units depending on the utilisation data and on the power usage strategy data. 16. Power control circuitry according to example 15 wherein the processing circuitry obtains the power usage strategy data from the plurality of processing units.

17. Power control circuitry according to example 15 or example 16 wherein the power usage strategies for the plurality of processing units are power usage strategies determined depending on any one or more of: system event data relating to power source availability; fuel gauge data relating to a maximum available battery power; utilisations of one or more of the plurality of processing units; historical power consumptions of one or more of the plurality of processing units; relative estimated costs of a plurality of candidate power usage strategies.

18. Power control circuitry according to any of examples 15 to 17 wherein the estimated cost of each of the candidate power usage strategies is determined depending on a power usage of the respective candidate power usage strategy and power source availability.

19. Power control circuitry according to any preceding example wherein the processing circuitry is to: obtain performance state prediction data relating to probable subsequent performance states of the plurality of processing units; and to set the power limits for the plurality of processing units depending on the obtained performance state prediction data.

20. Power control circuitry according to any preceding example wherein the plurality of processing units are processing units of an integrated circuit device of the data processing platform.

21. Power control circuitry according to example 20 wherein the integrated circuit device comprises a system-on-chip.

22. Power control circuitry according to example 20 or example 21 wherein the processing circuitry is to allocate part of the system power limit to the integrated circuit device and wherein said at least part of the system power limit comprises or consists of the part of the system power limit allocated to the integrated circuit device. 23. Power control circuitry according to example 20 or example 21 wherein the integrated circuit comprises a ring interconnect for bringing the processing units into communication with each other, and wherein the processing circuitry is to set a power limit for the ring interconnect by apportioning at least part of the system power limit between at least the processing units of the said plurality of processing units and the ring interconnect.

24. Power control circuitry according to example 23 wherein the processing circuitry is to set the power limit for the ring interconnect by apportioning at least part of the system power limit between at least the processing units of the said plurality of processing units and the ring interconnect depending on a usage parameter relating to usage of the ring interconnect and optionally depending on the utilisation data.

25. Power control circuitry according to example 23 or example 24 wherein the processing circuitry is to dynamically update the power limit set for the ring interconnect by apportioning at least part of the system power limit between at least the processing units of the said plurality of processing units and the ring interconnect depending on a monitored usage parameter relating to a subsequent usage of the ring interconnect and optionally depending on subsequent utilisation data relating to subsequent utilisations of the processing units.

26. Power control circuitry according to example 20 or example 21 wherein the processing circuitry is to allocate a first portion of the system power limit to the integrated circuit device and a second portion of the system power limit to one or more components of the data processing platform which are not provided in the integrated circuit.

27. Power control circuitry according to example 20 or example 21 wherein the data processing platform further comprises one or more components which are not provided in the integrated circuit, wherein the processing circuitry is to set power limits for each of the one or more components by apportioning at least part of the system power limit between at least the processing units of the said plurality of processing units and the one or more components depending on respective monitored usage parameters relating to the usages of the one or more components and optionally depending on the utilisation data.

28. Power control circuitry according to example 26 or example 27 wherein the processing circuitry is to dynamically update the power limits set for the one or more components by apportioning at least part of the system power limit between at least the processing units of the said plurality of processing units and the one or more components depending on respective monitored usage parameters relating to subsequent usages of the one or more components and optionally depending on subsequent utilisation data relating to subsequent utilisations of the processing units.

29. A data processing platform comprising:

a plurality of processing units; and

the power control circuitry according to any preceding example to set power limits for the plurality of processing units.

30. An embedded controller comprising the power control circuitry according to any of examples 1 to 28.

31. A power management unit controller comprising the power control circuitry according to any of examples 1 to 28.

32. Machine-readable instructions provided on at least one machine-readable medium, the machine-readable instructions, when executed, to cause processing hardware to:

obtain system power limit data relating to a system power limit for a data processing platform comprising a plurality of processing units;

obtain utilisation data relating to utilisations of the plurality of processing units; and

set power limits for the plurality of processing units by apportioning at least part of the system power limit between at least the plurality of processing units depending on the utilisation data.

33. An operating system comprising the machine-readable instructions of example 32. 34. The machine-readable instructions of example 32 provided on a non-transitory storage medium.

35. A method of setting power limits for processing units of a data processing platform, the method comprising:

obtaining system power limit data relating to a system power limit for the data processing platform;

obtaining utilisation data relating to utilisations of a plurality of processing units of the data processing platform; and

setting power limits for the plurality of processing units by apportioning at least part of the system power limit between at least the plurality of processing units depending on the utilisation data.

36. A method according to example 35 comprising: determining power usages of the plurality of processing units; and setting the power limits of the plurality of processing units depending on the utilisation data and on the determined power usages.

37. A method according to example 35 or example 36 further comprising: adjusting the power limits set for each of one or more of the plurality of processing units for a later time period depending on a comparison of the power limit and determined power usage of that processing unit during an earlier time period.

38. A method according to any of examples 35 to 37 comprising: associating a respective weighting with each of the plurality of processing units; and setting the power limits for the plurality of processing units depending on the utilisation data and on the respective weightings associated with the plurality of processing units.

39. A method according to any of examples 35 to 38 comprising: setting the power limits for the plurality of processing units depending on the utilisation data and on a user specified energy performance preference.

40. A method according to any of examples 35 to 39 comprising: obtaining workload data relating to future utilisations of the plurality of processing units; and setting the power limits for the plurality of processing units depending on the utilisation data and on the workload data.

41. A method according to example 40 wherein the obtained workload data comprises data indicative of one or more types of application to be run by the data processing platform.

42. A method according to any of examples 35 to 41 wherein the method further comprises: dynamically updating the power limits for the plurality of processing units by apportioning at least part of the system power limit between at least the plurality of processing units depending on subsequent utilisation data relating to subsequent utilisations of the plurality of processing units.

43. A method according to any of examples 35 to 42 wherein the method further comprises: obtaining subsequent system power limit data relating to a subsequent system power limit for the data processing platform; and dynamically updating the power limits for the plurality of processing units by apportioning at least part of the subsequent system power limit between at least the plurality of processing units depending on subsequent utilisation data relating to subsequent utilisations of the plurality of processing units.

44. A method according to any of examples 35 to 43 wherein the method comprises dynamically updating the power limits set for first and second processing units of the plurality of processing units in response to a change in the relative utilisations of the plurality of processing units, thereby changing a ratio of a power limit set for the first processing unit to the power limit set for the second processing unit.

45. A method according to any of examples 35 to 44 comprising dynamically updating the power limit set for a first processing unit of the plurality of processing units in response to a change in the relative utilisations of the plurality of processing units, thereby changing a ratio of the power limit set for the first processing unit to the system power limit. A method according to any of examples 35 to 45 comprising:

obtaining power usage strategy data relating to power usage strategies for the plurality of processing units; and

setting the power limits for the plurality of processing units depending on the utilisation data and on the power usage strategy data. A method according to example 46 comprising obtaining the power usage strategy data from the plurality of processing units. A method according to example 46 or example 47 comprising determining the power usage strategies for the plurality of processing units depending on any one or more of: system event data relating to power source availability; utilisations of one or more of the plurality of processing units; fuel gauge data relating to a maximum available battery power; historical power consumptions of one or more of the plurality of processing units; relative estimated costs of a plurality of candidate power usage strategies. A method according to example 48 comprising determining the estimated cost of each of the candidate power usage strategies depending on a power usage of the respective candidate power usage strategy and power source availability. A method according to any of examples 35 to 49 comprising: obtaining performance state prediction data relating to probable subsequent performance states of the plurality of processing units; and setting the power limits for the plurality of processing units depending on the obtained performance state prediction data. A method according to any of examples 35 to 50 comprising setting a power limit for a ring interconnect providing communication between the processing units by apportioning at least part of the system power limit between at least the processing units of the said plurality of processing units and the ring interconnect. A method according to example 51 comprising setting the power limit for the ring interconnect by apportioning at least part of the system power limit between at least the processing units of the said plurality of processing units and the ring interconnect depending on a usage parameter relating to usage of the ring interconnect and optionally depending on the utilisation data.

53. A method according to example 51 or example 52 comprising dynamically updating the power limit set for the ring interconnect by apportioning at least part of the system power limit between at least the processing units of the said plurality of processing units and the ring interconnect depending on a monitored usage parameter relating to a subsequent usage of the ring interconnect and optionally depending on subsequent utilisation data relating to subsequent utilisations of the processing units.

54. A method according to any of examples 35 to 53 comprising allocating a first portion of the system power limit to an integrated circuit device comprising the processing units and allocating a second portion of the system power limit to one or more components of the data processing platform which are not provided in the integrated circuit.

55. A method according to any of examples 35 to 54 wherein the data processing platform further comprises one or more components which are not provided in an integrated circuit comprising the processing units, the method comprising setting power limits for each of the one or more components by apportioning at least part of the system power limit between at least the processing units of the said plurality of processing units and the one or more components depending on respective monitored usage parameters relating to the usages of the one or more components and optionally depending on the utilisation data.

56. A method according to example 55 comprising dynamically updating the power limits set for the one or more components by apportioning at least part of the system power limit between at least the processing units of the said plurality of processing units and the one or more components depending on respective monitored usage parameters relating to subsequent usages of the one or more components and optionally depending on subsequent utilisation data relating to subsequent utilisations of the processing units. 57. Power control circuitry according to any of examples 1 to 28 wherein the processing circuitry is to determine and output the power limits set for each of the plurality of processing units to the respective processing unit. 58. Power control means for:

obtaining system power limit data relating to a system power limit for a data processing platform comprising a plurality of processing units;

obtaining utilisation data relating to utilisations of the plurality of processing units; and

setting power limits for the plurality of processing units by apportioning at least part of the system power limit between at least the plurality of processing units depending on the utilisation data.

59. Power control means according to example 58 wherein the power control means is for determining power usages of the plurality of processing units and setting the power limits of the plurality of processing units depending on the utilisation data and on the determined power usages of the plurality of processing units.