POWER ELECTRONICS MODULE AND METHOD FOR ITS MANUFACTURE

The present disclosure relates to a power electronics module comprising a substrate with at least a first metalli zation area and a first group of power electronic devices . The present disclosure further relates to a method for manufacturing such a power electronics module .

Power electronics modules comprising a plurality of power electronic devices are used in many di f ferent application areas . In particular, in the area of power electronics , a plurality of power semiconductor chips may be connected in parallel to form a power electronics module with a relatively high current rating .

With increasing demands for power density, it is desirable to increase the current rating of such power electronics modules . Increasing the power density can be achieved, for example , by the development and introduction of new chip technologies providing a reduction of conduction and switching losses of the individual semiconductor power devices during operation . However, the development of new chip technologies and their largescale manufacturing is very time consuming and costly, and therefore provides more of a long-term perspective . Accordingly, other means of increasing a current rating of a power electronics module are desirable .

Embodiments of the disclosure relate to power electronics modules and methods for their manufacturing enabling an increased current rating of a power electronics module with a given si ze or, a smaller si ze of a power electronics module with a given current rating . This disclosure shows an alternative method with low ef fort to enhance or optimi ze the current capability .

According to one aspect , a power electronics module comprises a substrate with at least a first metalli zation area, a first group of power electronic devices arranged in the first metalli zation area, and a common, uninterrupted j oining layer arranged between the first metalli zation area and the first group of power electronic devices . The first group comprising a plurality of power electronic devices , and the common, uninterrupted j oining layer establishes a mechanical and an electrical contact between the first metalli zation area and the first group of power electronic devices .

Among others , the inventors have found that , by omitting or reducing a distance between power electronic devices and j oining a plurality of power electronic devices using a common, uninterrupted j oining layer to a single metalli zation area, a total active area of the power electronic devices arranged on a power electronics module of a given si ze can be increased, thereby also increasing a current rating of the power electronic devices . While the space on a substrate available for positioning of power electronic devices , such as semiconductor chips , is limited, it can be better utili zed by j oining multiple power electronic devices using a common, uninterrupted j oining layer . This is in contrast to the j oining of each power electronic device separately using a separate j oining layer, where space is lost due to spaces between individual power electronic devices .

According to at least one implementation, each one of the power electronic devices of the first group is arranged directly adj acent to at least one other power electronic device of the first group . In other words , the power electronic devices of the first group are arranged essentially without any gap, or at least a strongly reduced gap, between them, thus maximi zing the use of available mounting space . By removing unused space between power electronic devices , the si ze of the power electronic devices , and consequently the active area can be increased . In particular, when power electronic devices , such as semiconductor chips , can be arranged very close to each other without signi ficant empty space between them, an optimal use of the available surface area of the substrate can be obtained .

According to at least one implementation, the power electronic devices may be sel f-aligned and/or the distance between adj acent power electronic devices of the first group is smaller than 1 mm, and in particular smaller than 0 . 5 mm . Such distances cannot be obtained using conventional mounting techniques , when power electronic devices are aligned and mounted using separate j oining layers .

A sel f-aligned may be achieved, for example , by exploiting physical properties of the common, uninterrupted j oining layer and/or a j oining material comprised therein, such as its surface tension and/or viscosity in a liquid state .

According to at least one implementation, the first metalli zation area comprises a subarea covering a part of the first metalli zation area and/or the substrate , and the common, uninterrupted j oining layer covers essentially the entire subarea . The area covered by the common, uninterrupted joining layer may exclude any space required for alignment of the group of power electronic devices. The subarea may represent a substantial part of the first metallization area or the substrate, such as the entire area available for placement of power electronic devices. For example, it may represent more than 25, 50 or 75 percent of the main surface area of the first metallization area or the substrate. The subarea may be a rectangular area or an area with any other geometry defined by the power electronic devices to be placed on the power module. For example, the subarea may be a largest rectangular part of the first metallization area. The subarea may exclude one or more smaller parts of the first metallization area configured for interconnecting the power electronic devices and/or for further components of the power electronics modules .

According to different implementations, the power electronic devices of the first group may be joined to the first metallization area using different joining techniques, including soldering, diffusion soldering, diffusion bonding, sintering or gluing.

According to at least one implementation, the power electronic devices are self-aligned by a meniscus formed at, least in parts of, the periphery of each power electronics device. In this case, all or part of adjacent menisci of adjacent power electronic devices may merge, leaving a recess in the common, uninterrupted joining layer in an internal gap between the power electronic devices, and providing a clear meniscus on an outer periphery of the first group of power electronic devices. Thus rather than relying on external alignment aids, such as compartmentalized solder preforms, the surface tension of a liquid or liquefiable j oining material may be used to determine a very narrow gap between neighboring power electronic devices .

In case the power electronic devices are soldered to the substrate , a solder layer may act as the common, uninterrupted j oining layer . Moreover, due to the physical properties of a soldering process , a distance between neighboring power electronic devices of the first group may be defined by a solder meniscus . This ef fectively enables a sel f-alignment of the power electronic devices .

A corresponding ef fect may also be achieved with a liquid or paste-like glue , which will form a meniscus in the form of a glue fillet at the periphery of the power electronic devices .

In case the power electronic devices are sintered to the substrate , the common, uninterrupted j oining layer may be implemented as a sinter layer of essentially uni form thickness .

In case the power electronic devices are glued to the substrate , the common, uninterrupted j oining layer may comprise an adhesive layer, in particular a double-sided adhesive tape or a continuous layer of scribed or printed glue .

According to at least one implementation, the power electronic devices of the first group comprise semiconductor chips , such as MOSFETs , MISFETs , JFETs , IGBTs , or diodes .

According to at least one implementation, each one of the semiconductor chips may comprise at least two terminals , and the terminals of each one of the semiconductor chips may be connected electrically in parallel. Combining multiple semiconductor chips in parallel enables a high current rating .

According to different implementations, the power electronic devices of the first group may be of the same type, or may be of two or more different types. For example, a combination of one or more protective or free-wheeling diodes and one or more transistor or switching devices may be arranged on the first metallization area to form a hybrid power electronics module .

According to another aspect, a method for manufacturing a power electronics module comprises: arranging a layer of joining material, in particular a single preform, between a first metallization area of a substrate and respective contact surfaces of a first group of power electronic devices, wherein the first group comprises a plurality of power electronic devices; and forming a common, uninterrupted joining layer from the joining material, wherein the common, uninterrupted joining layer establishes at least a mechanical and an electrical contact between the first metallization area and the first group of power electronic devices.

The above method step enable result in a power electronics module with a high current density as detailed above.

Depending on the used joining technique, e.g. soldering, diffusion soldering, diffusion bonding, sintering or gluing, di f ferent processing steps may be performed to process and j oin the plurality of power electronic devices of the first group together, thereby lowering manufacturing cost and improving yield .

The present disclosure comprises several aspects of a power electronics module and methods for its manufacturing . Every feature described with respect to one of the aspects is also disclosed herein with respect to the other aspects , even i f the respective feature is not explicitly mentioned in the context of the speci fic aspect .

The accompanying figures are included to provide a further understanding . In the figures , elements of the same structure and/or functionality may be referenced by the same reference signs . It is to be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale .

Figure 1 shows a schematic cross-section through a power electronics module with a common, uninterrupted j oining layer .

Figure 2 shows a top view of a power electronics module comprising five power electronic devices with a common, uninterrupted j oining layer .

Figures 3 and 4 show di f ferent views of a solder fixture used for manufacturing a power electronics module .

Figures 5 to 9 show a method for manufacturing a power electronics module by soldering . Figures 10 and 11 show a method for manufacturing a conventional power electronics module by soldering .

Figures 12 to 15 show a method for manufacturing a power electronics module by sintering .

While the disclosure is amenable to various modi fications and alternative forms , speci fics thereof are shown by way of example in the figures and will be described in detail below . It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments described . On the contrary, the intention is to cover all modi fications , equivalents , and alternatives falling within the scope of the invention as defined by the appended set of claims .

Figure 1 shows , in a schematic manner, a cross-section through a power electronics module 10 . The power electronics module 10 comprises a substrate 11 with a first metalli zation area 12 on one of its main surfaces . For example , the substrate 11 may be a ceramic substrate with a metalli zation layer formed on one side . A common, uninterrupted j oining layer 13 is formed on a surface of the first metalli zation area opposite the substrate 11 . As detailed later, the j oining layer 13 may be a solder layer, a sinter layer, an adhesive layer, or a layer prepared by di f fusion soldering or di f fusion bonding . On top of the j oining layer 13 , a group comprising two power electronic devices 14 is arranged . The group of power electronic devices 14 may comprise at least one semiconductor power diode and/or at least one semiconductor power transistors . The j oining layer 13 is uninterrupted in the sense that it does not comprise any intentional gaps and/or provides a direct electrical path between the power electronic devices 14 of the same group, irrespective of an electrical path provided by the first metallization area 12.

Attention is drawn to the fact that a remaining gap G between the two power electronic devices 14 is very small. That is to say, the power electronic devices 14 are arranged more or less directly adjacent to one another in the first metallization area 12. In terms of absolute distance, this may mean that the remaining gap G between the two power electronic devices 14 is smaller than 1 mm, for example 0.5 mm or less. In terms of relative distance, this may mean that the remaining gap G between the two power electronic devices 14 is smaller than 10% or 5% of the width and/or length of the adjacent power electronic devices 14. Depending on the specific mounting technique used, the adjacent power electronic devices 14 may not be aligned perfectly in parallel. In that case, the terms "gap" and "distance" may refer to the average distance gap or between two adjacent power electronic devices 14.

Such distances between adjacent power electronic devices 14 cannot be achieved using conventional manufacturing methods, wherein each power electronic device 14 is joined to a metallization area using a separate joining layer 13 as detailed later. Inversely, this means that the joining layer 13 is substantially continuous, and preferably has no gap in an area located between two adjacent power electronic devices 14. Put differently, the joining layer 13 is formed from a common body of joining material. For example, a single piece of material, such as a single solder preform, a single sintering preform, or a single adhesive tape, may be used. Alternatively, a paste-like joining material, such as solder paste, sinter material, or liquid adhesive, may be applied by dispensing or printing it in a continuous or patterned shape, such as a cross, snowflake, or multiple dots. A continuous joining layer 13 is formed by putting the power electronic devices 14 on the previously dispensed joining material.

Figure 2 shows a top view of a power electronics module 10 with a total of five power electronic devices 14a to 14e, for three IGBTs (or other type of transistors) and two diodes. A first part 15, in Figure 2 the lower part, covers a substantial part of the substrate 11, e.g. more than 50 percent of the total surface of the substrate 11, and comprises an essentially rectangular subarea 16, indicated using a dashed line, of a first metallization area 12.

In the depicted embodiment, the subarea 16 represents the largest rectangular subarea of the first metallization area 12. A large proportion of the subarea 16, e.g. more than 95 percent, is covered by the five power electronic devices 14a to 14e. Only a remaining outer area of the subarea 16 near the outer edges of the five power electronic devices 14a to 14e is left uncovered. A smaller, second part 17 of the substrate 11, in Figure 2 the upper part, may comprise further parts of the first metallization area and further metallization areas. For example, metal traces used for connecting contact surfaces on the back side of the power electronic devices 14a to 14e and/or for connecting the power electronics modules 10 to other components or for joining of other electronic devices like sensor devices, passive device, control devices may be provided. The proportion of the subarea 16 can be at least 80 to 85 percent in some other variants of the power electronics module, e.g. when the shape of the subarea is other than the rectangular geometrical shape or when the current rating requirement is lower .

In other embodiments , further metalli zation areas and/or subareas may be provided . For example , in a hal f-bridge used for an inverter module , two di f ferent metalli zation areas may be provided for placement of one or more high-side group and one or more low-side group of power electronic devices , respectively (not shown) . For multi-phase inverters , further metalli zation areas and corresponding groups of power electronic devices may be provided . In such configurations , one or more respective subareas for placement of power electronic devices may only cover a smaller part of the substrate ' s surface , but may still represent the largest continuous geometrical shape , such as a rectangle , of the respective metalli zation .

In the embodiment shown in Figure 2 , the individual power electronic devices 14a to 14e touch each other or are separated only by a very narrow gap caused by the respective j oining technique , as detailed below . In the embodiment shown in Figure 2 , the width of remaining gap G between the individual power electronic devices 14 is smaller than a width of a remaining outer edge E between the outside circumference of the first group of power electronic devices 14 and the respective outer circumference of the subarea 16 .

Figures 3 to 9 show how such a power electronics module may be formed by soldering . At first , a modi fied solder fixture 18 is explained with reference to Figures 3 and 4 , before individual phases of a related manufacturing process are explained with reference to Figures 5 to 9 . Figures 3 and 4 show a perspective and a plane view of a first part 18a of the solder fixture 18 , respectively . As can be best seen in Figure 3 , the first part 18a of the solder fixture 18 comprises a number of depressions for holding the components of power electronics module 10 . In particular, a larger, relatively shallow first recess 19 corresponds to the outer circumference of the substrate 11 and/or the metalli zation areas formed thereon, and serves to hold the substrate 11 during soldering .

A smaller, slightly deeper, second recess 20 is formed within the first recess 19 , and is configured to hold a plurality of power electronic devices 14 . In the described example , the second recess 20 is configured to hold the five power electronic devices 14a to 14e previously shown in Figure 2 and a common solder preform, as explained later . While only a single second recess 20 configured for holding a single group of power electronic devices 14 is shown in Figures 3 and 4 , fixtures 18 comprising several second recesses 20 for multiple groups arranged on the same or di f ferent metalli zation areas 12 are also envisioned .

The first part 18a of the solder fixture 18 comprises a number of further depressions , openings and other structural features that facilitate insertion and removal of the various components into and out of the solder fixture 18 , and for accommodating weights for pushing down any power electronic devices 14 placed therein . For the sake of brevity, these are not described in detail here .

In the top view of Figure 4 , a rectangular area 21 formed by the second recess 20 is highlighted using a dashed line .

Attention is drawn to the fact that the edges of the second recess 20 corresponding to the rectangular area 21 serve to align all of the power electronic devices 14 and the common solder preform together . In contrast , no internal dividing or alignment features are provided between the positions of the individual power electronic devices 14a to 14e . Avoidance of such internal protrusions increases the space available for placement of the power electronic devices 14 . Further attention is drawn to the fact that the rectangular area 21 formed within the second recess 20 essentially corresponds to or is only smaller by a relatively small fraction, e . g . a distance corresponding to a solder meniscus and/or needed for alignment , than the subarea 16 of the first metalli zation area 12 .

Figure 5 shows , in a schematic manner, a first stage in the manufacturing of a power electronics module 10 . At this stage , multiple power electronic devices 14 have been placed in a common recess 20 , from which only two are visible in the cross-section of Figures 5 to 9 . Below each one of the power electronic devices 14 , a corresponding weight 22 is arranged, which may be a loose part or may be attached to the first part 18a of the solder fixture 18 in a movable manner .

In the described embodiment , above the two power electronic devices 14 , a single , continuous solder preform 23 is placed . Due to its larger si ze and the fact that only a single solder preform 23 needs to be placed in the solder fixture 18 , handling of the preform 23 and thus the entire manufacturing process may be simpli fied . The solder preform 23 covers corresponding contact surfaces of the two power electronic devices 14 and essentially extends over the entire widths of the second recess 20 . Accordingly, the same solder preform may be used, irrespective of the individual si ze of the used power electronic devices 14. For example, the same solder preform 23 may be used to attach two full-size or four halfsize chips to the same metallization area 12. Attention is drawn once again to the fact that no separating protrusion is present between the two power electronic devices 14.

Figure 6 shows a further stage in the manufacturing process. At this stage, a double-sided substrate 11 comprising a first metallization area 12 on the first side and a second metallization area 24 arranged on the opposite, second side of the substrate 11 is placed in the first part 18a of the solder fixture 18. For example, in a power module, the first side may correspond to a backside, and the second side may correspond to a front side of the substrate 11. In the depicted embodiment, the first metallization area 12 is placed in the first recess 19 surrounding the second recess 20 such that a subarea of the first metallization area 12, for example the subarea 16 shown in Figure 2, is aligned with the power electronic devices 14.

At a next stage, shown in Figure 7, a second part 18b of the solder fixture 18 (fixture bottom plate) is placed on top of the substrate 11, i.e. the second metallization area 24, to close the solder fixture 18.

Thereafter, as shown in Figure 8, the closed solder fixture 18 comprising the first part 18a and the second part 18b is flipping, such that the weights 22 press the respective power electronic devices 14 against the first metallization area 12. At this stage, the solder preform 23 is heated or otherwise liquefied, resulting in a layer of liquid solder material 25. Optionally, a process gas or liquid, such as hydrogen, or formic acid may be applied during soldering, to support or enable a chemical reduction of the solder material . For example , hydrogen or formic acid may be used for reduction of the solder material of the solder preform 23 . Alternatively, or additionally, an inert gas like nitrogen may be applied during at least phases of the j oining process .

Once the soldering process is complete , the solidi fied solder material 25 forms a common, uninterrupted solder layer 26 as shown in Figure 9 . The thickness of the solder layer 26 may vary to a small extend in areas below the power electronic devices 14 and neighbouring areas , e . g . by a limited overflow of the soldering material into the gap G or towards the edge E . Nonetheless , such a solder layer 26 may be described as homogenous , as it is formed in a single rather than several successive soldering steps .

Thereafter, the solder fixture 18 can be removed, with the individual power electronic devices 14 being mechanically and electrically attached to the first metalli zation area 12 . Moreover, the solder layer 26 may also serve as a thermal connection between the power electronic devices 14 and the substrate 11 , e . g . for cooling of the power electronic devices 14 . Due to the uninterrupted nature of the common j oining layer 13 and/or the larger total surface area of the power electronic devices 14 , the thermal capabilities of the resulting power electronics module 10 may also be improved, for example , by achieving a more uni form heat distribution .

As can be seen in Figure 9 , due to the surface tension of the liquid solder material , the individual power electronic devices 14 are essentially sel f-aligned by a solder meniscus 27 formed at the periphery of power electronic devices 14 , e . g . by merging with the meniscus of an adj acent power electronic device 14 , indicated by a recess 36 in the solder layer 26 in a remaining, internal gap between the power electronic devices 14 , and a clear meniscus 27 on the outer periphery of the group of power electronic devices 14 . In this way, the physical properties of the solder material itsel f provides an alignment aid, further alleviating the need for internal protrusions within the second depression 20 of the solder fixture 18 .

While a conventional soldering process has been described, more advanced soldering techniques , such as di f fusion soldering may also be used accordingly . In this case , rather than weights 22 , a controlled pressure may be applied to the power electronic devices 14 , e . g . by corresponding fixtures .

Moreover, in another embodiment , instead of placing a solder preform 23 in the common recess 20 , solder paste is coated on a surface of the first metalli zation area 12 . For example , a subarea intended for the placement of power electronic devices 14 may be covered with a patterned layer of a viscous solder paste by printing or coating or dispensing . The power electronic devices 14 of the first group are then mounted, for example , using a pick-and-place process and a subsequent thermal process , such as reflow soldering or another bonding technique , resulting in a common, uninterrupted solder layer 26 as described above . In this case , use of a fixture for holding the power electronic devices 14 is optional , as the power electronic devices 14 may be held in place before and during soldering by the solder paste . Finally, in case more than one group of power electronic devices 14 shall be mounted, each group can be mounted separately, as described below with respect to sintering .

Figures 10 and 11 show an intermediate stage and resulting power electronics module 28 formed by an alternative , more conventional method of attaching two power electronic devices 14 to a substrate 11 with a first metalli zation area 12 .

As shown in Figure 10 , each one of the power electronic devices 14 is individually aligned on all sides before and during soldering . To this end, a protrusion 29 is present in a first part 18a of a solder fixture 18 , separating the power electronic devices 14 and individual solder preforms from each other . Accordingly, two separate solder preforms 23a and 23b must be placed in each one of two corresponding recesses 20a and 20b . During the soldering process , the power electronic devices 14 as well as the solder materials remain separated by the protrusion 29 .

Accordingly, as is shown in Figure 11 , two separate solder layers 26a and 26b are formed, which are separated from one another ( except for unintentional solder overflows ) by a corresponding gap G, which typically exceeds 1 mm in width . The surface area of the substrate 11 and corresponding part of the first metalli zation area 12 according to the gap G is lost for the placement of active components , so the chip si zes and consequently the active areas of the chips must be smaller . This leads to a lower current rating of the power electronics module 28 compared to the power electronics module 10 of Figure 9 . That is to say, when using a common, uninterrupted j oining layer 13 , larger and/or more numerous chips forming the power electronic devices 14 may be placed in common metalli zation area 12 of a given si ze . This results in a larger total active area of the chips , which in turn results in a higher current capability or power density . Inversely, i f the number and si ze of the individual power electronic devices 14 is fixed, a smaller substrate 11 with a smaller metalli zation area 12 may be used to obtain the same current capability . This may result in a miniaturi zation and reduction of cost .

Figures 12 to 15 show, in a schematic manner, di f ferent stages of a manufacturing method for a power electronics module 10 based on sintering .

At a first stage , shown in Figure 12 , a layer of sinter material is provided on a first metalli zation area 12 of a double-sided substrate 11 . As an example , sintering preform 30 may be placed on the first metalli zation area 12 . Alternatively, a layer of sinter material may be applied, for example by printing, in a corresponding area of the first metalli zation area 12 .

At a next stage , shown in Figure 13 , multiple power electronic devices 14 , forming a group of power electronic devices to be sintered, are placed on the sintering preform 30 . For example , a pick and place procedure may be used to place individual power semiconductor chips on the sinter preform 30 .

The substrate 11 with the aligned power electronic device 14 may be placed in a sinter press . In an optional step, a protective foil 31 may be placed on top of the power electronic devices 14 to provide mechanical protection and/or protection against contaminations during sintering, e . g . to protect corresponding electrodes or other parts of the upper side of the power electronic devices 14 . For example , a first part 32a of a sintering fixture 32 may be placed over the protective foil 31 , the power electronic devices 14 , the sintering preform 30 and the double-sided substrate 11 as shown in Figure 13 . As shown in Figure 13 , the first part 32a of a sintering fixture 32 comprises a recess 33 for laterally holding and/or aligning the power electronic device 14 before and during sintering . On the opposite side of the doublesided substrate 11 , i . e . below the second metalli zation area 24 , a second part 32b of the sintering press or sintering fixture 32 is arranged .

While the term " sintering fixture" is used here and a profiled sintering fixture 32 is shown for better understanding, attention is drawn to the fact that , in its simplest form, sintering may be performed between two arbitrary, flat surfaces . That is to say, the recess 33 represents an optional feature for the sintering process .

As shown in Figure 14 , the two opposite surfaces used for sintering are closed and pressed against each other to sinter the material of the sinter preform 30 into an essentially uni form sinter layer 34 between the power electronic devices 14 and the first metalli zation area 12 .

While sintering based on mechanical pressing has been described above , other known sintering processes based on heat and/or a processing atmospheric may also be used or combined with a mechanical sintering process . For example , sintering may be performed in an atmosphere consisting of an inert gas to avoid unwanted chemical reactions.

As detailed above, the sintering layer 34 provides both a mechanical and electrical connection between the adjoining parts, and may also provide a thermal connection.

Once the sintering is complete, as shown in Figure 15, the sintering fixture 32 may be removed and further processing steps may take place. For example, as also shown in Figure 15, one or more bond wires 35 may be connected to electrical contacts arranged on the opposite, upper surface of the individual power electronic devices 14, for example between different power electronic devices 14 as shown in Figure 15, or between a power electronic device 14 and a metallization area (not shown) . In this way, for example, a relatively large number of power electronic devices 14 may be connected electrically in parallel.

In the scenario shown in Figures 1 to 9 and Figures 12 to 15, a single, continuous and homogenous preform is used as solder or sinter material layer, respectively, which covers a large part of the outer surface of the first metallization area 12. However, in other embodiments (not shown) , different groups of power electronic devices 14 may be soldered or sintered to a common metallization area 12 in successive stages. In this case, a single preform or area covered with joining material, such as a solder paste or sinter material, may only cover a part of the first metallization area 12, which corresponds to a respective first group of power electronic devices 14.

Moreover, especially in the case of sintering, depending on the joining materials and joining processes, a stack of multiple preforms and/or multiple layers of j oining materials may be used .

Moreover, although not shown in the drawings , the above solder or sintering processed may be repeated for the second main surface of the substrate , thereby forming power electronics modules 10 carrying power electronic devices 14 on the two opposite metalli zation areas 12 and 24 .

The embodiments shown in Figures 1 to 9 and 12 to 15 as stated represent exemplary embodiments of improved power electronics modules 10 and methods for their manufacturing . Therefore , they do not constitute a complete list of all embodiments according to the improved devices and methods . Actual devices and methods may vary from the embodiments shown in terms of arrangements , devices and processing steps , for example .

For example , while not shown in the attached figures , a common, uninterrupted j oining layer 13 may also be formed using an adhesive layer . For example , a preferably electrically conductive , double-sided adhesive tape may be placed on an upper surface of a first metalli zation area 12 of a substrate 11 . Thereafter, individual power electronic devices 14 forming a group of power electronic devices can be placed on the opposite second adhesive surface of the doublesided adhesive tape , e . g . by a pick and place process .

Alternatively, a preferably electrically conductive , typically patterned layer of liquid or viscous glue , such as a silver glue , may be dispensed, for example in a patterned layer, by scribing, dispensing, printing or coating the liquid or viscous glue on the surface of the first metallization area 12, or on corresponding contact surfaces of a plurality of power electronic devices 14 held, for example, in a common fixture similar to the first part 18a of the solder fixture 18 shown in Figures 3 and 4, or placed one-by-one on the first metallization area 12, for example using a pick and place process. Thereafter, the first metallization area 12 may be aligned with the group of power electronic devices 14. As a result, the liquid or viscous glue forms a homogenous layer. After placement of the power electronic devices 14 the glue may be cured using an appropriate process, such as heating or evaporating of a solvent, resulting an essentially homogenous, uninterrupted joining layer 13.

In this case, a self-alignment of the power electronic devices 14 similar to the one described above with respect to soldering may be achieved.

For example, a liquid glue may be printed, either on the first metallization area 12 or a corresponding contact surface of the power electronic devices 14 of the first group. Then, the power electronic devices 14 are placed, on next to another, on the first metallization area 12.

For glues with a relatively low viscosity, its surface tension may be sufficient to form a glue layer of uniform thickness and finally, after placing of the power electronic devices 14, of a meniscus in the form of spew fillet. For higher viscosities, such as paste-like glues, an external pressure may be applied to the power electronic devices 14, to squeeze out glue placed between each power electronic device 14 and a corresponding part of the first metallization area 12, thus forming a spew fillet. For example, a paste- like glue may be printed or scribed in form of a cross or a snow flake at or near the center of each power electronic device 14 to be attached to the substrate 11 o a corresponding mounting position of the first metalli zation area 12 . The snow flake glue pattern is then flattened, for example , by using weights or springs integrated into a common manufacturing form similar in shape to the first part 18a of the solder fixture 18 described above or by pressing all power electronic devices 14 towards the first metalli zation area 12 , either individually by using a placement tool or together, i . e . after all power electronic devices 14 of the first group have been placed, by using a stamp-like tool with a flat pressing surface guided in parallel to the surface of first metalli zation area 12 , as detailed above with respect to sintering .

In either case , a continuous glue layer of uni form thickness is formed between the first metalli zation area 12 and the corresponding contact surface of the power electronic devices 14 . Moreover, the power electronic devices 14 are sel faligned by the surface tension and viscosity of the liquid glue forming, leading to the formation of menisci in the form of spew fillets at the periphery of the power electronic devices 14 .

Reference Signs

10 power electronics module

11 substrate

12 first metalli zation area

13 j oining layer

14 power electronic device

15 first part ( of substrate )

16 subarea

17 second part ( of substrate )

18 solder fixture

18a first part of solder fixture

18b second part of solder fixture

19 first recess

20 second recess

21 rectangular area

22 weight

23 solder preform

24 second metalli zation area

25 solder material

26 solder layer

27 solder meniscus

28 power electronics module

29 protrusion

30 sintering preform

31 protective foil

32 sintering fixture

33 recess

34 sinter layer

35 bond wire

36 recess

G gap

E edge