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Title:
POWER LIMITING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2010/074187
Kind Code:
A1
Abstract:
Disclosed is a power limiting circuit equipped with: a maximum value prediction filter unit (11) that interpolates the data of one of the branches of a digital input signal; a maximum value detection unit (12) that detects, at fixed intervals, a maximum value and a time detection position based on the output from the maximum value prediction filter unit; a threshold value subtraction unit (13) that subtracts a threshold value from the detected maximum value, outputting a peak signal with a level of 0 (zero) when the resulting value is negative; a coefficient selection unit (14) that weights the peak signal in response to the time detection position; a complex filter unit (15) that restricts the weighted peak signal to the band frequency of the input signal; a filter coefficient calculation unit (16) that calculates the filter coefficient of the complex filter unit; a delay adjustment unit (17) that delays the other branched input signal by exactly the amount of time necessary for calculation of the band frequency-restricted peak signal; and a subtraction unit (18) that subtracts the band frequency-restricted peak signal from the other branched input signal that has been delayed.

Inventors:
SATO HIROTAKA (JP)
KONO KIMIHIKO (JP)
DOI YOSHIAKI (JP)
KUSHIOKA YOICHI (JP)
Application Number:
PCT/JP2009/071512
Publication Date:
July 01, 2010
Filing Date:
December 17, 2009
Export Citation:
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Assignee:
NEC CORP (JP)
NEC ENGINEERING LTD (JP)
HITACHI INT ELECTRIC INC (JP)
SATO HIROTAKA (JP)
KONO KIMIHIKO (JP)
DOI YOSHIAKI (JP)
KUSHIOKA YOICHI (JP)
International Classes:
H04J11/00; H03F1/32; H04B1/04
Domestic Patent References:
WO2006049140A12006-05-11
Foreign References:
JP2004104162A2004-04-02
JP2001086094A2001-03-30
Attorney, Agent or Firm:
IKEDA, Noriyasu et al. (JP)
Noriyasu Ikeda (JP)
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