OPERATION

STATEMENT OF CORRESPONDING APPLICATIONS This application is based on the provisional specification filed in relation to New Zealand Patent Application No. 723311, and the provisional specification filed in relation to New Zealand Patent Application No. 723314, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD The present disclosure relates to power line carrier systems, and more particularly transceiver circuits communicatively coupled to a power distribution network for use in a distributed automation system, and modules and control protocols for such systems.

BACKGROUND ART Automation systems are becoming increasingly common in commercial buildings and domestic dwellings for the control and automation of lighting, heating, ventilation, air conditioning (HVAC), appliances, security, and energy management. This is especially the case for locations that have energy generation and/or storage capabilities.

Historically, power was provided from the National Grid with surplus generation (e.g. from solar panels) fed back into the National Grid. However, with the widening gap between the cost of imported and exported power the economics of feeding power back in to the National Grid has deteriorated. To mitigate this problem there is a movement towards distributive energy storage; whereby surplus power is stored at the dwelling, to be used later. Much like the National Grid communicates with consumers to implement demand response, a distributive energy storage system needs to be managed - i.e. within the dwelling, generation and storage capabilities need to be matched to the demand.

A power line carrier (PLC) network is produced by implementing a communication protocol that uses electrical wiring within a power distribution system to simultaneously carry both data and electrical power. Such a network allows an automation system to communicate to individual loads, generators and energy storage devices in order to balance the power demands.

A barrier to reliable communication across a power distribution system is electrical noise. The electrical noise can interfere with the carrier frequency of the PLC message, causing it to be interfered with in such a way that it cannot be decoded. Faultier communication can introduce errors, with a particular consequence of loads turning off and on unintentionally. Household appliances and devices are common sources of electrical noise, in particular the switched mode power supplies frequently used to power such devices. For reliability of an automation system using PLC messages it is highly important that it is able to operate within such an electrically noisy environment.

Further, known PLC systems are both expensive and complex - characteristics which are ill-suited to many components within an automation system of a commercial building or residential dwelling. These components are either a commodity or compete with low-tech solutions - for example, to be integrated into a light switch to provide remote communication to other devices on the power distribution system. The expense of existing systems limits their use to products that are able to support a higher price to the user.

Also, automation systems were historically based upon a central processor (for example a personal computer or a programmable logic controller) that read event-signals from input modules and send control-signals to output modules. This type of architecture is vulnerable to a failure of the central processor, and growing complexity as modules are added. For example, if the power supply to the central processor were to fail, then the whole network would be disabled.

Further, such automation systems have significant commissioning requirements, ongoing technical support and high component costs. Consequently they are expensive, creating a barrier to the widespread uptake of automation - particularly in residential dwellings, which is a cost sensitive market.

It is an object of the present invention to address at least one of the foregoing problems, or at least to provide the public with a useful choice.

All references, including any patents or patent applications cited in this specification are hereby incorporated by reference. No admission is made that any reference constitutes prior art. The discussion of the references states what their authors assert, and the applicants reserve the right to challenge the accuracy and pertinency of the cited documents. It will be clearly understood that, although a number of prior art publications are referred to herein, this reference does not constitute an admission that any of these documents form part of the common general knowledge in the art, in New Zealand or in any other country.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like, are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense, that is to say, in the sense of "including, but not limited to".

Further aspects and advantages of the present invention will become apparent from the ensuing description which is given by way of example only.

SUMMARY According to a first aspect of the present disclosure, disclosed embodiments are directed to systems and methods for communicating data in a power line carrier system including a power distribution network and two or more devices having transceiver circuits communicatively coupled to the power distribution network.

According to an exemplary embodiment of the present disclosure there is provided a method for transmitting a data packet onto a power distribution network.

In an exemplary embodiment, error correction encoding may be performed on the data packet to be transmitted. In an exemplary embodiment, forward error correction (FEC) may be performed, encoding the data using an error-correcting code (ECC) prior to transmission. In an exemplary embodiment, bit-shuffling may be performed to reduce the risk of clusters of bits within the data packet being corrupted, such as in the event of burst noise. It should be appreciated that other error correction encoding may be performed, and that the exemplary embodiments disclosed are not intended to be limiting.

In an exemplary embodiment, the method may include modulating the data packet prior to transmission onto the power distribution network. In an exemplary embodiment the modulation scheme is frequency-shift keying (FSK). In an exemplary embodiment the modulation scheme may be binary frequency-shift keying (BFSK). It should be appreciated that other modulation schemes may be implemented, and that the exemplary embodiments disclosed are not intended to be limiting.

In exemplary embodiments in which a FSK modulation scheme is implemented, the signal carrying the data packet may be filtered before transmission onto the power distribution network. In an exemplary embodiment the signal may be filtered before and after coupling with the power distribution network. In an exemplary embodiment the signal may be filtered using at least one bandpass filter to attenuate frequencies outside those used in the modulation scheme.

In exemplary embodiments the signal carrying the data packet may be transmitted within a Comite Europeen de Normalisation Electrotechnique (CENELEC) compliant band. It should be appreciated that this is not intended to be limiting to all exemplary embodiments, and that any other suitable carrier frequency may be used.

In an exemplary embodiment the data packet may be transmitted asynchronously. This is envisaged as improving suitability for use in both alternating current and direct current power distribution networks, as the transmission is not synchronised to the mains nor dependent upon zero-crossings.

In an exemplary embodiment, the method may include applying an anti-collision-algorithm to time- sequence the transmission of data packets on the power distribution network. Such an algorithm allocates data packets to a plurality of time-slots. In an exemplary embodiment the time-slot allocation may be based on a random assignment. In an exemplary embodiment the time-slot allocation may include priority scheduling - i.e. data packets are divided into groups with different priorities, and data packets with higher priority are statistically transmitted sooner than those of a lower priority. In an exemplary embodiment the time-slots may be synchronised to the end of detection of a data-packet on the power distribution network, at which point the scheduled data- packets are transmitted. According to an exemplary embodiment of the present disclosure there is provided a method for receiving a data packet over a power distribution network. In an exemplary embodiment the method for receiving the data packet may reverse the transmission process, for example filtering the signal with a bandpass filter, demodulating the signal, and decoding the error correction before the data packet is read. In an exemplary embodiment the method for receiving the data packet may include frequency shifting the received data packet before demodulation. In doing so the attenuation of the signals outside the bandpass filter frequencies is increased to provide greater signal selectivity. In exemplary embodiments signal conditioning may be performed after the frequency shifting.

According to an exemplary embodiment of the present disclosure there is provided a power line carrier (PLC) transceiver circuit for transmitting and receiving data packets on a power distribution network. It is envisaged that exemplary embodiments of the transceiver circuit may be produced using generic components in order to avoid single-source inventory. Electronic components supplied by the electronics industry are subject to change with or without notice, and have a design lifetime. The use of generic components is envisaged as mitigating risk associated with single-sourcing both in terms of support and cost (which gives a symbiotic relationship with a low-cost objective).

In an exemplary embodiment the transceiver circuit may include a signal generator. For example, the transceiver circuit may include a microcontroller driving one or more switches to output a binary sequence comprising the bits of the data packet. The signal generator may be configured to output the signal in accordance with the modulation scheme and anti-collision algorithm. In exemplary embodiments the signal generator may also be used to receive and process data packets.

In an exemplary embodiment the transceiver circuit may include at least one filter circuit. In an exemplary embodiment the filter circuit may include at least one bandpass filter. The at least one bandpass filter may be configured to attenuate the harmonics in the signal prior to and/or after the coupling to the power distribution network.

In an exemplary embodiment the transceiver circuit may include an intermediate frequency (IF) circuit to provide greater signal selectivity. The IF circuit may include a mixing circuit and an IF filter. It is envisaged that the IF circuit may be AC coupled to the transceiver circuitry used for transmission of data packets. In an exemplary embodiment the transceiver circuit may include a signal conditioning circuit following the intermediate frequency (IF) circuit.

According to a further aspect of the present disclosure, disclosed embodiments are directed to systems and methods for communicating data across a network. It is envisaged that exemplary embodiments may have particular application to discrete modules communicating across a power distribution network using a power line carrier system, but it should be appreciated that the disclosure may be applied to other forms of network.

According to an exemplary embodiment of the present disclosure there is provided a module for use in a distributed automation system, the module including at least one processor and a local database. The module may include a transceiver for the transmission and receiving of messages on a network of the distributed automation system. In exemplary embodiments the transceiver may be the power line carrier (PLC) transceiver circuit as described herein - however it should be appreciated that this is not intended to be limiting to every embodiment of the module.

The module may be configured to generate an event message in response to an input to the module. The stimulus for such inputs may come from a wide range of manual or automatic events, including user initiated events (for example selection of a button or switch, or voice activation), or automated events such as a sensed event (for example motion triggering, proximity sensing, or threshold sensing) or timed event.

Each module within the system may be configured to receive the event message and determine whether an action is required in response. Such actions may include, for example, driving an output of the module, and generating an event message in response. It should be appreciated that transmission network includes the originating module, thereby enabling a module to action an event message that it created and operate as a stand-alone system. The outputs of the modules may be used to control operation of subsystems within a building or complex, for example: lighting systems, or heating ventilation and air conditioning (HVAC) systems.

A module for use in a distributed automation system, the module including: at least one processor, a local database, and a transceiver for the transmission and receiving of event messages on a network of the distributed automation system, wherein the processor is configured to: generate an event message in response to an input to the module with reference to the local database, cause the event message to be transmitted on the network, receive the event message, and determine with reference to the local database whether an action is required in response to receiving the event message.

In an exemplary embodiment the event message includes an address word. The address word may be read by a module and compared against the module's local database to determine whether the event message is to be actioned by that module. In an exemplary embodiment each module may be configured to have a plurality of inputs, with the local database of the module configured to identify an address word from a plurality of address words for inclusion in the event message based on the input received.

In an exemplary embodiment, the local database may associate at least one address word with an output of the module. On receiving an event message having an address word with which an output is associated, the module may drive that output in accordance with settings within the local database specific to that output.

In an exemplary embodiment the local database may associate a plurality of address words with a single output, allowing that output to be controlled by a plurality of inputs - whether those inputs are to the same module, or different modules.

In an exemplary embodiment each module may be configured to have a plurality of outputs. In an exemplary embodiment, the local database may associate the same address word with more than one output. It is envisaged that this may have particular application to the control of scenes - i.e. a particular arrangement of outputs performed simultaneously. In an exemplary embodiment the event message may include a control byte defining the action to be performed by at least one module matching the address word - for example, turning an output ON or OFF. In an exemplary embodiment the control byte may also define a number of data-bytes to be attached to the event message for use in defining the action. The action following receipt of the event message may include open-loop control of the output - i.e. control of the output without monitoring the output to determine whether a set goal for the action has been achieved. However, exemplary embodiments of the module may implement closed-loop control (including cascaded control loops), monitoring an input and generating event messages in response to that input to modify the output to achieve a setting within the local database. The event message may include other components known in the art, for example a header and a checksum. The event message may be transmitted over the network using any suitable transmission scheme known in the art. For example, in a power line carrier case it is envisaged that the event message may be frequency shift key (FSK) modulated, transmitted within a random time-slot once the transmission network is free, and repeated for improved communication reliability. In exemplary embodiments the event message may be transmitted and received in accordance with the method described herein.

According to an exemplary embodiment of the present disclosure there is provided a non-transitory computer-readable medium having instructions stored thereon that, upon execution by one or more processors, causes functions to be carried out, wherein the functions include the exemplary method steps substantially as herein described.

For a firmware and/or software (also known as a computer program) implementation, the techniques of the present disclosure may be implemented as instructions (for example, procedures, functions, and so on) that perform the functions described. It should be appreciated that the present disclosure is not described with reference to any particular programming languages, and that a variety of programming languages could be used to implement the present invention. The firmware and/or software codes may be stored in a memory, or embodied in any other processor readable medium, and executed by a processor or processors. The memory may be implemented within the processor or external to the processor.

A processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, state machine, or cloud computing device known in the art. A processor may also be implemented as a combination of computing devices, for example, a combination of a digital signal processor (DSP) and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

The steps of a method, process, or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by one or more processors, or in a combination of the two. The various steps or acts in a method or process may be performed in the order shown, or may be performed in another order. Additionally, one or more process or method steps may be omitted or one or more process or method steps may be added to the methods and processes. An additional step, block, or action may be added in the beginning, end, or intervening existing elements of the methods and processes.

BRIEF DESCRIPTION OF DRAWINGS

Further aspects of the present invention will become apparent from the following description which is given by way of example only and with reference to the accompanying drawings in which:

FIG. 1A is a top level block diagram of an exemplary power line carrier system;

FIG. IB is a lower level block diagram of an exemplary embodiment of the power line carrier system;

FIG. 2A is a flow chart illustrating an exemplary embodiment of operation of transmission components of the power line carrier system;

FIG. 2B is a schematic diagram of an exemplary transmitter circuit of a transceiver for use in the power line carrier system;

FIG. 2C is a graph of a digital waveform and the corresponding analog output from the transmitter circuit;

FIG. 3A is a flow chart illustrating an exemplary embodiment of operation of receiving components of the power line carrier system;

FIG. 3B is a schematic diagram of an exemplary receiver circuit of a transceiver for use in the power line carrier system;

FIG. 4 is a chart illustrating an exemplary method of allocating data packets for transmission within the power line carrier system;

FIG. 5A is a first graph of timer waveforms used to perform frequency discrimination on a received signal, and an associated output;

FIG. 5B is a second graph of timer waveforms used to perform frequency discrimination on a received signal, and an associated output;

FIG. 6 is a block diagram of an exemplary distributed automation control system; FIG. 7 is a flow chart illustrating a high level method of operating the distributed automation control system;

FIG. 8 is a flow chart illustrating stimulus sources for events within the distributed automation control system;

FIG. 9 is a flow chart illustrating an exemplary method of generating an event message for distribution within the system;

FIG. 10 is a flow chart illustrating an exemplary method of transmitting an event message within the system;

FIG. 11 is a flow chart illustrating an exemplary method of receiving and unpacking an event message within the system; FIG. 12 is a flow chart illustrating an exemplary method of actioning an event message at a module within the system;

FIG. 13 is a flow chart illustrating an exemplary method of performing automated closed- loop control within the system;

FIG. 14 is a flow chart illustrating an exemplary method of performing automated cascaded closed-loop control within the system;

FIG. 15 is a flow chart illustrating an exemplary method of automatically controlling a lighting system including motion sensing;

FIG. 16 is a flow chart illustrating an exemplary method of automatically performing daylight harvesting; FIG. 17 is a flow chart illustrating an exemplary method of automatically controlling a HVAC system;

FIG. 18 is a flow chart illustrating an exemplary method of automatically controlling a vent system for temperature adjustment; FIG. 19A illustrates mapping of address words to the inputs and outputs of a module within the system;

FIG. 19B illustrates an example of mapping of address words to the inputs and outputs of a module within the system, and FIG. 20 is a block diagram of an exemplary configuration of a distributed automation control system.

DETAILED DESCRIPTION

FIG. 1A illustrates a power line carrier (PLC) system 100, in which a first transceiver 102a and a second transceiver 102b communicate over a power distribution network (PDN) 104, for example that of a private dwelling or a commercial building. The system 100 may have a range of applications, but it is envisaged that exemplary embodiments disclosed herein may be particularly suited to automation of a building - for example demand-side power management, or to operate devices within the building in response to user or automated input events. FIG. IB is a block diagram of an exemplary embodiment of the PLC system 100. For completeness, it should be appreciated that while the first transceiver 102a is described with reference to transmitting functions, and the second transceiver 102b with reference to receiving functions, each transceiver 102a, 102b may act as both a transmitter and receiver.

Generally, the first transceiver 102a is configured to generate a data packet in block 106, error correction encoding is performed in block 108, the data packet is output in accordance with a frequency modulation scheme in block 110, the resulting signal is filtered in block 112, and coupled to the PDN 104 in block 114.

The second transceiver 102b is configured to receive the transmitted signal though a coupling to the PDN 104 in block 116, filter the signal in block 118, optionally frequency shift the signal in block 120 and perform signal conditioning in block 122, decode the frequency modulation in block 124, perform error correction decoding in block 126, and read the resulting data packet in block 128.

Exemplary methods and circuits used in the transmission and receiving of the data packet are described in greater detail below.

An exemplary embodiment of transmission of the data packet from the first transceiver 102a is herein described with reference to FIG. 2A and FIG. 2B. In a first step 202, microcontroller 210 outputs a square wave in accordance with a binary Frequency-shift keyed (FSK) modulation scheme by driving a first switch 212a and a second switch 212b, in which the binary data of the data packet is transmitted as discrete frequencies (fi and / ₂ ). The output digital waveforms are complementary, with incorporated dead time. The dead time between the complementary waveform prevent shoot through on the first and second switches 212a and 212b, and may be used to reduce higher frequency harmonics. When the waveform is in the "HIGH" state, the midpoint of the first and second switches 212a and 212b is connected to V+ through first resistance 214. When in the "LOW" state, the midpoint is connected to V-. The maximum current injected (and monitored) into a subsequent filter circuit (c.f. transmission power) is controlled by the first resistance 214.

The resulting signal is passed through a bandpass filter in step 204 and coupled to the PDN 104 in step 206, with further filtering performed on the coupling side in step 208. The bandpass filter and coupler are realised in the same in the circuit illustrated in FIG. 2B. Referring to FIG. 2C, the bandpass filter attenuates the harmonics of the digital waveform 250 leaving predominately the fundamental frequency of sinusoidal form 252. The output of the filter is connected across the PDN 104.

In the example filter circuit, first inductance 216 (LI) and first capacitance 218 (CI), coupled through transformer 220 with second inductance 222 (L2) and second capacitance 224 (C2) are a series resonant circuit at the carrier frequency f _c (average of fi and / ₂ ). Third inductance 226 (L3) and third capacitance 228 (C3) form a 3 ^rd harmonic trap for the f _c . Fourth inductance 230 (L4) and fourth capacitance 232 (C4) form a parallel resonant circuit at f _c for the purpose of providing a barrier between the coupler circuit and other circuitry 234 powered from across fifth capacitance 236. = ^{fi + fi} ~ ^{1 1 1}

2 2π Ιϊχ θί 27rVZ2 x 2 2 L4 X 4

2π^Ι > x C3

It should be noted that second inductance 222 and fourth capacitance 232 in series with fifth capacitance 236 act as a low-pass filter to attenuate higher order harmonics.

An exemplary embodiment of receiving of the data packet with the second transceiver 102b is herein described with reference to FIG. 3A and FIG. 3B.

When the transceiver 102b is not transmitting, it is in receiver mode - i.e. monitoring the PDN 104 with both the first switch 212a and second switch 212b in an "OFF" state. Signals on the PDN are bandpass filtered in step 302, coupled to the receiver circuit in step 304, and bandpass filtered again in step 306 through the same two stage series resonance circuit used for transmission and described above with reference to FIG. 2A and FIG. 2B.

In the exemplary embodiment illustrated, the signal is frequency shifted in step 308 and filtered using an intermediate frequency filter in step 310. Referring to FIG. 3B, the signal is AC coupled via a resonant circuit (sixth capacitance 320, seventh capacitance 322, eighth capacitance 324 and fifth inductance 326) into a mixer circuit 328 with a local oscillator frequency A DC rail voltage is supplied by second resistance 330 and third resistance 332. The AC signal is decoupled by capacitance 324 and mixed with the waveform using third and fourth switches 334 and 336. The mixed frequency is set to the frequency of a subsequent intermediate frequency filter (IFF) 338 plus the carrier frequency for high-side injection (although it should be appreciated that in exemplary embodiments low-side injection may be used):

This frequency shift can be shown by expressing the desired signal frequency as the carrier frequency plus/minus the deviation frequency (Δ ):

The result of multiplying and frequency shift is a beat frequency fbeat = \f,n ^~ fs \ = \f IFF + fc ^~ fc ± 4 | = f _IFF ±

The beat frequency is then passed through the IFF 338 with a bandwidth (few) including the frequency deviation (Δ ), and excludes those frequencies outside: f _BW = K X 2Af

1 < K < 2

The resulting output is then amplified and digitized in step 312 by circuit 340. The output of the IFF 338 drives the base of a first common emitter amplifier 342 to boost the signal. Then the signal is AC coupled by ninth capacitance 344 into a second common emitter amplifier 346 to further boost the signal. In order to increase the selectivity of the second amplifier a series resonant circuit (at/ _/ff ), formed by sixth inductance 348 (L6) and tenth capacitance 350 (CIO), is connected from the emitter of the second common emitter amplifier 346 to the negative rail:

The output of the second common emitter amplifier 346 is connected to one terminal of a comparator 352 with the other terminal connected to the average of the output of the second common emitter amplifier 346. To average the output of the second common emitter amplifier 346 a low-pass filter 354, formed by fourth resistance 356 (R4) and eleventh capacitance 358 (Cll), is used with a frequency response of the filter ( ) is much lower than the IFF frequency {J _IFF ):

The output of the comparator 352 may optionally be passed through a filter 360 into the microcontroller 210 for decoding in step 314. The optional filter 360 is formed by fifth resistance 362 (R4) and twelfth capacitance 364 (Cll), having a frequency response (fe) much greater than the IFF frequency JIFF):

An exemplary embodiment of encoding and decoding of the data packet is herein described.

In an exemplary embodiment the microcontroller may pre-process the data-packet that is to be transmitted over the power distribution network with an encoding algorithm that embeds forward error correction and bit-shuffling.

In an exemplary embodiment a check-sum is first appended and a header attached to the front of the data packet. The resulting data packet is then expressed as a series of bit-matrices of dimension [n x w).

Data packet:

Next, each row in the bit-matrix (n x w) is multiplied by a generation matrix which carries the forward error correction (FEC) of dimension ((n + q) x n) to form a bit-matrix of ((n + q) x w).

Appended with FEC:

After which the bits are transposed into a binary array, and then bit-shuffled across bit-array ((n + q) x w) to form a binary sequence. \ \fl fl ^■■■ fl fl fl fl fl fl \

The q-bits of FEC carry redundant information that is used to help reconstruct corrupted data. Bit shuffling across the bit-array mitigates the risk of clusters of bits being corrupted, such as in the event of burst noise. The resulting bit-array defines the binary sequence of transmission frequencies [fi and / ₂ ). In front of the binary sequence, a pre-sequence (carrier time) at/i (or/ ₂ ) is transmitted for a duration T _c - where T _c is greater than the time required to transmit n-bits of data.

The encoding algorithm may be used with variable length data packets, and provides self- synchronising on the data packet header.

In an exemplary embodiment an anti-collision algorithm is used to time-sequence the injection of messages on the power distribution network. The algorithm allocates 5 time-slots (see FIG. 4) that are spaced apart more than the time taken to transmit the carrier (T _c ) and header [T eaderY-

^> T _C + T _header In an exemplary embodiment the time-slot selection is based upon a random assignment with priority scheduling, i.e. data packets are divided into groups with different priorities. Consequently data packets with higher priority are statistically transmitted sooner than those of a lower priority. The time-slots are synchronised to the end of an existing data packet being detected on the power distribution network, for duration of T _A , after which data packets are transmitted without delay: T _A = T _s x S

In an exemplary embodiment the digital waveform used to drive the transceiver circuit is generated by configuring a first timer (herein referred to as "TimerA") on the microcontroller as a complementary output-compare with a fixed duty cycle of 50%. The frequency is switched between fi and fi by adjusting TimerA's prescaler, thus preserving the 50% duty cycle property of the waveform. The process of switching frequency is performed by the Direct Memory Access (DMA) of the microcontroller, which is triggered by a second timer (herein referred to as "TimerB"). The period of TimerB set to the Bits Per Second (BPS) rate of the system. The automated function of the TimerA, TimerB and DMA require no software servicing to transmit the binary sequence of frequencies once the DMA has been loaded. When the transfer from the DMA is complete the receiver function (discussed further below) is restored.

In an exemplary embodiment, the decoding of data packets on the power distribution network may be performed by the microcontroller's discriminator algorithm. By discriminating the received digital frequency, the microcontroller reconstructs the original binary sequence, which is then decoded back into the original data packet.

In the exemplary embodiment described above, the received digital frequency is first passed through a digital frequency divider with the resulting event used to reset a first timer (TimerA) of the receiving transceiver. If the high selectivity circuitry described above is used, then the compare value (COMP1) is set corresponding to the period of the IFF frequency. Otherwise COM P1 is set to the carrier frequency, (see FIG. 5A and 5B):

When TimerA's counter reaches COM Pl the slaved second timer (TimerB) is reset. For frequencies greater than (fiFF, fc) TimerA is kept below COMPl and TimerB is never reset (i.e. remains high) - as illustrated in FIG. 5A. For frequencies less than ( _/ ) TimerB is repeatedly reset (i.e. remains low) - as illustrated in FIG. 5B.

The output compare of TimerB is passed into a hardware serial decoder via a low-pass filter that abates glitches. This configuration of the timers and serial decoders allows the microcontroller to perform the frequency-to-logic-to-data transforms without software servicing (neither interrupt nor non-interrupt).

In exemplary embodiments in which bit shuffling and error correction is performed, the output of the serial decoder is then reverse bit shuffled, then multiplied with the error-check matrix to determine which bits need flipping. The result gives the original data packet. The final step is to apply the checksum test for message integrity. For systems with Gaussian noise and short-duration transient noise the bit error rate (BER) and message error rate (M ER) can be reduced by transmitting repeat messages N times (N _rep eat)- Under these noise conditions the messages can be considered as statistically independent, therefore the probability of success (Psuccess) is one minus the product of successive failures, i.e.: Therefore the number of repeat messages (N) is;

MER ^N = l - P success

ln(l -^ ucce s)

]n(MER)

For example, if a system is to have a failure rate less than 1 in every 3,000 messages, then the probability of success is: r„..„, ^-^ - 0.999m

And if the system has a single message success rate of 10%, then number of repeat messages is four (4): ^ ^success )

ln( ER)

_ ln(l - 0.999666)

ln(0.l)

= 3.47

= 4

The efficacy of the system 100 implementing the encoding protocol described above with regard to channel utilization has been tested in comparison with a commercially available PLC transceiver (ST7538Q - manufactured by ST Microelectronics at the time of filing the application) operating with a baud rate of 4.8 kbps with a band width of 5 kHz. The test setup involved two transceiver circuits communicating over power-lines separated by an attenuator with a line-impedance of 10 Ω on each side. Noise was injected into the respective circuits using a GW INSTEK AFG-2125 arbitrary function generator. For Gaussian noise, the internal noise function generator was used, while for in-band noise the frequency sweep function was used with the output sweeping from 120 to 140 kHz in 1 ms.

At a transmission voltage of 2.25Vpp the communication reliability of system 100 at 60dB attenuation was measured at 99.2%. Under Gaussian noise conditions at a Signal-to-Noise-Ratio (SNR) of 6.2dB the channel utilisation was measured at 29.4%. For in-band noise conditions at a SNR of 8.7dB the channel utilisation was measured at 21.8%.

By way of comparison, for communication reliabilities greater than 97% the ST7538Q circuit was determined to have receiver sensitivity of 40dB (c.f. system 100 test result of greater than 60dB), Gaussian noise sensitivity to 0 dB (c.f. system 100 test result 10 dB), and in-band sensitivity less than OdB (c.f. system 100 test result of 30 dB). It should be appreciated that these test results are not intended to exclude the use of commercially available PLC transceivers in embodiments of the present disclosure, as illustrated below, but serve to demonstrate the potential efficacy of the transceiver and/or encoding techniques disclosed herein.

FIG. 6 illustrates a distributed automation control system 600 including a plurality of control modules 602a-n, including a first control module 602a and a second control module 602b. Each of the modules 602a, 602b includes a controller 604a, 604b in communication with a storage medium having a local database 606a, 606b. In the exemplary embodiment illustrated, each module 602a, 602b has a power line carrier (PLC) transceiver 608a, 608b - for example a FSK power line transceiver IC such as model number ST7538Q manufactured by ST Microelectronics at the time of filing the application, or the transceiver 102a, 102b substantially as described above. The PLC transceivers 608a, 608b are coupled by transmission circuits 610a, 610b and receiver circuits 612a, 612b to the transmission network 614 - for example the mains power supply (i.e. 230Vac) cabling of residential dwellings and commercial buildings.

It should be appreciated that while two modules 602a, 602b are illustrated in FIG. 6, and the system 600 is described herein as having a plurality of modules 602a-n, each module 602a-n may operate as a contained system - i.e. being able to action an event message that it has created.

Referring to FIG. 7, in response to an event input to one of the modules 602a-n in step 702, an event message is created in step 704 then transmitted over the network 614 in step 706. It should be appreciated that the transmission and subsequent receipt of the event message may be performed in accordance with the encoding and decoding techniques described above. The event message is received by all modules 602a-n (including the originating module) and unpacked in step 708, and then if the event message is determined as requiring an action from each module 602a-n an action will follow in step 710.

Referring to FIG. 8, in exemplary embodiments the stimulus 800 of step 702 may be a response to a manual input 802, for example one or more of: a mechanical button 804a, non-contact switch 804b, speech recognition 804c, motion sensing 804d, or obstructions sensing 804e. In exemplary embodiments the stimulus 800 may be a response to an automated input 806, for example one or more of: environmental sensors 808a, transducers 808b, processor generated stimulus 808c, or timer initiated stimulus 808d. FIG. 9 illustrates an exemplary method of generating the event message of step 704 in response to the stimulus. The local database 606 receives the stimulus and in step 900 determines whether the stimulus is recognized as requiring the generation of an event message. If so, a control byte and address word are retrieved based on the recognized stimulus in step 902, and a base structure for the event message is created in step 904. The base structure includes a header, the control byte, and the address word (from most significant bit to least significant bit).

In step 906, a determination is made from the control byte whether there are data bytes to be transmitted in the event message, and if so the data bytes [0..n] are retrieved in step 908 and appended to the base structure in step 910. A checksum is then added in step 912 to complete the event message.

After the event message has been created it is transmitted onto the network 614 in step 706. Referring to FIG. 10, a random time-slot is selected in step 1000. The event message then waits for the time-slot in step 1002, and then on checking that the transmission network is free in step 1004, is transmitted in step 1006. The event message can be repeated in step 1008 through N iterations for improved communication reliability.

FIG. 11 illustrates an exemplary method of receiving the transmitted event message in step 708. The software protocol reads the received byte in step 1100, and checks if the byte is that of a header in step 1102. Once the header has been received the following three bytes are read in step 1106: the control byte and address word. At this stage 1108 the base structure of the event message is received, and the control byte can be checked against the local database 606 to determine, in step 1110, the number of data bytes to be received in step 1112. In step 1114 the checksum is read, and if the checksum is determined to be correct in step 1116 then the event message is validated.

Referring to FIG. 12, once an event message has been validated the address word is identified in step 1200 and checked for a match in the local database 606 in step 1202. If there is a match then control byte and data bytes are referenced against the local database 606 in step 1204 to form an action in step 1206 to be applied to the received module 602a-n. If the action is determined as requiring a delay in step 1208, this is performed, else the action is carried out in step 1210.

In exemplary embodiments, the action may form part of open loop control of the module 602a-n, in which the action is carried out without monitoring the resulting output to feed back into control of that action.

FIG. 13 illustrates an exemplary method 1210a in which the action 1210 is a form of closed-loop control. The event message starts the control loop in step 1300, in which an input (e.g. a sensor) is monitored in step 1302. If the sensor value is determined as being greater than an upper limit retrieved from the local database 606 in step 1304, then a first response event message is generated in step 1306 reflecting this condition. The control loop has a loop time of n-seconds, and a wait time is applied in step 1308 before returning to monitoring the sensor in step 1302. If the sensor value is determined as being less than a lower limit retrieved from the local database 606 in step 1310, then a second response event message is generated in step 1312 reflecting this condition.

FIG. 14 illustrates an exemplary method 1210b in which the action 1210 is a form of cascaded control. The event message starts the control loop in step 1400, in which a first input (e.g. a first sensor) is monitored in step 1402. If the first sensor value is determined as being outside a limit retrieved from the local database 606 in step 1404, then a second input (e.g. a second sensor) is monitored in step 1406.

If the second sensor value is determined as being greater than an upper limit retrieved from the local database 606 in step 1408, a first response event message is generated in step 1410 reflecting this condition. If determined as being a closed loop in step 1412, the control loop has a loop time of n-seconds, and a wait time is applied before returning to monitoring the first sensor in step 1402. If the sensor value is determined as being less than a lower limit retrieved from the local database 106 in step 1414, then a second response event message is generated in step 1416 reflecting this condition.

FIG. 15 illustrates an exemplary method 1500 of automatically controlling a lighting system including motion sensing, in response to receiving an event message to do so. In step 1502 an illuminance sensor monitors light levels. Where the luminous flux per unit area (lux) is determined as being less than an limit retrieved from the local database 606 in step 1504, it may be desirable to turn lights on (or otherwise increase light levels). However, doing so may be energy inefficient if there are no people present requiring those lights. As such, a passive infrared (PI ) sensor is enabled in step 1506, and if motion is detected in step 1508 then an event message is generated in step 1510 to increase light levels. Where the luminous flux per unit area (lux) is determined as being greater than the limit in step 1504, the PIR sensor is disabled in step 1510.

FIG. 16 illustrates an exemplary method 1600 of automatically performing daylight harvesting, in response to receiving an event message to do so in step 1602. In step 1604 an illuminance sensor monitors light levels. Where the lux is determined in step 1606 as being less than a lower limit retrieved from the local database 606 in step 1606, an UP event message is generated in step 1608 to increase light levels. Else, where the lux is determined in step 1606 as being above the lower limit, a determination is made in step 1610 as to whether the lux is above an upper limit retrieved from the local database 606. If so, a DOWN event message is generated in step 1612 to decrease light levels. In any case, a wait time of n-seconds (for example, 10 seconds) is applied before looping back to monitoring the illuminance sensor in step 1604. FIG. 17 illustrates an exemplary method 1700 of automatically controlling a HVAC system, in response to receiving an event message to do so in step 1702. In step 1704 a C0 ₂ sensor monitors C0 ₂ levels. Where the C0 ₂ level is determined in step 1706 as being greater than an upper limit retrieved from the local database 606, an UP event message is generated in step 1708 to increase outside air ventilation rate. Else, where the C0 ₂ level is determined as being below the upper limit in step 1706, a determination is made in step 1710 as to whether the C0 ₂ level is less than a lower limit retrieved from the local database 606. If so, a DOWN event message is generated in step 1712 to decrease outside air ventilation rate in order to reduce energy costs associated with heating or cooling outside air. In any case, a wait time of n-seconds (for example, 900 seconds) is applied before looping back to monitoring the C0 ₂ sensor in step 1704. FIG. 18 illustrates an exemplary method 1800 of automatically controlling a vent system for temperature adjustment, in response to receiving an event message to do so in step 1802. In step 1804 a temperature sensor monitors air temperature. Where the temperature is determined in step 1806 as being greater than an upper limit retrieved from the local database 606, an UP event message is generated in step 1808 to increase ventilation. Else, where the temperature is determined in step 1806 as being below the upper limit, a determination is made in step 1810 as to whether the temperature is less than a lower limit retrieved from the local database 606. If so, a DOWN event message is generated in step 1812 to decrease. In any case, a wait time of n-seconds (for example, 300 seconds) is applied before looping back to monitoring the temperature sensor in step 1804. Each module 602a-n may have a plurality of inputs and a plurality of outputs. As illustrated in FIG. 19A, address words may be mapped to each input (II, 12, In), and in exemplary embodiments a plurality of address words (Gl, G2, Gg) may be mapped to each output (01, 02, On). FIG. 19B illustrates an exemplary configuration in which a stimulus on the second input (12) will create an event message with an address word of "[002]". This address word is mapped to a number of outputs (02, 03, 04) to provide a group address, receipt of which will cause an action on each of those outputs. This may be used to action a scene in response to a single input. FIG. 20 illustrates an exemplary configuration of a distributed automation system 2000. Modules 2002a and 2002b are configured to generate event messages to cause an output on module 2002c, module 2002d is configured to generate event messages causing outputs on modules 2002e and 2002f, and module 2002g is configured to generate event messages causing outputs on modules 2002e and 2002h.

In this example, modules 2002a and 2002b have been configured to create event messages that module 2002c actions, i.e. the event messages have an address word matching that in the local database of module 2002c. Module 2002c can have multiple address words in its database, therefore the event messages of modules 2002a and 2002b do not necessary have the same address word. An exemplary application of modules 2002a-c is a system in which two switches (modules 2002a and 2002b) control a common light (module 2002c) in a hallway. With conventional wiring, the two switches and the light would be wired together. However, it would not be possible to add a third switch with conventional wiring, while the distributed automation system and its associated software protocol allows additional module(s) to be added without changing the existing modules or wiring.

FIG. 20 also illustrates two groups of modules: 1) modules 2002d-f, and 2) modules 2002g, 2002e and 2002h. In the first group, module 2002d transmits an event message to modules 2002e and 2002f, and in the second group module 2002g transmits an event message to modules 2002e and 2002h. In this configuration there is a common address word (i.e. a group address) between modules 2002h and 2002e and a different common address word between modules 2002e and 2002f. An exemplary application of this configuration is a case in which two switches (modules 2002d and 2002g) controlling three lights (modules 2002e, 2002f and 2002h), with one light (module 2002e) activated by either switch (modules 2002d or 2002g).

In this example, the output modules (2002e, 2002f and 2002h) can translate the event message differently through their respective local databases. For example, module 2000e can have a turn-off delay, and a different fade-rate to the others.

It should be noted that various changes and modifications to the presently preferred embodiments described herein will be apparent to those skilled in the art. Such changes and modifications may be made without departing from the spirit and scope of the invention and without diminishing its attendant advantages. It is therefore intended that such changes and modifications be included within the present invention. The invention may also be said broadly to consist in the parts, elements and features referred to or indicated in the specification of the application, individually or collectively, in any or all combinations of two or more of said parts, elements or features.

Where in the foregoing description reference has been made to integers or components having known equivalents thereof, those integers are herein incorporated as if individually set forth.

Aspects of the present invention have been described by way of example only and it should be appreciated that modifications and additions may be made thereto without departing from the scope thereof as defined in the appended claims.