TECHNICAL FIELD

The present disclosure relates to a power module, and more particularly, to a three-level power module with optimized pin layout.

BACKGROUND

Semiconductor power modules are widely used in industry. For example, such a power module may be used for the controlled switching of high currents and can be used in power converters (such as inverters) to convert DC to AC or vice versa, or for converting between different voltages or frequencies of AC. Such inverters are used in motor controllers or interfaces between power generation or storage, or a power distribution grid. For example, a power module may be used in a "grid tie" inverter of a battery storage system. In such a battery storage system, current is supplied to a power supply grid either to stabilize the grid or to provide electrical power during times where the grid electric energy is expensive, i.e. in the morning and in the afternoon. The batteries are recharged during night-time when grid energy cost is lower, or they can be recharged using solar power. Overall, the system helps the customer to reduce expenses for electrical energy. The "grid tie" inverter connects the battery storage system to the grid and has the task to convert the DC voltage of the battery to AC voltage for the grid and vice versa.

"Two-level" topologies, where DC power is supplied in a 2-conductor system (positive and negative voltages) are commonly used in many currently available inverters. This topology has the drawback of reduced efficiency and non-ideal sinusoidal current shape on the output of the inverters, requiring significant filtering effort.

SUMMARY

It is an object of the present disclosure to provide a power module with enhanced efficiency.

In a first aspect, a three-level power module comprises sets of one or more pins which are suitable for connecting to a positive Direct Current (DC) potential, a negative DC potential and a neutral potential, wherein at least one of pins suitable for connecting to the positive DC potential and at least one of pins suitable for connecting to the negative DC potential are each placed adjacent to a pin suitable for connecting to the neutral potential.

The term "three level" used here indicates that DC power is connected to the power module through connections carrying a positive voltage, a negative voltage and, in addition a third connection carrying an intermediate voltage (neutral), where the positive voltage is at a potential higher than that of the negative voltage, and the neutral connection is at a potential that is between the positive and negative voltages, and may be at zero potential in some embodiments. For example, inverter systems may use ±400 Volt, and a power supply to such an inverter comprises a positive voltage of +400V, a negative voltage of -400V, and also a neutral of OV. The neutral may be tied to ground.

In an embodiment, at least one pin of the positive DC potential is placed on a first side of the three-level power module and at least one pin of the negative DC potential is placed on a second side of the three-level power module opposite to the first side, and wherein at least one pin of the neutral potential is placed adjacent to the at least one pin of the positive DC potential on the first side and at least one pin of the neutral potential is placed adjacent to the at least one pin of the negative DC potential on the second side.

By "a first side that is opposite to a second side" is meant that if the first side is, for example, one of the long sides of a rectangular power module then the second side is the other long side of the power module, or if the first side is one of the short sides of the power module then the second side is the other short side of the power module. A pin placed adjacent to a pin on the same side means that the pins are placed at one and the same side of the power module, and next to each other. In an embodiment, the number of pins of each of the potentials that are placed adjacent to each other is higher than that needed for current carrying capability.

In an embodiment, the number of pins of each of the potentials that are placed adjacent to each other is twice that needed for current carrying capability. In an embodiment, there are four pins for each of the positive DC potential, the negative DC potential and the neutral potential.

In an embodiment, two pins of the neutral potential are placed adjacent to the four pins of the positive DC potential on the first side of the three-level power module, and two pins of the neutral potential are placed adjacent to the four pins of the negative DC potential on the second side of the three-level power module.

In an embodiment, the first side is opposite to the second side.

In an embodiment, the three-level power module further comprises at least one substrate on which one or more semiconductor switches are mounted, wherein the one or more semiconductor switches comprise wide-bandgap semiconductors. In an embodiment, the wide-bandgap semiconductors comprise Silicon Carbide semiconductor switches.

In an embodiment, the SiC semiconductor switches comprise SiC

Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs).

In an embodiment, the three-level power module comprises a Neutral Point Clamped-1 (NPC1 ) topology. The NPC1 topology is a known topology for three-level inverter circuits and comprises four switches in series between the positive and negative DC power lines. It is further described below.

In an embodiment, the three-level power module comprises a NPC2 topology. The NPC2 topology is a known topology for three-level inverter circuits and comprises two switches in series between the positive and negative DC power lines, and the load connection comprising the connection between these switches. In addition, two further switches, as a bi-directional switch, lie between the load connection and the neutral power line. It is also further described below.

In an embodiment, the at least one substrate comprises a Direct Bonded Copper (DBC) substrate. Such a substrate is formed by a copper/ceramic/copper sandwich, where a circuit structure may be created in the upper copper layer and which may be populated with semiconductor switches, capacitors and/or resistors as required to form a functioning circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages will be more apparent from the following description of embodiments with reference to the figures, in which:

Fig. 1 shows a cross section view of a power module according to an embodiment of the present disclosure;

Fig. 2 shows a perspective view of the power module according to the

embodiment of the present disclosure;

Fig. 3 shows a view of a power module with lid placed according to an

embodiment of the present disclosure;

Fig. 4 shows a symbolic representation of a power module with IGBT/Diode combination in an NPC1 three-level topology; Fig. 5 shows a symbolic representation of a power module with IGBT/Diode combination in an NPC2 three-level topology;

Fig. 6 shows a symbolic representation of a power module with SiC-MOSFETs in an NPC1 three-level topology;

Fig. 7 shows a symbolic representation of a power module with SiC-MOSFETs in an NPC2 three-level topology;

Fig. 8 shows a top view of an exemplary power module according to an

embodiment of the present disclosure;

Fig. 9 shows a comparison of two power modules with different pin layouts;

Fig. 10 shows a diagram of a circuit comprising a set of parallel inductors; Fig. 11 shows an example of a power module according to an embodiment of the present disclosure; and

Fig. 12 shows the view of the current paths in the power module shown in Fig. 11 .

DETAILED DESCRIPTION

The embodiments of the disclosure will be detailed below with reference to the drawings. It should be noted that the following embodiments are illustrative only, rather than limiting the scope of the disclosure.

References in the specification to "one embodiment," "an embodiment," etc.

indicate that the embodiment described may include a particular feature, structure, or characteristic, but it is not necessary that every embodiment includes the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

It shall be understood that although the terms "first" and "second" etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed terms.

The terminology used herein is for the purpose of describing particular

embodiments only and is not intended to be liming of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "has", "having", "includes" and/or "including", when used herein, specify the presence of stated features, elements, and/or components etc., but do not preclude the presence or addition of one or more other features, elements, components and/ or combinations thereof. In the following description and claims, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skills in the art to which this disclosure belongs.

Fig. 1 shows a cross section view of a power module 100 according to an embodiment of the present disclosure, and Fig. 2 shows a perspective view of the power module according to the embodiment of the present disclosure. As shown, the power module 100 according to an embodiment of the present disclosure comprises a copper baseplate 110 with two substrates 120 soldered on top of it. Direct Bonded Copper (DBC) substrates are used in the power module 100. The DBC substrates are formed by a sandwich of Cu 122 (for example, of 300μηη), Ceramics 124 (for example, AIN of 320μηη) and Cu 126 (for example, of 300μηη) where in the upper Cu layer 122 a circuit structure can be found that holds semiconductor switches 130, capacitors 150 and gate resistors 140. Aluminum bond wires 160 are used for the top-side connection of the die and for

interconnection with pins 210, including signal pins and power pins of the power module 100. The two DBC substrates are connected via bond wires 220. The power module 100 is encapsulated with a molded plastic frame 170 (holding the press-fit contact pins). It is filled with Silicone-gel 180. The frame is fixed by metal bushings 230. The power module 100 is closed by a plastic lid 300. Fig. 3 shows a view of the power module 100 with lid 300 in place.

During assembly of the power module, first the semiconductor switches, resistors and capacitors are soldered to the DBC substrate. Afterwards the substrate is pre-tested. The tested DBC is then soldered to a 3mm thick copper baseplate covered with nickel plating. Afterwards the plastic frame is mounted; this is done by bonding the frame to the baseplate using silicone glue. In addition, the frame and the base plate are fixed by metal bushings. Afterwards the pins and the substrates are connected in a second bonding step with bond wires. In the final step the module is filled with silicone-gel, the lid is mounted and the module is tested in regards to secure the electrical function. The soldering steps may be combined into a single soldering step in order to save process complexity and hence cost. The power module is designed to fulfill two major characteristics: High power conversion efficiency and high power density. Factors as lifetime, cost and quality are also taken into account. In order to achieve high power conversion efficiency, a three-level topology is used. By using a three-level topology, less external components (i.e. filters) are needed because the sine-waveform is reproduced better. At the same time, the overall system efficiency increases. Fig. 4 shows a symbolic representation of a power module 400 with conventional Silicon technology (mainly IGBT/Diode combination) in a Neutral Point Clamped (NPC)1 three-level topology. Fig. 5 shows a similar symbolic representation of a power module 500 with conventional Silicon technology (mainly IGBT/Diode combination) in an NPC2 three-level topology. As shown, there are additional freewheeling diodes D1 , D4, D5 and D6. The configurations require the discrete diode components in accompany with each of the semiconductor switches T1 ~4.

In an embodiment, high performance wide-bandgap semiconductors, such as Silicon Carbide (SiC) semiconductor switches may be used, as they generally outperform standard silicon based components, i.e. Insulated Gate Bipolar

Transistors (IGBT).

The wide-bandgap semiconductors (e.g., SiC semiconductor switches) have the characteristic to switch very fast, and therefore have lower switching losses than IGBTs. The wide-bandgap semiconductors, for example SiC

Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), have higher efficiency, and so the less cooling is needed compared with IGBTs.

The three-level topology may make use of the MOSFET intrinsic body diode, and thus no additional Si or SiC freewheeling diode is needed as it is the case in IGBT based three-level power module. Moreover, the SiC MOSFET needs less space on the substrate compared to equal rated IGBT. Therefore, higher power densities are possible.

Fig. 6 shows a symbolic representation of a power module 600 with

SiC-MOSFETs in a Neutral Point Clamped (NPC)1 three-level topology. Fig. 7 shows a similar symbolic representation of a power module 700 with Sic-MOSFETs in an NPC2 three-level topology. As shown, no additional freewheeling diodes are required in either power module. There are four semiconductors, T1-T4, and two substrates DBC1 and DBC2 inside the power module. No discrete diode component is used in accompany with each of the semiconductor T1-T4. The numerals 1-24 in the figure denote pin reference numbers of the power module.

Fig. 7 also shows that the semiconductors in the power module 700 form an NPC-2 topology circuit, which is split over the two substrates, DBC1 and DBC2. DBC1 holds a half-bridge circuit comprising T1 and T4, and DBC2 holds a bi-directional switch circuit comprising T2 and T3. That is, DBC1 holds two semiconductors that are connected in series between the positive and negative terminals of the power module, and the connection between T1 andT4 is connected to the load terminal of the power module. DBC2 holds two

semiconductors that are connected as a bi-directional switch between the neutral terminal and load terminal of the power module.

Fig. 8 shows a top view of an exemplary power module 800 according to an embodiment of the present disclosure. As shown, there are eight semiconductors, where T1-T4 are doubled compared with those shown in Fig. 7. DBC1 holds T1 and T4, and DBC2 holds T2 and T3. In other words, each transistor in Fig. 7 is realized by two transistors in parallel in Fig. 8. Similar as Fig. 7, the bond wires ringed denote the connection between the two DBC substrates. The numerals 1- 26 in the figure denote pin reference numbers of the power module.

Any current path in an electrical component such as a power module unavoidably has an inductance. Such parasitic inductances store energy, and have the effect of keeping the current constant by the use of this stored energy, as is well known in the field. This effect acts strongly against fast switching, since it prevents fast changes in current. It is therefore very important to reduce the amount of parasitic inductances if fast switching is desired. The current circuits within a power module, comprising the copper tracks, wire bonds and terminal connections, all contribute to parasitic inductance, and so great care needs to be taken when laying out such connections. The inductance is formed by a current flowing in a "loop" formed by conductors. The smaller the commutation loop for the current, the smaller is the inductance. By placing at least one of pins for the positive DC potential and the negative DC potential to be close to a pin for the neutral potential, the commutation loop of the current is reduced, which reduces the stray inductance in the power module. In an embodiment, the at least one pin for the positive DC potential is placed adjacent to the pin for the neutral potential. By placing the pin(s) for the positive DC potential and/or the negative DC potential close to the pin(s) for the neutral potential, the size of the commutation loop is reduced for the external DC-link capacitor connection. That also reduces the inductance. This placing of pins has the additional advantage that it is easier to connect to external capacitors in a way that has reduced stray inductance.

To have both contacts, for e.g. the snubber capacitors, close to each other also reduces the inductance from the power module to the capacitors. Additionally the complexity of the printed circuit board is reduced, because the electrical conductors are close to each other. So with the selected pin-out, the following can be achieved: lowest external inductance to DC-capacitors and the option to place capacitors directly at the pins.

Fig. 9 shows a comparison of two power modules with different pin layouts. In Fig. 9(a), the stray inductance is low as the commutation loop spanned by the conductors is small. Compared with the one shown in Fig. 9(a), the commutation loop shown in Fig. 9(b) has a longer loop line, and thus the power module has higher inductance, which will lead to a reduced module performance. As shown in Fig. 9(a), the pin of the positive DC potential is placed one side while the pin of the negative DC potential is placed at another side opposite to the side for the pin of the positive DC terminal and at least a pin of the neutral potential is placed adjacent to the pin of the positive DC potential at the same side as the pin of the positive DC potential, and at least a pin of the neutral potential is placed adjacent to the pin of the negative DC potential at the same side as the pin of the negative DC potential.

To have several paths for the DC current in the power module is also helpful in reducing the inductance. This can be seen from the known derivation of an inductance of a set of parallel inductors shown in Fig. 10, where the inductance of the circuit is calculated as the following equation:

" 1 1 1

> — =— +— + +

J I I I J (1 ) where L _ges is the total inductance, Li-L _N denote the inductance of each of the inductors L1-Ln.

From the foregoing equation, it can be seen that the more paths that are available in parallel, the lower is the inductance.

In an embodiment, the number of pins of each of the potentials is higher than that needed for current carrying capability. The number of possible paths for the DC current is increased by having more than one pin for each potential. That is, for the positive DC potential, neutral potential and negative DC potential of the power module, each potential comprises more than one pin.

The number of pins is usually chosen to take the required current. The calculation depends upon the type of pin required. For example for a press-fit pin a maximum of 40A per pin is usually allowed. For soldered pins it can be slightly higher, for example 45-50A. The embodiment illustrated in Fig. 11 uses press-fit pins. In this embodiment where the maximum expected current is 80 A, two pins would normally be used. However, increasing this number to four pins per power potential the stray inductance of the pins is reduced by around 50%. This follows from the equation (1 ) shown above, where increasing the number of paths decreases the stray inductance.

The basic rule is that doubling the number of pins reduces the inductance by half. There are limits, in practice, to how much pin numbers can be increased, since any particular packaging size will have limits to how many pins can be fitted in the space, and clearance and creepage distances also need to be taken into account in the calculation of the number of pins.

The main design consideration is generally to reduce the current loading of any one pin so that the lifetime of that pin and connections made to it, normally limited by the thermal cycling effects due to high currents, is designed to be greater than the lifetime limit imposed by other parts of the power module design. This design consideration often results in two pins, in order to carry the current over the full lifetime. According to an embodiment of the present disclosure, this pin number is increased to be larger than two, which increases the possible number of current paths. In an embodiment, the number of pins is double, i.e., increased from two to four, which will reduce the stray inductances by about 50%.

Fig. 11 shows an example of a power module according to an embodiment of the present disclosure. As shown, each of the positive DC potential and the negative DC potential has four pins (pins 19-22 for the positive DC potential and pins 3-6 for the negative DC potential), and pins of the positive DC potential are on the opposite side of the power module to pins of the negative DC potential. In order to minimize the commutation loop there are two pins for the neutral potential on each side of the power module. That enables the power module to have a very short commutation loop between positive DC potential and neutral potential and also between negative DC potential and neutral potential. Fig. 12 shows the view of the current paths in the power module shown in Fig. 11 , where the left one shows the current paths between the neutral potential and the negative DC potential and the right one shows the current paths between the neutral potential and the positive DC potential.

Additionally, by having pins of the neutral potential on either side of the module, as shown in Fig. 11 , the current sharing between the 4 pins is optimized and the length of the current path is reduced, which reduced the stray inductance. According to the disclosure, having several short current paths between the

DC-link capacitor and the power module within a power inverter leads to very low stray inductances. With low stray inductances, switching speed can be increased. With increased switching speed the efficiency is higher. This is particular important for some applications, particularly for inverters.

Also, by having pins for the neutral potential adjacent to pins for the positive DC potential and also the negative DC potential, it allows for a simplified PCB layout when the power module is utilized. According to the disclosure, by dividing the current flow within and around the power module into several different parallel paths (with, for example, the use of a plurality of pins for the positive DC and negative DC potentials and neutral potential), the stray inductances are reduced as well as thernno-nnechanical stress on components. The disclosure has been described above with reference to embodiments thereof. It should be understood that various modifications, alternations and additions can be made by those skilled in the art without departing from the spirits and scope of the disclosure. Therefore, the scope of the disclosure is not limited to the above particular embodiments but only defined by the claims as attached.