Title:
POWER SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAME, AND POWER CONVERSION APPARATUS
Document Type and Number:
WIPO Patent Application WO/2021/100747
Kind Code:
A1
Abstract:
A power semiconductor device (100) which achieves miniaturization of an insulation substrate and which is capable of suppressing a connection failure is provided with: an insulation substrate (10); a semiconductor element (21); and a printed circuit board (30). The semiconductor element (21) is joined to one main surface of the insulated substrate (10). The printed circuit board (30) is joined so as to face the semiconductor element (21). A main electrode (21b) and a signal electrode (21c) are formed in the semiconductor element (21). The printed circuit board (30) includes a core material (31), a first conductive layer (32), and a second conductive layer (33). The second conductive layer (33) has a bonding pad (33a). A missing portion (36C) is formed in the printed circuit board (30). A metal pillar (51C) is disposed through the missing portion (36C) so as to reach the insulation substrate (10). The signal electrode (21c) and the bonding pad (33a) are connected via a metal wire (90). The metal pillar (51C) and the insulation substrate (10) are joined together.
Inventors:
ASAJI NOBUHIRO (JP)
OKADA KAZUYA (JP)
ISHIBASHI HIDETOSHI (JP)
OKADA KAZUYA (JP)
ISHIBASHI HIDETOSHI (JP)
Application Number:
PCT/JP2020/042948
Publication Date:
May 27, 2021
Filing Date:
November 18, 2020
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H01L25/07; H01L25/18
Domestic Patent References:
| WO2014185050A1 | 2014-11-20 | |||
| WO2013146212A1 | 2013-10-03 |
Foreign References:
| JP2019153607A | 2019-09-12 | |||
| JP2017199809A | 2017-11-02 | |||
| JP2019087700A | 2019-06-06 |
Attorney, Agent or Firm:
FUKAMI PATENT OFFICE, P.C. (JP)
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