POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A POWER SEMICONDUCTOR DEVICE

WIPO Patent Application WO/2022/136278

A3

A power semiconductor device (1) is described comprising: - a first main electrode (3), - a second main electrode (4), - a gate electrode layer (5) between the first main electrode (3) and the second main electrode (4), - a semiconductor layer stack (2) between and in electrical contact with the first main electrode (3) and the second main electrode (4), the semiconductor layer stack (2) comprising: - differently doped semiconductor layers, wherein at least two semiconductor layers differ in at least one of their conductivity type and their doping concentration, - a plurality of pillar-shaped or fin-shaped regions (20), which run through the gate electrode layer (5) and which each comprise a contact layer (21) arranged at the first main electrode (3) with a first doping concentration and with a first conductivity type, wherein each contact layer (21) extends to a side (5A) of the gate electrode layer (5) facing the first main electrode (3), the contact layers (21) of adjacent pillar-shaped or fin-shaped regions (20, 930) merge on the side of the gate electrode layer (5, 94) facing the first main electrode (3, 921) so that the contact layers (21) of adjacent pillar-shaped or fin-shaped regions (20, 930) are arranged continuously on the side of the gate electrode layer (5, 94) facing the first main electrode (3, 921).

WIRTHS STEPHAN (CH)
KNOLL LARS (CH)
MIHAILA ANDREI (CH)

PCT/EP2021/086803

August 04, 2022

December 20, 2021

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HITACHI ENERGY SWITZERLAND AG (CH)

H01L29/78; H01L21/336; H01L29/08; H01L29/16; H01L29/423

US5994735A	1999-11-30
US5323040A	1994-06-21
US20200111917A1	2020-04-09

EPPING HERMANN FISCHER PATENTANWALTSGESELLSCHAFT MBH (DE)

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