Title:
POWER SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME
Document Type and Number:
WIPO Patent Application WO/2022/259289
Kind Code:
A1
Abstract:
A problem has arisen in which peeling occurs between an insulating resin layer (14) and a sealing material (10) when the insulating resin layer (14) for mitigating electrolysis was provided and the entire device was sealed with the sealing material (10) because of the high electric field in the end section of a semiconductor chip (1) of a power semiconductor device. Therefore, the present invention is characterized in that the stress between the insulating resin layer (14) and the sealing material (10) is mitigated by providing the interval between said insulating resin layer (14) and sealing material (10) with: a stress-mitigating resin layer (15) for covering from the semiconductor chip (1) surface across the insulating resin layer (14) to the end surface of the semiconductor chip (1); and an adhesive resin layer (16) for covering from the surface of the semiconductor chip (1) across the entire surface of the stress-mitigating resin layer (15).
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Inventors:
SAWAKAWA MAO (JP)
MIYAJI YOSHITAKA (JP)
SHIOTA HIROKI (JP)
YAMATAKE ATSUSHI (JP)
MIYAJI YOSHITAKA (JP)
SHIOTA HIROKI (JP)
YAMATAKE ATSUSHI (JP)
Application Number:
PCT/JP2021/021499
Publication Date:
December 15, 2022
Filing Date:
June 07, 2021
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H01L23/29; H01L23/31; H01L25/07; H01L25/18; H01L29/861; H01L29/868
Foreign References:
| JP2004296906A | 2004-10-21 | |||
| JPH0870067A | 1996-03-12 | |||
| JPH02105471A | 1990-04-18 |
Attorney, Agent or Firm:
PALMO PATENT FIRM, P.C. (JP)
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