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Title:
POWER SEMICONDUCTOR DEVICE WITH A DOUBLE GATE STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2019/186126
Kind Code:
A1
Abstract:
We disclose herein a high voltage semiconductor device, comprising: a first semiconductor region; a drift region over the first semiconductor region, the drift region having a lower doping concentration than the first semiconductor region; at least two gate trenches extending from a surface into the drift region; a body region located over the drift region and between the at least two gate trenches; a contact region located in the body region, the contact region having a higher doping concentration than the body region, the body region adjoining the at least two gate trenches. The lateral distance between the at least two gate trenches or the width of the body region is selected such that when an on-state bias is applied between the at least two gate trenches and the contact region, channels from the respective gate trenches are joined together to form a single channel within the body region so as to enable an on-state carrier transport from the contact region to the first region through the single channel and the drift region.

Inventors:
UDREA, Florin (23 Babraham Road, Cambridge Cambridgeshire CB2 0RB, CB2 0RB, GB)
KANG, Hyemin (Electrical Engineering Department, University of Cambridge9 JJ Thomson Avenue, Cambridge Cambridgeshire CB3 0FA, CB3 0FA, GB)
Application Number:
GB2019/050841
Publication Date:
October 03, 2019
Filing Date:
March 25, 2019
Export Citation:
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Assignee:
CAMBRIDGE ENTERPRISE LIMITED (The Old Schools, Trinity Lane, Cambridge Cambridgeshire CB2 1TN, CB2 1TN, GB)
International Classes:
H01L29/78; H01L21/336; H01L29/10; H01L29/739
Domestic Patent References:
WO2000065646A12000-11-02
WO2005038927A12005-04-28
Foreign References:
US20080035992A12008-02-14
US20170365665A12017-12-21
EP0966763A11999-12-29
US20110018004A12011-01-27
DE19640308A11998-04-02
Other References:
KATOH SHUNSUKE ET AL: "High channel mobility double gate trench MOSFET", 2013 25TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & IC'S (ISPSD), IEEE, 15 June 2014 (2014-06-15), pages 167 - 170, XP032620442, ISSN: 1943-653X, ISBN: 978-1-4673-5134-8, [retrieved on 20140714], DOI: 10.1109/ISPSD.2014.6856002
Attorney, Agent or Firm:
MARKS & CLERK LLP (62-68 Hills Road, Cambridge Cambridgeshire CB2 1LA, CB2 1LA, GB)
Download PDF:
Claims:
CLAIMS:

1. A high voltage semiconductor device, comprising:

a first semiconductor region;

a drift region over the first semiconductor region, the drift region having a lower doping concentration than the first semiconductor region;

at least two gate trenches extending from a surface into the drift region;

a body region located over the drift region and between the at least two gate trenches;

a contact region located in the body region, the contact region having a higher doping concentration than the body region, the body region adjoining the at least two gate trenches; wherein the lateral distance between the at least two gate trenches or the width of the body region is selected such that when an on-state bias is applied between the at least two gate trenches and the contact region, channels from the respective gate trenches are joined together to form a single channel within the body region so as to enable an on-state carrier transport from the contact region to the first region through the single channel and the drift region.

2. A high voltage semiconductor device according to claim 1 , wherein the single channel in the body region substantially removes a depletion region adjacent the single channel in the body region.

3. A high voltage semiconductor device according to claim 1 or 2, wherein the carrier concentration in the single channel is the highest in a middle portion of the body region.

4. A high voltage semiconductor device according to claim 3, wherein the middle portion of the body region is distant from the interface between the gate trench and the body region.

5. A high voltage semiconductor device according to claim 3, wherein a peak carrier concentration in the single channel is shifted towards the middle portion of the body region by applying a quantum mechanical model.

6. A high voltage semiconductor device according to any preceding claim, wherein the body region comprises one layer or a plurality of layers stacked together.

7. A high voltage semiconductor device according to any preceding claim, wherein the body region comprises a further semiconductor layer sandwiched between two layers adjoining the gate trenches, wherein the further semiconductor layer having an opposite conductivity type than the two layers adjoining the gate trenches.

8. A high voltage semiconductor device according to claim 7, wherein the further semiconductor layer is configured such that, during an on-state, a depletion region is removed by an electric field from the trench gates and carriers flowing through the further semiconductor layer.

9. A high voltage semiconductor device according to claim 7 or 8, wherein the further semiconductor layer is configured such that, during an on-state, the charge of the single channel is reinforced by the pre-existing charge of the further semiconductor layer.

10. A high voltage semiconductor device according to claim 7, 8 or 9, wherein the further layer is configured such that, during an off-state, the body region is fully depleted by an electric field formed between the further semiconductor layer and the two layers adjoining the trench gates.

11. A high voltage semiconductor device according to claim 10, wherein a depletion region created by the electric field blocks current flow during the off- state operation.

12. A high voltage semiconductor device according to any preceding claim, wherein each gate trench is adjoined by a separate contact region or a same contact region.

13. A high voltage semiconductor device according to claim 12, comprising a further contact region between two contact regions adjoining the at least two gate trenches, the further contact region having an opposite conductivity type than the contact regions adjoining the at least two gate trenches.

14. A high voltage semiconductor device according to claim 13, wherein the further contact region extends in a third dimension of the high voltage semiconductor device.

15. A high voltage semiconductor device according to claim 13 or 14, wherein the further contact region extends continuously in the third dimension.

16. A high voltage semiconductor device according to claim 13 or 14, wherein the further contact region extends in periodic structures.

17. A high voltage semiconductor device according to any preceding claim, further comprising a punch through region directly underneath the body region and between two trench gates, the punch through region having a higher doping concentration than the body region.

18. A high voltage semiconductor device according to any preceding claim, comprising a further punch through region directly underneath each trench gate, the further punch through region extending into the drift region.

19. A high voltage semiconductor device according to any preceding claim, wherein the first region is of a first conductivity type and the drift region is of a second conductivity type opposite to the first conductivity type, and wherein the high voltage semiconductor device is an insulated gated bipolar transistor (IGBT).

20. A high voltage semiconductor device according to any one of claims 1 to 18, wherein the first region is of a second conductivity type and the drift region is of the second conductivity type, and wherein the high voltage semiconductor device is a metal oxide semiconductor field effect transistor (MOSFET).

21. A high voltage semiconductor device according to any preceding claim, wherein the first region is of a second conductivity type and the drift region comprises pillars or vertical stripes or cylinders of both the first and the second conductivity types, and wherein the high voltage semiconductor device is a super-junction semiconductor device.

22. A method of manufacturing a high voltage semiconductor device, the method comprising:

forming a first semiconductor region;

forming a drift region over the first semiconductor region; the drift region having a lower doping concentration than the first semiconductor region;

forming at least two gate trenches extending from a surface into the drift region;

forming a body region located over the drift region and between the at least two gate trenches;

forming a contact region located in the body region, the contact region having a higher doping concentration than the body region, the body region adjoining the at least two gate trenches;

wherein the lateral distance between the at least two gate trenches or the width of the body region is selected such that when an on-state bias is applied between the at least two gate trenches and the contact region, channels from the respective gate trenches are joined together to form a single channel within the body region so as to enable an on-state carrier transport from the contact region to the first region through the drift region.

23. A method according to claim 22, wherein forming the body region comprising sequential deposition or implantation or growth of the body region over the drift region and the first region and forming contact regions on the body region.

24. A method according to claim 23, further comprising using a dry etching technique to form patterned trenches.

25. A method according to claim 24, further comprising deposition or growth of an insulating layer to form trench gate oxides.

26. A method according to claim 25, further comprising deposition of a gate metal or a poly silicon layer.

Description:
POWER SEMICONDUCTOR DEVICE WITH A DOUBLE GATE STRUCTURE

Technical Field

The present disclosure relates to a power semiconductor device with adjoined gates with enhanced channel conductivity connected to a drift region. The power semiconductor device demonstrates a low on-state resistance.

Background of the Disclosure

Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and Insulated Gate Bipolar Transistors (IGBTs) are common types of power semiconductor devices. Their application areas range from portable consumer electronics, domestic appliances, electric cars, motor control and power supplies to RF and microwave circuits and telecommunication systems.

In power devices, the on-state voltage drop (V 0 N) for a given current density is the main parameter that defines the on-state performance. The specific on-state resistance is defined as the on-state voltage drop divided by the on-state current density. A low specific on-state resistance translates into lower on-state losses. The specific on-state resistance is the product between the on-state resistance and the active surface area of the device.

The on-state resistance of the device consists of several series resistances including channel resistance (RCH), drift resistance (R D ) and contact resistance (R C o)· In silicon technology, for high voltage rating, the channel resistance is often negligible (especially for higher voltages), as the drift resistance could be significantly higher than the channel resistance. However, in wide bandgap technology, such as silicon-carbide (SiC), for the same voltage rating, the drift region is more highly doped and shallower, and therefore the drift resistance can be orders of magnitude smaller. In addition, the channel resistance can be quite high, as the carrier surface mobility in SiC is significantly smaller than that in Silicon devices. Therefore, in wide bandgap devices the channel resistance can be as high, or higher than the drift resistance. The high channel resistance mainly originates from the poor quality of the interface between semiconductor and the insulating layer. In general, the semiconductor resistance can be defined as the multiplication of the carrier (electron or hole) concentration, carrier mobility and the sustained electric field. When carriers pass through the channel region close to the interface between semiconductor and insulator, the carrier mobility is highly affected by the interface quality as well as the transverse electric field. It is known that wideband gap semiconductors, such as SiC having poor quality interface have low mobility which yields high channel resistance, which affects the on-state losses.

As discussed, conventional power devices using wide bandgap material, especially silicon carbide (SiC), have been suffering from significantly lowered channel mobility due to the poor interface properties. This low mobility increases the overall on-state channel resistance of the device, thereby increasing on-state voltage drop and thus increasing the device losses when the device is operated a switch in a power electronic application. At the same time, the p body (for a n channel device) in wide bandgap devices has high concentration, to avoid punch-through. Its concentration also determines the threshold voltage. The high p body concentration results in high fixed charge present in the depletion region adjacent to the channel, when the gate is biased positively with respect to the source. This depletion region charge lowers the effective charge in the channel. Furthermore, the depletion region induces a high transversal electric field which is also responsible for directly reducing the mobility of the carriers (electrons for an n-channel device, holes for a p-channel device) in the channel.

Fig. 1 illustrates a known high voltage MOSFET 200. The device 200 includes n+ drain region 210 connected with a drain contact 205. A drift region 215 is formed over the drain region 210. On top of the drift region 215, there is provided a p-type body region 230 and a trench gate region (including a gate contact 225 and a gate insulator material 220). A contact region 235 is formed in the body region 230. A source contact 240 is formed on the contact region 235. When a positive bias is applied to the gate, with respect to the source contact, above the threshold voltage, electrons are attracted to the gate 220, 225 forming an electron inversion layer (or channel) as shown in FIG. 1. The peak density is formed directly near the insulator (as shown in the graph next to the schematic diagram of Fig. 1). According to the classical electrostatic theory, the peak of the electron inversion layer should be formed directly adjacent to the insulating layer. However, when a quantum mechanical model is applied to the channel, the peak of the inversion layer is shifted towards the semiconductor (Fig. 2). In any case, a depletion region exists, next to channel, where a high transverse electric field is present. The gate charge equates the channel charge plus the depletion region charge. Multiple cells or fingers with multiple gates or finger gates are used in known power devices to lower the on-state resistance and allow transport of carriers from the source to the drift region of the power device and eventually to the drain.

Fig. 2 illustrates a known alternative power MOSFET 300. Like the device of Fig. 1 , this device 300 also includes a drain contact 305, n+ drain region 310, n-type drift region 315, two trench gates 320, source contact regions 335 and a source contact 340. In prior art device of Fig. 2, when the width of the MESA (i.e. the width of the p- type body well/region 330) W, is wide, there is no interference between both channels (as shown in dashed region underneath the gate insulator 325), and a substantial depletion region is adjacent to each channel. This depletion region has a detrimental effect on the channel resistance as (i) it lowers the effective charge in the channel region, as part of the gate charge equates the depletion region charge, leaving less charge in the inversion layer and (ii) introduces a transverse electric field which further lowers the mobility in the channel. Joining two channels may be known in low-voltage devices, in the field of VLSI, as“volume inversion” and is characteristic to devices such as FIN FETs, but has never been applied and/or embedded in a high voltage, and/or in a wide bandgap device. While in FIN FETs, the length of the channel is very short (nanometer levels) in high voltage/power devices, the length of the channel is high (0.5 to 2 pm typically) and therefore the channel resistance is an important part of the overall on- state channel resistance of the power device.

Known documents include:

[1] B. Majkusiak, T. Janik, and J. Walczak,“Semiconductor Thickness Effects in the Double-Gate SOI MOSFET,” vol. 45, no. 5, pp. 1127-1134, 1998.

[2] F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa,“Double-Gate Silicon-on-lnsulator Transistor with Volume nversion : A New Device with Greatly Enhanced Performance,” vol. 8, no. 9, pp. 410-412, 1987.

[3] United States Patent US 2001/6475869 B1 , Advanced Micro Devices, Inc. February 26, 2001

[4] United States Patent US 2014/6787402 B1 , Advanced Micro Devices, Inc. April 27, 2001 [5] United States Patent US 2002/6630388 B2, Toshihiro, et al. March 13, 2002

Summary

Generally speaking, a power semiconductor device with a very narrow spacing between two adjacent MOS gates is disclosed herein. In one embodiment, a power device has a thin layer with a first conductive type (p-type) which is sandwiched by insulators and gate electrodes. As the width of the thin layer (or p-body well), termed MESA, decreases to nanometer levels (under 1 pm and preferably under 0.4 pm), the carrier density in the channels increases significantly and the channels are no longer located at the interface. The width of the MESA or body region is generally about 5nm to about 200nm. When the two channels from adjacent gates join, the depletion region is substantially (completely) eliminated, thus creating a conduction path closer to the middle of the thin layer. This conduction channel between adjacent gates connects to the drift region allowing in the on-state transport of carriers from the source to the drain via the drift region. In another embodiment, a power device has a preformed channel, in the form of a thin layer (or a further semiconductor region or layer) with a second conductive type (n-type), sandwiched by conductive layers of first conductive type (p- type) (adjoining the insulators), insulators, and gate electrodes. In all embodiments, since the conduction path is not at the interface and the depletion region is substantially or completely eliminated, this means that the carriers suffer less from interface scattering as well as less of mobility reduction to transversal fields in the depletion region. The increase in the charge density in the channel, due to the absence of the depletion region, less scattering and less influence of the transverse field, can be seen as a significant increase in the effective channel mobility. This disclosure can be applied to any power MOSFETs and super-junctions as well as Insulated Gate Bipolar Transistors (IGBTs) and is particularly applicable to devices built in wide bandgap materials such as SiC which are known to suffer from poor channel mobility. However, the disclosure/invention is equally applicable to Si based devices as well, and especially those where the channel resistance is still an important fraction of the total on-state resistance.

According to this disclosure a power semiconductor device featuring a drift region and with a very narrow spacing between two adjacent MOS gates is disclosed herein. The power device has a thin layer with a first conductive type (p-type) which is sandwiched by insulators and gate electrodes. As the width of the thin layer (or p-body well), termed MESA, decreases to nanometer levels (under 1 pm, and preferably below 0.4 pm), the carrier density in the channels increases significantly and the channels are no longer located at the interface. Moreover, the two channels can join, eliminating completely the depletion region and creating a path closer to the middle of the thin layer. This means that the carriers suffer less from interface scattering and are less exposed to transverse electric fields which are known to lower the mobility.

Given the very significant equivalent increase in the channel mobility (part being an effect of the carrier charge increase), the channel resistance can be reduced significantly. The effect could also be seen as the equivalent of a device with much higher channel mobility. In another embodiment of the disclosure, where a channel layer is pre-formed far from the interface, in the off-state (blocking mode), the n-type region is fully depleted by the adjacent p-type layers, using the depletion region from the p-n junctions created. In the on-state, once a certain gate potential is applied, the depletion region in the n-type layer is removed and channel current flows through the n-type pre-formed channel layer. Since the free carriers formed in n-type layers are not affected by the electric field induced by the gate electrode, and the channel is away from the interface, the channel mobility is virtually equivalent to the bulk level. This pre-formed channel is also enforced and modulated with inversion layer charge from the insulated gates.

According to one aspect of the present disclosure, there is provided a high voltage semiconductor device, comprising: a first semiconductor region; a drift region over the first semiconductor region, the drift region having a lower doping concentration than the first semiconductor region; at least two gate trenches extending from a surface into the drift region; a body region located over the drift region and between the at least two gate trenches; a contact region located in the body region, the contact region having a higher doping concentration than the body region, the body region adjoining the at least two gate trenches; wherein the lateral distance between the at least two gate trenches or the width of the body region is selected such that when an on-state bias is applied between the at least two gate trenches and the contact region, channels from the respective gate trenches are joined together to form a single channel within the body region so as to enable an on-state carrier transport from the contact region to the first region through the single channel and the drift region.

Generally speaking, the first semiconductor region (or the drain) is of a second conductivity type (or n-type) or of a first conductivity type (or p-type) for an IGBT. The drift region is of the second conductivity type. The body region is generally of the first conductivity type or the second conductivity type or a mixture of the first and second conductivity types. The contact region is of the second conductivity type (n-type). The drift region is generally lowly doped (e.g. E13 to E15 cm 3 ). The body region has higher doping concentration than the drift region, and the contact region has higher doping concentration than the body region. It will be understood that the trench gates are laterally spaced from one another and the body region is located in the lateral space between the two gates. The width of the lateral space between two gates is selected to be very thin (under nanometre level) so that channels from both gates can join together to form the single channel.

It will be understood that the present disclosure is particularly related to“high” voltage semiconductor devices which are also termed as power devices. It will be understood that the high voltage or power devices are operating in a range of voltage over 20V. The highest voltage range can vary depending on the exact device being used, but generally high voltage devices operate from a voltage from 20V to 20KV. It will be also appreciated that the high voltage semiconductor devices disclosed herein could be either based on silicon or silicon carbide materials. The high voltage devices disclosed are generally vertical power semiconductor devices in which carrier flows from the source/emitter region through the channel and the drift region to the drain/collector region in a vertical direction from the gate regions. The drift region is important for power devices because it is used to sustain the high voltage in the reverse conducting mode. Generally the presence of the drift region in a power device is an important difference between the power device and low voltage device (e.g. a CMOS device).

The single channel in the body region may substantially remove a depletion region adjacent the single channel in the body region. This increases charge density in the channel. During the blocking or off-state mode, the single channel can support the high voltage. The carrier concentration in the single channel may be the highest in a middle portion of the body region. This reduces scattering effect at the interface of the gate which in turn increases carrier mobility.

The middle portion of the body region may be distant from the interface between the gate trench and the body region. A peak carrier concentration in the single channel may be shifted towards the middle portion of the body region by applying a quantum mechanical model.

The body region may comprise one layer or a plurality of layers stacked together. When the body region has one continuous layer, then the body region may be of a first (p-type) or second (n-type) conductivity type or a combination of both first and second conductivity types.

The body region may comprise a further semiconductor layer sandwiched between two layers adjoining the gate trenches, wherein the further semiconductor layer having an opposite conductivity type than the two layers adjoining the gate trenches.

The further semiconductor layer may be configured such that, during an on-state, a depletion region is removed by an electric field from the trench gates and carriers flowing through the further semiconductor layer. The further semiconductor layer may be configured such that, during an on-state, the charge of the single channel is reinforced by the pre-existing charge of the further semiconductor layer.

The further layer may be configured such that, during an off-state, the body region is fully depleted by an electric field formed between the further semiconductor layer and the two layers adjoining the trench gates. A depletion region created by the electric field may block current flow during the off-state operation. In this particular example, the choice of width and impurity concentrations of the further semiconductor layer and the layers surrounding the further semiconductor layer (or n-type and the p-type layers respectively) between the insulated gates is important to reduce (or minimize) the on- state resistance when the device is ON, but also block the current flow during off-state forming a fully depleted region in the further semiconductor layer or the n-type layer (given by the field produced by the p-n junction action).

Each gate trench may be adjoined by a separate contact region or a same contact region. For example, one continuous contact region connects both gates or there are two separate contact regions each connecting to a trench gate. The high voltage semiconductor device may comprise a further contact region between two contact regions adjoining the at least two gate trenches, the further contact region having an opposite conductivity type than the contact regions adjoining the at least two gate trenches.

The further contact region may extend in a third dimension of the high voltage semiconductor device. The further contact region may extend continuously in the third dimension. The further contact region may extend in periodic structures.

The high voltage semiconductor device may further comprise a punch through region directly underneath the body region and between two trench gates, the punch through region having a higher doping concentration than the body region.

The high voltage semiconductor device may comprise a further punch through region directly underneath each trench gate, the further punch through region extending into the drift region. The further punch through region may have higher doping concentration compared to the doping concentration of the drift region. This has the advantage regarding the reliability of the insulated gates. It will be understood that the punch through region and the further punch through region are generally highly doped semiconductor regions to stop punch through breakdown in the high voltage device.

The first region may be of a first conductivity type (or p-type) and the drift region may be of a second conductivity type opposite to the first conductivity type, and the high voltage semiconductor device is an insulated gated bipolar transistor (IGBT).

The first region may be of a second conductivity type (or n-type) and the drift region is of the second conductivity type, and wherein the high voltage semiconductor device is a metal oxide semiconductor field effect transistor (MOSFET).

The first region may be of a second conductivity type and the drift region comprises pillars or vertical stripes or cylinders of both the first and the second conductivity types, and wherein the high voltage semiconductor device is a super-junction semiconductor device.

The novel features and advantages described in the present disclosure include:

- The device can effectively lower the channel resistance, R CH -

- The substantial or complete elimination of the depletion region between adjacent gates increases the charge density in the channel. - Narrow width of the p-body well increases the carrier’s mobility by lowering the scattering at the interface between semiconductor and insulator, less exposure to transverse electric fields (as the depletion region is eliminated).

- The adjacent gates with narrow gap to form a single conduction channel is connected to a drift region of lower conductivity to support the high voltage during the blocking mode or turn-off.

- In another embodiment a pre-formed channel is present and sandwiched between two p type regions and the insulated gates to further increase the mobility and reduce the channel resistance. In this particular embodiment, the choice of width and impurity concentrations of the p-type and the n-type layers between the insulated gates is important to minimize the on-state resistance when the device is ON but also block the current flow during off-state forming a fully depleted region in the n-type layer (given by the field produced by the p-n junction action).

According to a further aspect of the present disclosure, there is provided a method of manufacturing a high voltage semiconductor device, the method comprising: forming a first semiconductor region; forming a drift region over the first semiconductor region; the drift region having a lower doping concentration than the first semiconductor region;

forming at least two gate trenches extending from a surface into the drift region;

forming a body region located over the drift region and between the at least two gate trenches;

forming a contact region located in the body region, the contact region having a higher doping concentration than the body region, the body region adjoining the at least two gate trenches;

wherein the lateral distance between the at least two gate trenches or the width of the body region is selected such that when an on-state bias is applied between the at least two gate trenches and the contact region, channels from the respective gate trenches are joined together to form a single channel within the body region so as to enable an on-state carrier transport from the contact region to the first region through the drift region.

The method may comprise forming the body region comprising sequential deposition or implantation or growth of the body region over the drift region and the first region and forming contact regions on the body region.

The method may further comprise using a dry etching technique to form patterned trenches.

The method may further comprise deposition or growth of an insulating layer to form trench gate oxides.

The method may further comprise deposition of a gate metal or a poly silicon layer.

Brief Description of the Preferred Embodiments

Some preferred embodiments of the disclosure will now be described by way of example only and with reference to the accompanying drawings, in which:

Fig. 1 illustrates a known high voltage MOSFET;

Fig. 2 illustrates a known alternative power MOSFET;

Fig. 3 illustrates schematically a cross-sectional view of a vertical device with a single channel and adjoined gates according to one embodiment;

FIG.4 shows schematically a cross-sectional view of a power device according to one embodiment;

FIG.5 shows the simulated density of electron when the width of the p-body well is modified;

FIG.6 shows the simulation results of normalized effective electron mobility for different widths of the p-body well; FIG.7 shows the simulated specific channel resistance for different widths of the p-body well;

FIG. 8 shows schematically a cross-sectional view of an alternative vertical power device;

FIG. 9 shows the simulated transfer curve of a device schematically shown in Fig. 8;

FIG. 10 shows the simulated electron density of a device shown in Fig. 8;

FIG. 11 shows the simulated mobility of a device shown in Fig. 8;

FIG.12 shows schematically a cross-sectional view of a vertical device with multiple pair of adjacent gates;

Fig. 13 illustrates schematically a three-dimensional view of a vertical power device with adjacent gates and narrow spacing between the gates to form a single conductive channel;

Fig. 14 illustrates schematically a three-dimensional view of an alternative vertical power device with adjacent gates and narrow spacing between the gates to form a single conductive channel;

Fig. 15 illustrates schematically a three-dimensional view of an alternative vertical power device with adjacent gates and narrow spacing between the gates to form a single conductive channel;

Fig. 16 illustrates schematically a three-dimensional view of an alternative vertical power device with adjacent gates and narrow spacing between the gates to form a single conductive channel;

FIG.17 shows schematically a cross-sectional view of an alternative vertical device with adjacent gates and narrow spacing between the gates to form a single conductive channel; FIG.18 shows schematically a cross-sectional view of an alternative vertical device with adjacent gates and narrow spacing between the gates to form a single conductive channel;

FIG.19 shows schematically a cross-sectional view of an alternative vertical device with adjacent gates and narrow spacing between the gates to form a single conductive channel;

Fig. 20 shows a first step of manufacturing the device of Fig. 3;

Fig. 21 shows a second step of manufacturing the device of Fig. 3;

Fig. 22 shows a third step of manufacturing the device of Fig. 3; and Fig. 23 shows a fourth step of manufacturing the device of Fig. 3.

Detailed Description of the Preferred Embodiments

Fig. 3 illustrates schematically a cross-sectional view of a vertical device with a single channel and adjoined gates. Fig. 3 shows an example of a n-channel device (an n- channel power MOSFET), but the invention should also cover p-channel devices. The device 100 includes a drain contact 105, n+ drain region 110, n-type drift region 115, two trench gates 120 (with gate insulating layer 125), a p-type body region 130, source contact regions 135 and a source contact 340. The p-type body 130 region is also termed as a MESA region and the width of the MESA region 130 is termed as“W”. When a positive gate to source bias is applied, an electron inversion layer is formed on the interface of p-type body 130 and insulating layer 125. In the off-state, the device 100 behaves similarly to a power MOSFET. The junction responsible for blocking the voltage is between the p body region (MESA layer) 130 and the n- drift layer 115. The largest part of the voltage is sustained by the n- drift region 115. Given that the two adjacent insulated gates 125 are very close, and the gate electrode 120 is grounded during the off-state (blocking mode), the gates 120, 125 act as field plates pushing the voltage and the potential lines away from the p type body layer 130, more into the drift region 115. The close proximity of the two insulated gates 125 with the gates electrodes 120, helps to protect each-other against high electric fields at the corners of the trench (corners of 125).

The drift region 115 is designed to take the voltage. The doping and the thickness are adjusted so that the device meets or exceeds the rated breakdown voltage. If the device is made in wide bandgap material, such as SiC or GaN, the doping of the draft region 115 could be significantly higher (e.g. 100 x times higher) while the thickness could be lower (eg.10x lower).

As discussed, in the on-state, the device behaves similarly to a MOSFET. When the potential between the gate 120 and the source 140 is higher than a threshold voltage, the p-type body (or MESA region) 130 becomes inverted. According to the present disclosure, the channels coming from the two adjacent gates join in a single channel. Electrons flow from the source terminal 140 through the joint channel formed in the p layer (or p-type body) 130, through the drift region 115 to the drain region 110 and the drain terminal 105. According to this disclosure, the effective mobility of the joint channel (or the single channel) formed by inverting the p-type body layer 130 is increased and its charge is significantly higher than the charge of the two surface inversion layers in a prior-art traditional MOSFET. The result is a significantly reduced on-state resistance of the single channel and as a result a significantly lower total on- state resistance of the device.

FIG.4 shows schematically a cross-sectional view of a power device according to one embodiment. Many features of the device of Fig. 4 are the same as those in Fig. 3 and therefore carry the same reference numerals. The device 100 includes adjacent gates 125 and a narrow p-body well vertical device and its density of electron on the single channel when the device is ON (in the on-state). A single channel 132 is now present between the two gates 125 with no depletion region adjacent to it. In summary, according to the present disclosure, two adjacent gates 125 no longer form separate channels above the drift region 115 but a single channel 132, located in a thin layer (or thin p-type body) between the two gates 125. In this case, no depletion region exists and, as a result, the channel charge is significantly increased (see the graph next to the schematic diagram of FIG. 4). As the width of the p-body well, W, decreases, the inversion layers from the adjacent gates start to overlap. Since the total density of electron is the sum of each channel’s density of electron, the electron density of quantum mechanical model becomes higher with decreasing the width, W, as shown in FIG. 4. For low voltage devices Balestra et al [2], has shown that the inversion carriers (electrons) are confined at the center, when the width, W, is very thin and this is called“volume inversion”. Volume inversion can be modeled by Poisson-Schrodinger equation. However, no prior art exists in power devices or high voltage devices, and no prior art has been shown in wide bandgap (e.g. SiC based) power devices.

Generally speaking, the devices of Figs 3 and 4 can be summarised using the following features. A semiconductor device comprising at least some of the following regions and layers:

- a first region (n+ drain region) 110 of a second conductivity type at the bottom of the device;

a second region (n- drift region) 115 of a first conductivity type with low conductivity, which is responsible for blocking largely the voltage during the blocking mode or turn-off;

- a third region (the MESA region or the p-type body region) 115 of a second or first conductivity type, or a combination of first and second conductivity regions, spaced away from the surface and adjoining a higher region of the second region;

- a fourth region (n+ source) 135 of a second conductivity type adjoining a higher region of the third region 130;

- pairs of adjacent insulated gates 125 operated by a joint control electrode (not shown), and separated by a sub-micron distance; so that in operation, upon application of a suitable bias between the control electrode and the source electrode 140 connected to the fourth region, a single channel of the second conductivity type is formed between each pair of insulated gates 125, within the third region (or p-type body), the single channel 132 having no depletion region adjacent to it, and, where the single channel 132 joins the second region 115, to allow the on-state transport of carriers from the fourth region 135 to the first region 110 via the second region 115. FIG.5 shows the simulated density of electron when the width of the p-body well is modified. FIG. 5 also shows that by decreasing further W, the channel charge is further enhanced and the mobility is further increased.

FIG.6 shows the simulation results of normalised effective electron mobility for different widths of the p-body well.

FIG.7 shows the simulated specific channel resistance for different widths of the p-body well.

FIG. 8 shows schematically a cross-sectional view of an alternative vertical power device. Many features of Fig. 8 are the same as those in Fig. 3 and therefore carry the same reference numbers; except that the device of Fig. 8 has a pre-formed n-channel 845 adjoined by the p-type regions 130 and the insulated gates 125. In this embodiment, a channel layer 845 is pre-formed far from the interface. In off-state, the n-type region 845 is fully depleted by the adjacent p-type layers 130, using the depletion region form the p-n junctions created. In the on-state, once a certain gate potential is applied, the depletion region in the n-type layer is removed and channel current flows through the n-type layer 845. Since the free carriers formed in n-type layers 845 are not affected by the electric field induced by the gate electrode 125, and the channel is away from the interface, the channel mobility is virtually equivalent to the bulk level. This pre-formed channel is also enforced and modulated with inversion layer charge from the insulated gates 125.

Just like the device in Fig.3, in the off-state, the device of Fig. 8 behaves similarly to a power MOSFET. The junction responsible for blocking the voltage is between the p body (MESA) layer 130 and the n- drift layer 115. The largest part of the voltage is sustained by the n- drift region 115. Given that the two adjacent insulated gates 125 are very close, and the gate electrode 125 is grounded during the off-state (blocking mode), the gates act as field plates pushing the voltage and the potential lines away from the p-type body layer 130, more into the drift region 115. However, as opposed to the device in Fig. 3, a n-channel 845 is preformed and this needs to be depleted in the off-state and during turn-off for avoiding leakage current to flow from the source 135 to the drain 110. This channel 845 could be blocked by the action of the p-n 130, 845 junction. During the off-state, this junction should have an intrinsic depletion region which should deplete the pre-formed n channel 845. The doping concentrations of these layers 130, 845 should be chosen carefully to avoid leakage during the blocking mode and allow safe turning off. There is also a trade-off in this respect. For the off- state it would be advantageous to have higher doping in the p-type layer 130 to help the depletion of the n-type layer 845 (or the further semiconductor layer). For the on- state it would be best to have higher doping of the n-type layer 845. It is also possible to insert a narrow p layer (layer 1765) at the bottom of the layers 130/845 stack as shown in Fig. 17 to help with the leakage blocking. Alternatively, the 130/845 junction could also be reverse biased by an additional terminal, thus having separate contacts to the regions 130 and 845 (not shown). However, although possible, this would add complexity in the drive as the device would have four instead of three terminals.

In the on-state the pre-formed channel 845, together with the inverted channel helps to reduce the resistance of the channel. Depending on the gate voltage applied, the charge of the inversion layer could be greater or smaller than that of the pre-formed channel.

FIG. 9 shows the simulated transfer curve of a device schematically shown in Fig. 8.

FIG. 10 shows the simulated electron density of a device shown in Fig. 8.

FIG. 11 shows the simulated mobility of a device shown in Fig. 8.

FIG.12 shows schematically a cross-sectional view of a vertical device with multiple pair of adjacent gates. Many features of the device of Fig. 12 are the same as those in Fig. 3 and therefore carry the same reference numbers, except that in Fig. 12 there are three gates laterally spaced from one another. The additional gate components in this figure are 1220 and 1225.

Fig. 13 illustrates schematically a three-dimensional cross-sectional view of a vertical power device with adjacent gates and narrow spacing between the gates to form a single conductive channel. Many features of the device of Fig. 13 are the same as those in the device in Fig. 3, and therefore carry the same reference numbers. However, in Fig. 13, the p body well 130 can be contacted with a p+ stripe 1350 placed between two n+ contacts 135. The p+ stripe contacts 1350 can be placed in the third dimension. In this example, the trench gates 125 are laterally spaced in a first dimension, the current flows from the source 135 to the drain 105 in the second dimension transverse to the first dimension. The p+ stripes 1350 are extended in the third dimension in respect of the first and second dimensions defined above. In this example, the p+ stripes 1350 are periodically arranged in the third dimension and the n+ contacts 135 are joined together between two p+ stripes in the third dimension.

Fig. 14 illustrates schematically a three-dimensional cross-sectional view of an alternative vertical power device with adjacent gates and narrow spacing between the gates to form a single conductive channel. Many features of the device of Fig. 14 are the same as those in the device in Fig. 13, and therefore carry the same reference numbers. However, in Fig. 14, the p body well 130 can be contacted with a p+ stripe 1450 placed between two n+ contacts 135. In this example, the p+ stripe contacts 1450 are placed periodically between two n+ contacts 135 in the third dimension. There are no continuous n+ contacts 135 or p+ stripes 1450 in the third dimension.

Fig. 15 illustrates schematically a three-dimensional cross-sectional view of an alternative vertical power device with adjacent gates and narrow spacing between the gates to form a single conductive channel. Many features of the device of Fig. 15 are the same as those in the device in Fig. 13, and therefore carry the same reference numbers. However, in Fig. 15, the p body well 130 can be contacted with a p+ stripe 1550 placed between two n+ contacts 135. In this example, the p+ stripe contacts 1550 are placed between two n+ contacts 135 in the third dimension. In both second and third dimensions, the p+ stripe 1550 is a continuous layer between two continuous n+ contacts 130.

Fig. 16 illustrates schematically a three-dimensional cross-sectional view of an alternative vertical power device with adjacent gates and narrow spacing between the gates to form a single conductive channel. Many features of the device of Fig. 16 are the same as those in the device in Fig. 14, and therefore carry the same reference numbers. However, in Fig. 16, a p+ collector region 1655 and a collector contact 1660 are provided to form an Insulated Gate Bipolar Transistor (IGBT) instead of a MOSFET. On top of the p+ collector region 1655 there is provided a n+ buffer region 1620. The buffer region 1620 helps to stop punch-through breakdown. In the IGBT, the drift region’s conductivity is modulated by plasma formed of mobile carriers injected from the channel (electrons) and the p+ anode layer (holes) 1655.

FIG.17 shows schematically a cross-sectional view of an alternative vertical device with adjacent gates and narrow spacing between the gates to form a single conductive channel. Many features of the device of Fig. 17 are the same as those in the device in Fig. 3, and therefore carry the same reference numbers. However, in Fig. 17, a higher p+ layer 1765 is formed at the bottom of the p-body well 130 to prevent the punch - through.

FIG.18 shows schematically a cross-sectional view of an alternative vertical device with adjacent gates and narrow spacing between the gates to form a single conductive channel. Many features of the device of Fig. 18 are the same as those in the device in Fig. 3, and therefore carry the same reference numbers. The p-body well is now changed to an n-well 1830 and a higher p+ layer 1765 is formed at the bottom of the p- body well to prevent the punch -through as well as to give a positive threshold voltage (normally-off operation).

FIG.19 shows schematically a cross-sectional view of an alternative vertical device with adjacent gates and narrow spacing between the gates to form a single conductive channel. Many features of the device of Fig. 19 are the same as those in the device in Fig. 3, and therefore carry the same reference numbers. However, p+ layer 1970 are formed below the insulated gates 125 to avoid punch-through and help with the pushing of the electric field away from the insulated gates 125 towards the drift region 115. This has an advantage also regarding the reliability of the insulated gates.

The manufacturing steps of the devices discussed above are described in Figs. 20 to 23 below. Reference numerals in Figs. 20 to 23 are adapted from Fig. 13.

Fig. 20 shows the first step of manufacturing the device of Fig. 3. In the initial stage of manufacturing, the method comprises the following processing steps to form densely packed channel layers: sequential deposition/implantation/growth of p-type channel layer 130 and forming n+/p+ contact layers 130, 1350. Fig. 21 shows the second step of manufacturing the device. In this step, the gate trenches are made using a comb- shape pattern etching (using dry etching techniques). Fig. 22 shows the third step of manufacturing the device. In this step, deposition or growth of the insulating layer 125 is performed to form the gate oxides. Fig. 23 shows the fourth step of manufacturing the device. In this step, deposition of gate metal or poly silicon layer 120.

It will be appreciated that all doping polarities mentioned above could be reversed, the resulting devices still being in accordance with the present disclosure. In the present disclosure, generally the p-type doping polarity is referred as the first conductivity type and the n-type doping polarity is referred as the second conductivity type. However, the skilled person would be able to reverse them to form an appropriate device. The disclosure covers all the devices formed from the reverse doping polarities as well. Further, it will be appreciated that the source, trench gates, drain (for a MOSFET) or the emitter, collector and trench gate (for an IGBT) could be arranged to be out-of- plane or to be differently aligned so that the direction of the carriers is not exactly as described above, the resulting devices still being in accordance with the present invention.

The skilled person will understand that in the preceding description and appended claims, positional terms such as‘above’,‘overlap’,‘under’,‘lateral’,‘ver tical’, etc. are made with reference to conceptual illustrations of a semiconductor device, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a transistor when in an orientation as shown in the accompanying drawings.

Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.