Title:
POWER SEMICONDUCTOR MODULE
Document Type and Number:
WIPO Patent Application WO/2016/125363
Kind Code:
A1
Abstract:
In the present invention, leads 16a-16h are respectively connected to electrode pads 14a-14h disposed on the upper surface of a substrate 12. Power semiconductor elements 18a, 18b are respectively mounted on the electrode pads 14a, 14b. The leads 16a-16h, integrated together with a frame, are respectively connected to the electrode pads 14a-14h. At the distal end of each of the leads 16a-16h is formed a joining surface which has a surface area exceeding the surface area of the upper surface of a target electrode pad and which is joined to the upper surface of the target electrode pad.
Inventors:
KUDO KATSUMI (JP)
SATO TOMOHIKO (JP)
YAMADA MASAAKI (JP)
SATO TOMOHIKO (JP)
YAMADA MASAAKI (JP)
Application Number:
PCT/JP2015/081916
Publication Date:
August 11, 2016
Filing Date:
November 13, 2015
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H01L25/07; H01L23/50; H01L25/18
Domestic Patent References:
| WO2012114857A1 | 2012-08-30 |
Foreign References:
| JP2008135735A | 2008-06-12 | |||
| JPH0878619A | 1996-03-22 |
Attorney, Agent or Firm:
SAKAI, MASATOSHI (JP)
Boundary Masatoshi (JP)
Boundary Masatoshi (JP)
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