Title:
POWER SUPPLY WIRING STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2010/084533
Kind Code:
A1
Abstract:
A power supply wiring structure of a semiconductor integrated circuit has a single borderless stack via (20), which electrically connects together power supply wirings of two wiring layers different from each other and configures a wiring connecting section, and a multi-stack via (75), which functions as another wiring connecting section that electrically connects the power supply wirings and has a wide pad section. The single borderless stack via (20) is arranged in a wiring region having a high signal wiring density, and the multi-stack via (75) is arranged in a wiring region having a low signal wiring density. Thus, wiring efficiency in the region having the high signal wiring density is increased, wiring performance is improved and the area of a chip is reduced. Furthermore, compatibility with EDA tools is increased and IR-DROP is improved.
Inventors:
TAKESHIMA, Hideaki (())
Application Number:
JP2009/004119
Publication Date:
July 29, 2010
Filing Date:
August 26, 2009
Export Citation:
Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
International Classes:
H01L21/822; H01L21/82; H01L27/04
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (Osaka-Marubeni Bldg, 5-7Hommachi 2-chome, Chuo-ku, Osaka-sh, Osaka 53, 〒5410053, JP)
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