SUPERCONDUCTOR INTERCONNECT FABRICATION

RELATED APPLICATIONS

[0001] This application claims priority from U.S. Patent Application Serial No. 16/178306, filed 1 November 2018, which is incorporated herein in its entirety.

GOVERNMENT INTEREST

[0002] The invention was made under US Contract Number 30080984.

Therefore, the US Government has rights to the invention as specified in that contract.

TECHNICAL FIELD

[0003] The present invention relates generally to superconductors, and more particularly to a preclean and dielectric deposition methodology for superconductor interconnect fabrication.

BACKGROUND

[0004] Superconducting circuits are one of the leading technologies proposed for quantum computing and cryptography applications that are expected to provide significant enhancements to national security applications where communication signal integrity or computing power are needed. They are operated at temperatures <100 kelvin. Efforts on fabrication of superconducting devices have mostly been confined to university or government research labs, with little published on the mass producing of superconducting devices. Therefore, many of the methods used to fabricate

superconducting devices in these laboratories utilize processes or equipment incapable of rapid, consistent fabrication. Recently there has been a movement to mass producing superconducting circuits utilizing similar techniques as those utilized in conventional semiconductor processes. [0005] One well-known semiconductor process is the formation of contacts and conductive lines in a multi-level interconnect stack to couple devices to one another over different layers of an integrated circuit. One such fabrication process for formation of conductive contacts and lines is known as a dual damascene process. This technique has recently been attempted in the formation of superconducting circuits. During the fabrication of dual damascene superconducting circuits, via/trench structures are patterned, etched, filled with metal (e.g., niobium, tantalum, aluminum), then polished back using a chemical mechanical polishing (CMP) process. The next level dielectric is then deposited, and the sequence begins again, building up a multi-level interconnect stack. The CMP process and any exposure to oxygen prior to deposition of the next dielectric layer can result in oxidization of the conductive contacts and lines, which degrades performance.

SUMMARY

[0006] In one example, a method is provided of forming a superconductor device interconnect structure. The method comprises forming a first dielectric layer overlying a substrate and forming a superconducting interconnect element in the first dielectric layer. The superconducting interconnect element includes a top surface aligned with a top surface of the first dielectric layer to form a first interconnect layer. The

superconductor device interconnect structure is moved into a dielectric deposition chamber. The method further comprises performing a cleaning process on a top surface of the first interconnect layer in the dielectric deposition chamber to remove oxidization from a top surface of the first interconnect layer, and depositing a second dielectric layer over the first interconnect layer in the dielectric deposition chamber.

[0007] In another example, a method is provided of forming a superconductor device interconnect structure. The method comprises disposing a superconducting interconnect layer in a dielectric deposition chamber. The superconducting interconnect layer includes a superconducting contact or conductive line having a top surface aligned

? with a top surface of a first dielectric layer, wherein a top surface of the superconducting contact or conductive line has an oxidized layer, and the top surface of the first dielectric layer has an oxidized layer. Nitrogen trifluoride (NFa) gas is introduced into the dielectric deposition chamber with etch conditions set to induce a plasma clean etch with the NF3 gas for a predetermined time period to remove the oxidized layer from the superconducting contact or conductive line and the oxidized layer from the first dielectric layer. The NF3 gas is evacuated from the dielectric deposition chamber and a second dielectric layer is deposited over the superconducting interconnect layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 illustrates cross-sectional view of a superconducting device interconnect structure

[0009] FIG. 2 illustrates a schematic cross-sectional view of an example of a superconductor structure in its early stages of fabrication.

[0010] FIG. 3 illustrates a schematic cross-sectional view of the structure of FIG. 2 after a photoresist materia! layer has been deposited and patterned, and while undergoing an etch process in an etch chamber.

[0011] FIG. 4 illustrates a schematic cross-sectional view of the structure of FIG. 3 after the etch process and after the photoresist material layer has been stripped.

[0012] FIG. 5 illustrates a schematic cross-sectional view of the structure of FIG. 4 after a contact material fill in a materia! deposition chamber.

[0013] FIG. 6 illustrates a schematic cross-sectional view of the structure of FIG. 5 undergoing a chemical mechanical polish.

[0014] FIG. 7 illustrates a schematic cross-sectional view of the structure of FIG. 6 disposed in a dielectric deposition chamber undergoing a preclean process.

[0015] FIG. 8 illustrates a schematic cross-sectional view of the structure of FIG. 7 disposed in a dielectric deposition chamber undergoing an evacuation process. [0016] FIG. 9 illustrates a schematic cross-sectional view of the structure of FIG. 8 disposed in a dielectric deposition chamber undergoing a dielectric deposition process.

[0017] FIG. 10 illustrates a Secondary !on Mass Spectrometer (SIMS) data graph of oxide Depth versus Oxygen Concentration (atoms/CC).

DETAILED DESCRIPTION

[0018] The present invention is directed to a superconductor interconnect structure and a method for forming the same. The method incorporates a preclean process to remove oxide layers from superconducting metal interconnect elements (e.g., conductive lines, contacts) and the interlayer dielectric (ILD) surfaces prior to encapsulation of the metal interconnect elements in the next level of dielectric. The oxides can be as a result of a chemical mechanical process (CMP), and / or as a result of the exposure of the superconductor interconnect structure to oxygen outside of a vacuum environment. In one example, the method integrates a plasma preclean process into a dual damascene process for scaling into a high-density multilevel interconnect submicron technology. The method can employ a nitrogen trifluoride (NFS) gas based in-situ plasma preclean etch process prior to dielectric deposition of a next layer in the dual damascene process to assure a smooth clean surface of the metal interconnect elements and the !LD surface on the underlying layer.

[0019] In typical damascene superconducting fabrication architectures, oxide removal by etching of the metal interconnect oxide (typically niobium oxide) and ILD surface oxide utilizes either an etch chamber separate from the deposition chamber on the same mainframe so the transfer is done in vacuo or by utilizing an oxide etch chamber on a different mainframe whereby the wafer is transported between

mainframes. In either case, oxides form on the surfaces during the transfer even when transfers occur close to vacuum. [0020] A system and method are disclosed herein is to preclean by etching contaminants from a Silicon (Si), dielectric, or metal surface of a superconductor structure and the deposition of an overlying dielectric layer within a single dielectric deposition chamber. This process is of particular significance with respect to eliminating surface oxides prior to dielectric deposition of superconducting

interconnects. The removal of these surface oxides supports the following

improvements in a superconducting electronics fabrication process: eliminating oxygen sources from interface which can diffuse info superconducting metallization (e.g., Niobium) during subsequent processing and reduce interconnect critical current (lc) performance; eliminating unintended oxide layers during the deposition of Josephson Junction metallization which reduce the yield, uniformity, and repeatability of these structures; and the eliminating of high-loss interface oxides between dielectric material and superconducting traces which reduce the effective loss tangent of superconducting circuit elements.

[0021] In one example, a system is provided that includes a plasma enhanced chemical vapor deposition (PECVD) platform that is configured to support both an independent preclean process and dielectric deposition process in a single PECVD chamber. The Process of Record (FOR) uses two chambers 1 ) prec!ean chamber and 2) deposition chamber. This disclosure combines both the preclean and deposition process into a single chamber, which prevent any further oxidation from occurring during the transfer from an external etch chamber to a deposition chamber. The intention of the system and method of the present disclosure is to eliminate unintended oxidation by establishing the capability to etch surface oxides/contaminants and dielectric deposition in a single chamber. This technique eliminates exposing a clean wafer surface to the oxidizing environment prior to dielectric deposition, for example, in transfer/buffer chambers employed in cluster tools.

[0022] FIG. 1 illustrates cross-sectional view of a superconducting interconnect structure 10, for example, formed on a portion of a wafer. The superconducting interconnect structure 10 includes an active layer 14 overlying a substrate 12. The substrate 12 can be formed of silicon, glass or other substrate material. The active layer 14 can be a ground layer or a device layer. A first dielectric layer 16 overlies the active layer 14, and a second dielectric layer 18 overlies the first dielectric layer 16.

Both the first and the second dielectric layers 16 and 18 can be formed of a non-oxide based dielectric material. A first conductive line 20 is embedded in the first dielectric layer 16. A first conductive contact 22 extends from the first conductive line 20 at a first end to a second conductive line 24 in the second dielectric layer 18, and a second conductive contact 26 extends from the first conductive line 20 at a second end to a third conductive line 28 in the second dielectric layer 18. A third dielectric layer overlies the second conductive line 24, the third conductive line 28 and the second dielectric layer 18. Each dielectric layer can be formed of a non-oxide based dielectric, such as silicon nitride, amorphous silicon, or amorphous SiC.

[0023] Each of the contacts and conductive lines are formed of a

superconducting material, such as niobium. A cleaning process as described herein is performed prior to deposition of the third dielectric layer with both the cleaning process and the dielectric deposition process being performed in a single dielectric deposition chamber. A cleaning process can also be performed prior to deposition of the second dielectric layer 18 with both the cleaning process and the deposition of the second dielectric layer being performed in the same single dielectric deposition chamber.

[0024] Turning now to FIGS 2-9, fabrication is discussed in connection with formation of interconnects in the superconducting device of FIG. 1. It is to be

appreciated that the present example is discussed with respect to a process flow that starts with the formation of either a single or dual damascene layer of superconducting metal in an insulating dielectric. The present example will be illustrated with respect to a single damascene trench etched into a dielectric thin film to form a bottom conductive line followed by a dual damascene process to form top conductive lines. [0025] FIG. 2 illustrates a cross-sectional view of a superconductor structure 40 in its early stages of fabrication. The superconductor structure 40 resides in an etch chamber for forming vias and trenches in one or more dielectric layers. The

superconductor structure 40 includes an active layer 52, such as a ground layer or device layer, that overlays an underlying substrate 50. The underlying substrate 50 can be, for example, a silicon or glass wafer that provides mechanical support for the active layer 52 and subsequent overlying layers. A first dielectric layer 54 is formed over the active layer 52. Any suitable technique for forming the first dielectric layer 54 may be employed such as Low Pressure Chemical Vapor Deposition (LPCVD), Plasma

Enhanced Chemical Vapor Deposition (PECVD), High Density Plasma Chemical Vapor Deposition (HDPCVD), sputtering or spin-on techniques to a thickness suitable for providing an interconnect layer. Alternatively, the first dielectric layer 54 can be formed directly on the substrate 50 in examples in which the active layer 52 is omitted. A conductive line 56 resides within the first dielectric layer 54 and has a top surface that is flush with a top surface of the first dielectric layer 54. The conductive line 56 can be formed in a single damascene process, and goes through a cleaning process prior to deposition of the next dielectric layer.

[0026] The cleaning process is in situ plasma NF3 clean in a deposition chamber prior to the next dielectric layer 58 being deposited to remove any oxide from the surface of the conductive line 56. This process will be explained in further detail with reference to FIGS. 6-9. The second dielectric layer 58 overlies the first dielectric layer 54 and includes a pair of vias 60 that extend from a top surface of the second dielectric layer 58 to a top surface of the conductive line 56 that resides in the first dielectric layer 54. The dielectric material employed in the first dielectric layer 54 and the second dielectric layer 56 can be formed from a non-oxide based dielectric material. The pair of vias 60 were formed in a first portion of a dual damascene process. FIG. 3 illustrates a second portion of the dual damascene process. As illustrated in FIG. 3, a photoresist material layer 62 has been applied to cover the structure and patterned and developed to expose trench openings 64 in the photoresist material layer 62 in accordance with a trench pattern. The photoresist material layer 62 can have a thickness that varies in correspondence with the wavelength of radiation used to pattern the photoresist material layer 62. The photoresist material layer 62 may be formed over the second dielectric layer 58 via spin-coating or spin casting deposition techniques, selectively irradiated (e.g., via deep ultraviolet (DUV) irradiation) and developed to form the trench openings 64.

[0027] FIG. 3 also illustrates performing of an etch 200 {e.g., anisotropic reactive ion etching (RIE)) on the second dielectric layer 58 to form extended trench openings 68 (FIG. 4) in the second dielectric layer 58 based on the trench pattern in the photoresist material layer 62. The etch 200 can be a dry etch and employ an etchant which selectively etches the underlying second dielectric layer 58 at a faster rate than the underlying conductive line 56 and the overlying photoresist material layer 62. For example, the second dielectric layer 58 may be anisotropically etched with a plasma gas(es), herein carbon tetrafloride (CF ₄ ) containing fluorine ions, in a commercially available etcher, such as a parallel plate RIE apparatus or, alternatively, an electron cyclotron resonance (ECR) plasma reactor to replicate the mask pattern of the patterned of the photoresist material layer 62 to thereby create the extended trench openings 64. The photoresist material layer 62 is thereafter stripped {e.g., ashing in an O2 plasma) so as to result in the structure shown in FIG. 4.

[0028] Next, as illustrated in FIG. 5, the structure is placed into a material deposition chamber 1 10 and undergoes a contact material fill to deposit a

superconducting material 70, such as niobium, into the via openings 66 and the trench openings 68 to form the resultant structure shown in FIG. 5. The contact material fill can be deposited employing a standard contact material deposition. Following deposition of the contact material fill, the superconducting material 70 is placed into a polish chamber 120 and is polished via chemical mechanical polishing (CMP) down to the surface level of the dielectric layer 58 to form conductive lines 74 and contacts 72 that form part of the metal interconnects and provide the resultant structure of FIG. 6.

[0029] However, during the CMP process, an oxide surface 76 may grow on the surface of the metal to a thickness of approximately 70 A, and remain after the CMP process is complete. This oxide grows, for example, due to the presence of ammonium hydroxide and hydrogen peroxide in the CMP process !n the case where niobium is employed as the metal, a niobium oxide is formed. The presence of this niobium oxide will degrade the performance of the superconducting circuits (losses in the metal lines), so it needs be removed prior to the deposition of the next dielectric layer. A silicon oxide is formed on the deposited dielectric surface (e.g., on silicon nitride). The presence of this niobium oxide and silicon oxide will degrade the performance of the superconducting circuits through a variety of RF loss mechanisms typically associated with amorphous oxides so it needs to be removed prior to the deposition of the next dielectric layer.

[0030] The resultant structure is then placed into a dielectric deposition chamber 130 to undergo a precleaning process followed by a vacuum process and a dielectric deposition process, as illustrated in FIGS. 7-9. The resultant structure could have an oxidized surface layer on the superconducting material due to its exposure to oxygen when being removed from the CMP chamber to the dielectric deposition chamber, or an oxidized layer in addition to the oxide layers formed from the CMP process. The purpose of the precleaning process is to remove these oxide layers from the metal interconnect surfaces and the top surface of the dielectric layer prior to their encapsulation in the next level dielectric layer.

[0031] As illustrated in FIG. 7, the dielectric deposition chamber 130 includes an Argon source 330 that provides Argon (Ar) gas into the dielectric deposition

chamber 130 at a flow rate based on an Argon flow control device 340, and a nitrogen trifluoride (NFS) gas source 350 that provides NF3 gas into the dielectric deposition chamber 130 at a flow rate based on a NF3 flow control device 360. The dielectric deposition chamber 130 also includes a pressure controller 300 that sets the pressure inside the chamber 130, a RF power controller 310 that sets the power in the dielectric deposition chamber 130 and a temperature controller 320 that sets the temperature in the dielectric deposition chamber 130. In one example, the dielectric deposition chamber 130 is an Applied Materials DxZ plasma enhanced chemical vapor deposition (PECVD) chamber attached to a Centura mainframe. However, this process could be used in a number of different PECVD chambers that are properly configured with NFs gas and plasma capabilities.

[0032] In this example, the NFa plasma is a parallel plate and not a remote plasma. Plasma is directed from a top plate 131 to a bottom plate 133, which could be a chuck, that holds the wafer. Typically, remote plasma NF3 etches/cleans are used as chamber wall cleans and are not used as a process etch gas with a wafer present in the deposition chamber. However, it is possible to use remote NF3 plasmas for the preclean process as well.

[0033] In one example, the wafer moves through a transfer chamber to the dielectric deposition chamber 130. Once the wafer is in the dielectric deposition chamber 130, the gas flows and pressures are stabilized, then a plasma is ignited to perform the preclean process 220 that etches the oxides 78 that have formed on the surfaces of the ILD and the superconducting interconnect metal. A typical process condition utilizes an NF3 and Argon (Ar) gas mixture. Additionally, N2 can be added to the gas mixture. In one example, NF3 oxide preclean etch process conditions are as follows: NF3 flow is set to about 25 see to about 45 seem, Ar flow is set to about 1050 seem to about 1250 seem, N2 flow (if applicable) is set to about 0 to about 200 seem, power is set to about 700W, process pressure is set to about 1.5 Torr, and the process time is set to greater than 10 seconds. A representative etch rate is about 300 A/min to about 850 A/min with a typical process temperature set to about 400°C.

[0034] Once the NF3 preclean process is complete, the process gases are then pumped in a direction along arrow 78 by a pump 390, as shown in FIG. 8, to exhaust the gases to prepare the chamber 130 for the dielectric deposition process. In one example, all process gases are evacuated prior to the dielectric deposition process. In another example, only the NF3 and Ar gases are evacuated while the N2 gas continues to flow during the pumping process. A detail of note is that the wafer that was etched in the preclean process remains in the deposition chamber throughout the vacuum process and the subsequent dielectric deposition process. Typically, the vacuum process can take about 5 seconds to complete.

[0035] Next, as illustrated in FIG. 9, the wafer surface oxide 76 that was etched in the prec!ean process is encapsulated in a PECVD deposited dielectric layer 80 by undergoing a dielectric deposition process 230. This PECVD dielectric layer 80 could be silicon nitride, amorphous silicon, amorphous SiC, or any other non-oxide based PECVD deposited dielectric relevant to superconducting devices based on a

damascene architecture.

[0036] In previous techniques, the millitorr level vacuum in the transfer chamber of the wafer between a preclean process and a dielectric deposition process is sufficient to regrow a surface oxide on both the interconnect metal (i.e. Nb) and the ILD (i.e.

silicon nitride). Typically, this oxide is approximately a monolayer thick and can only be detected by a technique like secondary ion mass spectrometry (SIMS) where detection limits are below 0.1 % for oxygen. Techniques like x-ray photoelectron spectroscopy and energy dispersive x-ray spectroscopy are not sensitive enough to detect oxygen that is formed on the dielectric and metal surfaces during this in vacuo transport step.

[0037] FIG. 10 illustrates a Secondary Ion Mass Spectrometer (SIMS) data graph of oxide Depth versus Oxygen Concentration (atoms/CC). The SIMS data graph shows that the NFS pre-clean effectively removes the dielectric surface oxide to a comparable level as the current state of the art process or record (FOR) of utilizing two chambers and is effective when compared to doing no oxide etch.

[0038] What have been described above are examples of the invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the invention are possible. Accordingly, the invention is intended to embrace all such alterations, modifications, and variations that fall within the scope of this application, including the appended claims.