Title:
PREPARATION METHOD FOR SEMICONDUCTOR STRUCTURE, SEMICONDUCTOR STRUCTURE, AND SEMICONDUCTOR MEMORY
Document Type and Number:
WIPO Patent Application WO/2023/103139
Kind Code:
A1
Abstract:
The present disclosure provides a preparation method for a semiconductor structure, a semiconductor structure, and a semiconductor memory. The method comprises: providing a substrate; the substrate comprising an active region; sequentially depositing a first dielectric layer and a first barrier layer on the substrate; forming, on the first barrier layer, a first mask comprising a first etching pattern, wherein the first etching pattern comprises a groove extending in a first direction and evenly distributed etching holes, wherein the groove penetrates through the etching holes, and the depth of the etching holes is greater than that of the groove; and performing etching along the first etching pattern, removing the first barrier layer, and etching the first dielectric layer to form a conductive groove.
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Inventors:
YU YEXIAO (CN)
CHEN LONGYANG (CN)
LIU ZHONGMING (CN)
KONG ZHONG (CN)
CHEN LONGYANG (CN)
LIU ZHONGMING (CN)
KONG ZHONG (CN)
Application Number:
PCT/CN2022/070829
Publication Date:
June 15, 2023
Filing Date:
January 07, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L23/52; H01L21/768
Foreign References:
| US20100164114A1 | 2010-07-01 | |||
| US20130196477A1 | 2013-08-01 | |||
| CN110233152A | 2019-09-13 | |||
| US20100136781A1 | 2010-06-03 | |||
| CN102637646A | 2012-08-15 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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