Title:
PREPREG, LAMINATE, PRINTED CIRCUIT BOARD, AND SEMICONDUCTOR PACKAGE
Document Type and Number:
WIPO Patent Application WO/2019/112067
Kind Code:
A1
Abstract:
Provided is a prepreg which is capable of reducing warpage as a result of achieving reduced thermal expansion and increased elasticity without increasing the filling ratio of an inorganic filler, and in which void formation is suppressed. Specifically provided is a prepreg containing glass fibers and a thermosetting resin composition, wherein the prepreg includes a layer in which a plurality of glass fiber filaments are disposed extending in a substantially parallel manner in a single direction, and the thermosetting resin composition includes a maleimide resin. Additionally provided are a production method for said prepreg, a laminate containing the prepreg, a production method for said laminate, a printed circuit board containing the laminate, and a semiconductor package obtained by mounting a semiconductor element on said printed circuit board.
Inventors:
SHIMIZU MARI (JP)
FUJIMOTO DAISUKE (JP)
KOTAKE TOMOHIKO (JP)
TAKANEZAWA SHIN (JP)
SHIMIZU AKIRA (JP)
AOYAGI KOUICHI (JP)
FUJIMOTO DAISUKE (JP)
KOTAKE TOMOHIKO (JP)
TAKANEZAWA SHIN (JP)
SHIMIZU AKIRA (JP)
AOYAGI KOUICHI (JP)
Application Number:
PCT/JP2018/045310
Publication Date:
June 13, 2019
Filing Date:
December 10, 2018
Export Citation:
Assignee:
HITACHI CHEMICAL CO LTD (JP)
International Classes:
B29B15/08; C08J5/04
Foreign References:
| JPS4893698A | 1973-12-04 | |||
| JPH10508720A | 1998-08-25 | |||
| JP2003071836A | 2003-03-12 | |||
| JPH09323380A | 1997-12-16 | |||
| JPH03166233A | 1991-07-18 | |||
| JP2007262209A | 2007-10-11 |
Attorney, Agent or Firm:
HIRASAWA, Kenichi et al. (JP)
Download PDF: